[Cryptech-Commits] [core/math/modexp] 01/02: (1) Untangled the word index address generator from the product logic. (2) Updated the montprod TB to match changed FSM states in montprod.
git at cryptech.is
git at cryptech.is
Wed Jun 24 12:33:21 UTC 2015
This is an automated email from the git hooks/post-receive script.
joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.
commit 6a5d579475e1647744999373ce2f487175869a5d
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Wed Jun 24 14:22:07 2015 +0200
(1) Untangled the word index address generator from the product logic. (2) Updated the montprod TB to match changed FSM states in montprod.
---
src/rtl/montprod.v | 86 +++++++++++++++++++++++++++++++++++++++++-----------
src/tb/tb_montprod.v | 2 +-
2 files changed, 69 insertions(+), 19 deletions(-)
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index fa7c438..7276b4b 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -132,7 +132,13 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
+ reg word_index_we;
reg [(ADW - 1) : 0] word_index_prev_reg;
+ reg reset_word_index_lsw;
+ reg reset_word_index_msw;
+ reg inc_word_index;
+ reg dec_word_index;
+
reg [(ADW - 1) : 0] length_m1;
reg add_carry_in_sa_reg;
@@ -161,12 +167,13 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
wire shr_carry_out;
wire [(OPW - 1) : 0] shr_data_out;
- reg reset_word_index_lsw;
- reg reset_word_index_msw;
reg [(OPW - 1) : 0] sa_adder_data_in;
reg [(OPW - 1) : 0] muxed_s_mem_read_data;
+ // Temporary debug wires.
+ reg b_js;
+ reg pr_tt;
//----------------------------------------------------------------
@@ -253,13 +260,15 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
s_mem_we_reg <= s_mem_we_new;
s_mux_reg <= s_mux_new;
- word_index_reg <= word_index_new;
word_index_prev_reg <= word_index_reg;
shr_carry_in_reg <= shr_carry_in_new;
add_carry_in_sa_reg <= add_carry_in_sa_new;
add_carry_in_sm_reg <= add_carry_in_sm_new;
+ if (word_index_we)
+ word_index_reg <= word_index_new;
+
if (first_iteration_we)
first_iteration_reg <= first_iteration_new;
@@ -288,46 +297,74 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
//----------------------------------------------------------------
// prodcalc
+ //
+ // Logic to generate addresses and data selection
+ // for the OpA, OpM and Result memories.
//----------------------------------------------------------------
always @*
begin : prodcalc
opa_addr_reg = word_index_reg;
opb_addr_reg = b_word_index;
opm_addr_reg = word_index_reg;
- s_mem_addr = word_index_reg;
tmp_result_we = 1'b0;
-
result_addr_reg = word_index_prev_reg;
result_data_reg = s_mem_read_data;
-
if (montprod_ctrl_reg == CTRL_LOOP_ITER)
begin
opa_addr_reg = length_m1;
- s_mem_addr = length_m1;
end
if (montprod_ctrl_reg == CTRL_EMIT_S)
tmp_result_we = 1'b1;
+ end // prodcalc
+
+
+ //----------------------------------------------------------------
+ // word_index
+ //
+ // Logic that implements the word index used to drive
+ // addresses for operands.
+ //----------------------------------------------------------------
+ always @*
+ begin : word_index
+ word_index_new = {ADW{1'b0}};
+ word_index_we = 1'b0;
if (reset_word_index_lsw)
- word_index_new = length_m1;
+ begin
+ word_index_new = length_m1;
+ word_index_we = 1'b1;
+ end
- else if (reset_word_index_msw)
- word_index_new = {ADW{1'b0}};
+ if (reset_word_index_msw)
+ begin
+ word_index_new = {ADW{1'b0}};
+ word_index_we = 1'b1;
+ end
- else if (montprod_ctrl_reg == CTRL_CALC_SDIV2)
- word_index_new = word_index_reg + 1'b1;
+ if (inc_word_index)
+ begin
+ word_index_new = word_index_reg + 1'b1;
+ word_index_we = 1'b1;
+ end
- else
- word_index_new = word_index_reg - 1'b1;
- end // prodcalc
+ if (dec_word_index)
+ begin
+ word_index_new = word_index_reg - 1'b1;
+ word_index_we = 1'b1;
+ end
+ end // word_index
//----------------------------------------------------------------
// s_logic
+ //
+ // Logic to calculate S memory updates including address
+ // and write enable. This is where the main montprod
+ // calculation is performed.
//----------------------------------------------------------------
always @*
begin : s_logic
@@ -338,7 +375,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
add_carry_in_sm_new = 1'b0;
s_mem_new = {OPW{1'b0}};
s_mem_we_new = 1'b0;
-
+ s_mem_addr = word_index_reg;
case (montprod_ctrl_reg)
CTRL_INIT_S:
@@ -346,6 +383,11 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
s_mem_we_new = 1'b1;
end
+ CTRL_LOOP_ITER:
+ begin
+ s_mem_addr = length_m1;
+ end
+
CTRL_CALC_ADD:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
@@ -461,6 +503,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
b_bit_index_we = 1'b0;
bq_we = 1'b0;
s_mux_new = SMUX_0;
+ dec_word_index = 1'b0;
+ inc_word_index = 1'b0;
reset_word_index_lsw = 1'b0;
reset_word_index_msw = 1'b0;
first_iteration_new = 1'b0;
@@ -485,6 +529,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
CTRL_INIT_S:
begin
+ dec_word_index = 1'b1;
+
if (word_index_reg == 0)
begin
loop_ctr_set = 1'b1;
@@ -519,7 +565,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
CTRL_CALC_ADD:
begin
- s_mux_new = SMUX_ADD;
+ s_mux_new = SMUX_ADD;
+ dec_word_index = 1'b1;
if (word_index_reg == 0)
begin
@@ -540,7 +587,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
CTRL_CALC_SDIV2:
begin
- s_mux_new = SMUX_SHR;
+ s_mux_new = SMUX_SHR;
+ inc_word_index = 1'b1;
if (word_index_reg == length_m1)
begin
@@ -571,6 +619,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
CTRL_EMIT_S:
begin
+ dec_word_index = 1'b1;
+
if (word_index_prev_reg == 0)
begin
ready_new = 1'b1;
diff --git a/src/tb/tb_montprod.v b/src/tb/tb_montprod.v
index 5e0a015..a162326 100644
--- a/src/tb/tb_montprod.v
+++ b/src/tb/tb_montprod.v
@@ -225,7 +225,7 @@ module tb_montprod();
begin : bq_debug
if (SHOW_BQ_DEBUG)
begin
- if (dut.montprod_ctrl_reg == dut.CTRL_L_CALC_SM)
+ if (dut.montprod_ctrl_reg == dut.CTRL_CALC_ADD)
$display("====================> B: %x Q: %x b_bit_index_reg: %x <=====================", dut.b_reg, dut.q_reg, dut.b_bit_index_reg);
end
end
More information about the Commits
mailing list