[Cryptech-Commits] [core/math/modexp] 01/01: Updated the 2r1w block memory to be operand size generic. Minor fix in 1r1w block memory.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 0fa3d4900e4eb9cbf69ba927eb5823ed560fe975
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Jun 23 11:17:49 2015 +0200

    Updated the 2r1w block memory to be operand size generic. Minor fix in 1r1w block memory.
---
 src/rtl/blockmem1r1w.v |  2 +-
 src/rtl/blockmem2r1w.v | 25 +++++++++++++------------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v
index edff8dd..6a28cc2 100644
--- a/src/rtl/blockmem1r1w.v
+++ b/src/rtl/blockmem1r1w.v
@@ -44,7 +44,7 @@
 
 module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
                    (
-                    input wire           clk,
+                    input wire                  clk,
 
                     input wire  [(ADW - 1) : 0] read_addr,
                     output wire [(OPW - 1) : 0] read_data,
diff --git a/src/rtl/blockmem2r1w.v b/src/rtl/blockmem2r1w.v
index 252764f..557e810 100644
--- a/src/rtl/blockmem2r1w.v
+++ b/src/rtl/blockmem2r1w.v
@@ -39,23 +39,24 @@
 //
 //======================================================================
 
-module blockmem2r1w(
-                    input wire           clk,
+module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
+                   (
+                    input wire                  clk,
 
-                    input wire  [07 : 0] read_addr0,
-                    output wire [31 : 0] read_data0,
+                    input wire  [(ADW - 1) : 0] read_addr0,
+                    output wire [(OPW - 1) : 0] read_data0,
 
-                    input wire  [07 : 0] read_addr1,
-                    output wire [31 : 0] read_data1,
+                    input wire  [(ADW - 1) : 0] read_addr1,
+                    output wire [(OPW - 1) : 0] read_data1,
 
-                    input wire           wr,
-                    input wire  [07 : 0] write_addr,
-                    input wire  [31 : 0] write_data
+                    input wire                  wr,
+                    input wire  [(ADW - 1) : 0] write_addr,
+                    input wire  [(OPW - 1) : 0] write_data
                    );
 
-  reg [31 : 0] mem [0 : 255];
-  reg [31 : 0] tmp_read_data0;
-  reg [31 : 0] tmp_read_data1;
+  reg [(OPW - 1) : 0] mem [0 :  (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] tmp_read_data0;
+  reg [(OPW - 1) : 0] tmp_read_data1;
 
   assign read_data0 = tmp_read_data0;
   assign read_data1 = tmp_read_data1;