[Cryptech-Commits] [core/math/modexp] 01/01: montprod now supports generic operand size.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit e509e5dcbbd9d875cfffdc8a6dfb915d959f5235
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Jun 23 10:53:28 2015 +0200

    montprod now supports generic operand size.
---
 src/rtl/montprod.v | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index ffee748..c50751b 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -233,8 +233,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         begin
           ready_reg           <= 1'b1;
           loop_ctr_reg        <= 13'h0;
-          word_index_reg      <= 8'h0;
-          word_index_prev_reg <= 8'h0;
+          word_index_reg      <= {ADW{1'b0}};
+          word_index_prev_reg <= {ADW{1'b0}};
           add_carry_in_sa_reg <= 1'b0;
           add_carry_in_sm_reg <= 1'b0;
           shr_carry_in_reg    <= 1'b0;
@@ -242,8 +242,8 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
           q_reg               <= 1'b0;
           s_mux_reg           <= SMUX_0;
           s_mem_we_reg        <= 1'b0;
-          s_mem_wr_addr_reg   <= 8'h0;
-          b_bit_index_reg     <= 5'h0;
+          s_mem_wr_addr_reg   <= {ADW{1'b0}};
+          b_bit_index_reg     <= {(13 - ADW){1'b0}};
           first_iteration_reg <= 1'b0;
           montprod_ctrl_reg   <= CTRL_IDLE;
         end
@@ -312,11 +312,11 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         tmp_result_we = 1'b1;
 
 
-      if (reset_word_index_lsw == 1'b1)
+      if (reset_word_index_lsw)
         word_index_new = length_m1;
 
-      else if (reset_word_index_msw == 1'b1)
-        word_index_new = 8'h0;
+      else if (reset_word_index_msw)
+        word_index_new = {ADW{1'b0}};
 
       else if (montprod_ctrl_reg == CTRL_CALC_SDIV2)
         word_index_new = word_index_reg + 1'b1;
@@ -332,11 +332,11 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
   always @*
     begin : s_logic
       shr_carry_in_new      = 1'b0;
-      muxed_s_mem_read_data = 32'h0;
-      sa_adder_data_in      = 32'h0;
+      muxed_s_mem_read_data = {OPW{1'b0}};
+      sa_adder_data_in      = {OPW{1'b0}};
       add_carry_in_sa_new   = 1'b0;
       add_carry_in_sm_new   = 1'b0;
-      s_mem_new             = 32'h0;
+      s_mem_new             = {OPW{1'b0}};
       s_mem_we_new          = 1'b0;
 
 
@@ -368,7 +368,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
         SMUX_ADD:
           begin
             if (first_iteration_reg)
-              muxed_s_mem_read_data = 32'h0;
+              muxed_s_mem_read_data = {OPW{1'b0}};
             else
               muxed_s_mem_read_data = s_mem_read_data;
 
@@ -383,7 +383,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
             else if (q_reg)
               s_mem_new = add_result_sm;
             else if (first_iteration_reg)
-              s_mem_new = 32'h0;
+              s_mem_new = {OPW{1'b0}};
             else
               s_mem_new = s_mem_read_data;
 
@@ -430,12 +430,12 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
      loop_ctr_we      = 1'b0;
      length_m1        = length - 1'b1;
 
-     b_bit_index_new  = 5'h1f - loop_ctr_reg[4:0];
-     b_word_index     = loop_ctr_reg[12:5];
+     b_bit_index_new  = (2**(13 - ADW) - 1) - loop_ctr_reg[(13 - ADW - 1) : 0];
+     b_word_index     = loop_ctr_reg[12 : (13 - ADW)];
 
      if (loop_ctr_set)
          begin
-           loop_ctr_new = {length, 5'b00000} - 1'b1;
+           loop_ctr_new = {length, {(13 - ADW){1'b0}}} - 1'b1;
            loop_ctr_we  = 1'b1;
          end
 
@@ -485,7 +485,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
 
         CTRL_INIT_S:
           begin
-            if (word_index_reg == 8'h0)
+            if (word_index_reg == 0)
               begin
                 loop_ctr_set      = 1'b1;
                 montprod_ctrl_new = CTRL_WAIT;
@@ -521,7 +521,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
           begin
             s_mux_new = SMUX_ADD;
 
-            if (word_index_reg == 8'h0)
+            if (word_index_reg == 0)
               begin
                 reset_word_index_lsw = 1'b1;
                 montprod_ctrl_new    = CTRL_STALLPIPE_ADD;
@@ -571,7 +571,7 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
 
         CTRL_EMIT_S:
            begin
-             if (word_index_prev_reg == 8'h0)
+             if (word_index_prev_reg == 0)
                begin
                  ready_new         = 1'b1;
                  ready_we          = 1'b1;