[Cryptech-Commits] [core/math/modexp] 01/01: Changed blockmem1r1w used in montprod to generic data and address widths. Updated instantiation to use generics.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 5a0a6f87f2f63f9f1044725db0cac212c63f1fd6
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Jun 22 22:12:20 2015 +0200

    Changed blockmem1r1w used in montprod to generic data and address widths. Updated instantiation to use generics.
---
 src/rtl/blockmem1r1w.v | 20 ++++++++++++--------
 src/rtl/montprod.v     | 19 +++++++++----------
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v
index 1d84369..edff8dd 100644
--- a/src/rtl/blockmem1r1w.v
+++ b/src/rtl/blockmem1r1w.v
@@ -7,6 +7,9 @@
 //
 // The memory is used in the modexp core.
 //
+// paremeter OPW is operand word width in bits.
+// parameter ADW is address width in bits.
+//
 //
 // Author: Joachim Strombergson
 // Copyright (c) 2015, NORDUnet A/S All rights reserved.
@@ -39,19 +42,20 @@
 //
 //======================================================================
 
-module blockmem1r1w(
+module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
+                   (
                     input wire           clk,
 
-                    input wire  [07 : 0] read_addr,
-                    output wire [31 : 0] read_data,
+                    input wire  [(ADW - 1) : 0] read_addr,
+                    output wire [(OPW - 1) : 0] read_data,
 
-                    input wire           wr,
-                    input wire  [07 : 0] write_addr,
-                    input wire  [31 : 0] write_data
+                    input wire                  wr,
+                    input wire  [(ADW - 1) : 0] write_addr,
+                    input wire  [(OPW - 1) : 0] write_data
                    );
 
-  reg [31 : 0] mem [0 : 255];
-  reg [31 : 0] tmp_read_data;
+  reg [(OPW - 1) : 0] mem [0 : (ADW ** 2 - 1)];
+  reg [(OPW - 1) : 0] tmp_read_data;
 
   assign read_data = tmp_read_data;
 
diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 0bfd3c8..465fa38 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -4,7 +4,7 @@
 // ---------
 // Montgomery product calculator for the modular exponentiantion core.
 //
-// paremeter OPW is operand word width in bits.
+// parameter OPW is operand word width in bits.
 // parameter ADW is address width in bits.
 //
 //
@@ -186,15 +186,14 @@ module montprod #(parameter OPW = 32, parameter ADW = 8)
   //----------------------------------------------------------------
   // Instantions
   //----------------------------------------------------------------
-  blockmem1r1w s_mem(
-                     .clk(clk),
-                     .read_addr(s_mem_addr),
-                     .read_data(s_mem_read_data),
-                     .wr(s_mem_we_reg),
-                     .write_addr(s_mem_wr_addr_reg),
-                     .write_data(s_mem_new)
-                    );
-
+       blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
+                                                  .clk(clk),
+                                                  .read_addr(s_mem_addr),
+                                                  .read_data(s_mem_read_data),
+                                                  .wr(s_mem_we_reg),
+                                                  .write_addr(s_mem_wr_addr_reg),
+                                                  .write_data(s_mem_new)
+                                                 );
 
   adder32 s_adder_sm(
                      .a(muxed_s_mem_read_data),