[Cryptech-Commits] [core/math/modexp] 03/03: Adding mux to allow integrating s_mem init with main adder loop.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 10d0d1e670f266a7bf11e7d532148b90aaf7f591
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Jun 22 11:35:08 2015 +0200

    Adding mux to allow integrating s_mem init with main adder loop.
---
 src/rtl/montprod.v | 39 ++++++++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index cd7d5a9..4f4a9aa 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -142,9 +142,9 @@ module montprod(
   reg          shr_carry_in_reg;
   reg          shr_carry_in_new;
 
-  reg first_iteration_reg;
-  reg first_iteration_new;
-  reg first_iteration_we;
+  reg          first_iteration_reg;
+  reg          first_iteration_new;
+  reg          first_iteration_we;
 
 
   //----------------------------------------------------------------
@@ -160,10 +160,11 @@ module montprod(
   wire          shr_carry_out;
   wire [31 : 0] shr_data_out;
 
-  reg          reset_word_index_lsw;
-  reg          reset_word_index_msw;
+  reg           reset_word_index_lsw;
+  reg           reset_word_index_msw;
 
-  reg [31 : 0] sa_adder_data_in;
+  reg [31 : 0]  sa_adder_data_in;
+  reg [31 : 0]  muxed_s_mem_read_data;
 
 
 
@@ -195,7 +196,7 @@ module montprod(
 
 
   adder32 s_adder_sm(
-                     .a(s_mem_read_data),
+                     .a(muxed_s_mem_read_data),
                      .b(opm_data),
                      .carry_in(add_carry_in_sm_reg),
                      .sum(add_result_sm),
@@ -339,9 +340,10 @@ module montprod(
   //----------------------------------------------------------------
   always @*
     begin : s_select_write
-      shr_carry_in_new = 1'b0;
-      s_mem_we_new     = 1'b0;
-      sa_adder_data_in = 32'h0;
+      shr_carry_in_new      = 1'b0;
+      muxed_s_mem_read_data = 32'h0;
+      s_mem_we_new          = 1'b0;
+      sa_adder_data_in      = 32'h0;
 
       case (montprod_ctrl_reg)
         CTRL_INIT_S:
@@ -376,10 +378,17 @@ module montprod(
 
         SMUX_ADD_SA:
           begin
+            if (first_iteration_reg)
+              muxed_s_mem_read_data = 32'h0;
+            else
+              muxed_s_mem_read_data = s_mem_read_data;
+
+
             if (q_reg)
                 sa_adder_data_in = add_result_sm;
             else
-              sa_adder_data_in = s_mem_read_data;
+              sa_adder_data_in = muxed_s_mem_read_data;
+
 
             if (b_reg)
               s_mem_new = add_result_sa;
@@ -475,8 +484,8 @@ module montprod(
                 ready_new = 1'b0;
                 ready_we  = 1'b1;
                 reset_word_index_lsw = 1'b1;
-                first_iteration_new  = 1'b1;
-                first_iteration_we   = 1'b1;
+//                first_iteration_new  = 1'b1;
+//                first_iteration_we   = 1'b1;
                 montprod_ctrl_new    = CTRL_INIT_S;
                 montprod_ctrl_we     = 1'b1;
               end
@@ -532,8 +541,8 @@ module montprod(
 
         CTRL_L_STALLPIPE_SA:
           begin
-            first_iteration_new  = 1'b0;
-            first_iteration_we   = 1'b1;
+//            first_iteration_new  = 1'b0;
+//            first_iteration_we   = 1'b1;
             montprod_ctrl_new    = CTRL_L_CALC_SDIV2;
             montprod_ctrl_we     = 1'b1;
             reset_word_index_msw = 1'b1;