[Cryptech-Commits] [core/platform/novena] 01/02: add support for verilator linting

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository core/platform/novena.

commit 6fde50c9dd78be8662f7e84833d5c696b087ab9a
Author: Paul Selkirk <paul at psgd.org>
Date:   Thu Jun 18 13:46:16 2015 -0400

    add support for verilator linting
---
 common/rtl/lint-dummy.v | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
 eim/build/Makefile      |  3 +++
 i2c/build/Makefile      |  3 +++
 3 files changed, 70 insertions(+)

diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v
new file mode 100644
index 0000000..9016622
--- /dev/null
+++ b/common/rtl/lint-dummy.v
@@ -0,0 +1,64 @@
+// dummy modules for Xilinx IP for verilator linting
+
+// The module definitions are ganked from
+// /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims. It would be easier
+// to run verilator with -I for that directory, but verilator really
+// doesn't like the Xilinx code.
+
+/*verilator lint_off UNDRIVEN*/
+/*verilator lint_off UNUSED*/
+
+module DCM_SP (
+	CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
+	CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS,
+	CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
+parameter real CLKDV_DIVIDE = 2.0;
+parameter integer CLKFX_DIVIDE = 1;
+parameter integer CLKFX_MULTIPLY = 4;
+parameter CLKIN_DIVIDE_BY_2 = "FALSE";
+parameter real CLKIN_PERIOD = 10.0;
+parameter CLKOUT_PHASE_SHIFT = "NONE";
+parameter CLK_FEEDBACK = "1X";
+parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+parameter DFS_FREQUENCY_MODE = "LOW";
+parameter DLL_FREQUENCY_MODE = "LOW";
+parameter DSS_MODE = "NONE";
+parameter DUTY_CYCLE_CORRECTION = "TRUE";
+parameter FACTORY_JF = 16'hC080;
+parameter integer PHASE_SHIFT = 0;
+parameter STARTUP_WAIT = "FALSE";
+output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
+output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
+output [7:0] STATUS;
+input CLKFB, CLKIN, DSSEN;
+input PSCLK, PSEN, PSINCDEC, RST;
+endmodule
+
+module BUFG (O, I);
+    output O;
+    input  I;
+endmodule
+
+module IBUFGDS (O, I, IB);
+    output O;
+    input  I, IB;
+endmodule
+
+module IOBUF (O, IO, I, T);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter integer DRIVE = 12;
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IFD_DELAY_VALUE = "AUTO";
+    parameter IOSTANDARD = "DEFAULT";
+    parameter SLEW = "SLOW";
+    output O;
+    inout  IO;
+    input  I, T;
+endmodule
+
+module FDCE (Q, C, CE, CLR, D);
+    parameter INIT = 1'b0;
+    output Q;
+    input  C, CE, CLR, D;
+endmodule
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 7bb4ffd..5fd3f2a 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -69,3 +69,6 @@ vfiles = \
 	../../../../math/modexp/src/rtl/shr32.v
 
 include xilinx.mk
+
+lint:
+	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
diff --git a/i2c/build/Makefile b/i2c/build/Makefile
index d881820..b383078 100644
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@ -46,3 +46,6 @@ vfiles = \
 	../../../../cipher/chacha/src/rtl/chacha_qr.v
 
 include xilinx.mk
+
+lint:
+	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v