[Cryptech-Commits] [core/math/modexp] 02/02: Combined case statements to make it easier to follow the sequences.

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joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 35c08fcc620a0b6118dc7ee2811475454cf5050b
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Jun 18 10:34:16 2015 +0200

    Combined case statements to make it easier to follow the sequences.
---
 src/rtl/montprod.v | 49 ++++++++++++++++---------------------------------
 1 file changed, 16 insertions(+), 33 deletions(-)

diff --git a/src/rtl/montprod.v b/src/rtl/montprod.v
index 8f2d012..f505d0c 100644
--- a/src/rtl/montprod.v
+++ b/src/rtl/montprod.v
@@ -331,44 +331,19 @@ module montprod(
   //----------------------------------------------------------------
   always @*
     begin : s_select_write
-      shr_carry_in_new = 1'b0;
-      s_mux_new        = SMUX_0;
-      s_mem_we_new     = 1'b0;
-      sa_adder_data_in = 32'h0;
-
-      case (montprod_ctrl_reg)
-        CTRL_INIT_S:
-          begin
-            s_mux_new    = SMUX_0; // write 0
-            s_mem_we_new = 1'b1;
-          end
-
-        CTRL_L_CALC_SA:
-          begin
-            //s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
-            s_mux_new    = SMUX_ADD_SA;
-            s_mem_we_new = b_reg | q_reg;
-          end
-
-        CTRL_L_CALC_SDIV2:
-          begin
-            //s = (s + q*M + b*A) >>> 1; s>>=1.  Takes (1..length) cycles.
-            s_mux_new     = SMUX_SHR;
-            s_mem_we_new  = 1'b1;
-          end
-
-        default:
-          begin
-          end
-      endcase
-
-      s_mem_new           = 32'h0;
+      sa_adder_data_in    = 32'h0;
+      shr_carry_in_new    = 1'b0;
       add_carry_in_sa_new = 1'b0;
       add_carry_in_sm_new = 1'b0;
+      s_mem_new           = 32'h0;
+      s_mem_we_new        = 1'b0;
 
       case (s_mux_reg)
         SMUX_0:
-          s_mem_new = 32'h0;
+          begin
+            s_mem_new = 32'h0;
+            s_mem_we_new = 1'b1;
+          end
 
         SMUX_ADD_SA:
           begin
@@ -384,6 +359,7 @@ module montprod(
 
             add_carry_in_sa_new = add_carry_out_sa;
             add_carry_in_sm_new = add_carry_out_sm;
+            s_mem_we_new = b_reg | q_reg;
           end
 
         SMUX_SHR:
@@ -391,6 +367,7 @@ module montprod(
             shr_data_in      = s_mem_read_data;
             s_mem_new        = shr_data_out;
             shr_carry_in_new = shr_carry_out;
+            s_mem_we_new  = 1'b1;
           end
 
         default:
@@ -483,6 +460,8 @@ module montprod(
 
         CTRL_INIT_S:
           begin
+            s_mux_new = SMUX_0;
+
             if (word_index_reg == 8'h0)
               begin
                 loop_ctr_set  = 1'b1;
@@ -517,6 +496,8 @@ module montprod(
 
         CTRL_L_CALC_SA:
           begin
+            s_mux_new = SMUX_ADD_SA;
+
             if (word_index_reg == 8'h0)
               begin
                 reset_word_index_lsw = 1'b1;
@@ -534,6 +515,8 @@ module montprod(
 
         CTRL_L_CALC_SDIV2:
           begin
+            s_mux_new     = SMUX_SHR;
+
             if (word_index_reg == length_m1)
               begin
                 montprod_ctrl_new = CTRL_L_STALLPIPE_D2;