[Cryptech-Commits] [core/math/modexp] 02/05: Fixed non trivial yet fairly short testcases.

git at cryptech.is git at cryptech.is
Tue Jun 16 13:57:54 UTC 2015
Previous message (by thread): [Cryptech-Commits] [core/math/modexp] 01/05: cleanup of s mem write control.
Next message (by thread): [Cryptech-Commits] [core/math/modexp] 03/05: Collapsed done. Removes one cycle from each montprod.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
This is an automated email from the git hooks/post-receive script.

joachim at secworks.se pushed a commit to branch perfopt
in repository core/math/modexp.

commit 3e96b4a8e59679b62419b2c696defa4dc0096e36
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Jun 16 11:41:57 2015 +0200

    Fixed non trivial yet fairly short testcases.
---
 src/tb/tb_modexp.v | 73 +++++++++++++++++++++++++++++++++++-------------------
 1 file changed, 48 insertions(+), 25 deletions(-)

diff --git a/src/tb/tb_modexp.v b/src/tb/tb_modexp.v
index c2ab7fb..ca2ad8d 100644
--- a/src/tb/tb_modexp.v
+++ b/src/tb/tb_modexp.v
@@ -816,10 +816,10 @@ module tb_modexp();
       stop_test_cycle_ctr();
 
       write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data); //TEMPLATE_EXPECTED_VALUES
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data);
 
       if (success !== 1)
         begin
@@ -843,18 +843,22 @@ module tb_modexp();
       $display("Test with e = 65537 and 64 bit modulus.");
 
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
 
       write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
 
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
 
-      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
-      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000002);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000003);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
 
       start_test_cycle_ctr();
 
@@ -865,8 +869,9 @@ module tb_modexp();
       stop_test_cycle_ctr();
 
       write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h419a024f, read_data);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdddf178e, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4132d8e17, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
 
       if (success !== 1)
         begin
@@ -890,22 +895,28 @@ module tb_modexp();
       $display("Test with e = 65537 and 128 bit modulus.");
 
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
 
       write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf5e8eee0);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc06b048a);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h964b2105);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h2c36ad6b);
 
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h956e61b3);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h27997bc4);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h94e7e5c9);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb53585cf);
 
-      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
-      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000004);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000005);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005);
 
       start_test_cycle_ctr();
 
@@ -916,10 +927,11 @@ module tb_modexp();
       stop_test_cycle_ctr();
 
       write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1e97bff8, read_data);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h60029e6e, read_data);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hedaef85e, read_data);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfb0c6562, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h9c6d322c, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h25ab8bd3, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4aa80100, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0f3a02c, read_data);
 
       if (success !== 1)
         begin
@@ -945,9 +957,18 @@ module tb_modexp();
       $display("Test with e = 65537 and 256 bit modulus.");
 
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
 
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf169d36e);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbe2ce61d);
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hc2e87809);
@@ -958,6 +979,7 @@ module tb_modexp();
       write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h788e583b);
 
       write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf169d36e);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbe2ce61d);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc2e87809);
@@ -967,8 +989,8 @@ module tb_modexp();
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h299b36d2);
       write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h788e583b);
 
-      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
-      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000008);
+      write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000009);
+      write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000009);
 
       start_test_cycle_ctr();
 
@@ -979,10 +1001,11 @@ module tb_modexp();
       stop_test_cycle_ctr();
 
       write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data); //TEMPLATE_EXPECTED_VALUES
-      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data); //TEMPLATE_EXPECTED_VALUES
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data);
+      read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data);
 
       if (success !== 1)
         begin
@@ -1368,17 +1391,17 @@ module tb_modexp();
       reset_dut();
       dump_dut_state();
 
-//      tc1();
-//      tc2();
-//      tc3();
+      tc1();
+      tc2();
+      tc3();
 //      autogenerated_BASIC_33bit();
 //      autogenerated_BASIC_128bit();
 //      e65537_64bit_modulus();
-//      e65537_128bit_modulus();
+      e65537_128bit_modulus();
 //      e65537_256bit_modulus();
 
 //      rob_dec_1024();
-      rob_enc_1024();
+//      rob_enc_1024();
 
       display_test_results();
Previous message (by thread): [Cryptech-Commits] [core/math/modexp] 01/05: cleanup of s mem write control.
Next message (by thread): [Cryptech-Commits] [core/math/modexp] 03/05: Collapsed done. Removes one cycle from each montprod.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
More information about the Commits mailing list