[Cryptech-Commits] [core/math/modexp] 01/01: change from 12 bits address to 8 bits (for now?) for consistency with other cores
git at cryptech.is
git at cryptech.is
Wed Jun 10 16:41:06 UTC 2015
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paul at psgd.org pushed a commit to branch config_core_selector
in repository core/math/modexp.
commit b97c86991f5a6d814cc88e41ca68ca077a0056e3
Author: Paul Selkirk <paul at psgd.org>
Date: Wed Jun 10 12:38:15 2015 -0400
change from 12 bits address to 8 bits (for now?) for consistency with other cores
---
src/rtl/modexp.v | 255 ++++++++++++++++++++++++++-----------------------------
1 file changed, 122 insertions(+), 133 deletions(-)
diff --git a/src/rtl/modexp.v b/src/rtl/modexp.v
index 4e9fc51..2af987f 100644
--- a/src/rtl/modexp.v
+++ b/src/rtl/modexp.v
@@ -63,7 +63,7 @@ module modexp(
input wire cs,
input wire we,
- input wire [11 : 0] address,
+ input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
@@ -72,7 +72,6 @@ module modexp(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- localparam GENERAL_PREFIX = 4'h0;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
@@ -260,138 +259,128 @@ module modexp(
if (cs)
begin
- case (address[11 : 8])
- GENERAL_PREFIX:
- begin
- if (we)
- begin
- case (address[7 : 0])
- ADDR_CTRL:
- begin
- start_new = write_data[0];
- end
-
- ADDR_MODULUS_LENGTH:
- begin
- modulus_length_we = 1'b1;
- end
-
- ADDR_EXPONENT_LENGTH:
- begin
- exponent_length_we = 1'b1;
- end
-
- ADDR_MODULUS_PTR_RST:
- begin
- modulus_mem_api_rst = 1'b1;
- end
-
- ADDR_MODULUS_DATA:
- begin
- modulus_mem_api_cs = 1'b1;
- modulus_mem_api_wr = 1'b1;
- end
-
- ADDR_EXPONENT_PTR_RST:
- begin
- exponent_mem_api_rst = 1'b1;
- end
-
- ADDR_EXPONENT_DATA:
- begin
- exponent_mem_api_cs = 1'b1;
- exponent_mem_api_wr = 1'b1;
- end
-
- ADDR_MESSAGE_PTR_RST:
- begin
- message_mem_api_rst = 1'b1;
- end
-
- ADDR_MESSAGE_DATA:
- begin
- message_mem_api_cs = 1'b1;
- message_mem_api_wr = 1'b1;
- end
-
- ADDR_RESULT_PTR_RST:
- begin
- result_mem_api_rst = 1'b1;
- end
-
- default:
- begin
- end
- endcase // case (address[7 : 0])
- end
- else
- begin
- case (address[7 : 0])
- ADDR_NAME0:
- tmp_read_data = CORE_NAME0;
-
- ADDR_NAME1:
- tmp_read_data = CORE_NAME1;
-
- ADDR_VERSION:
- tmp_read_data = CORE_VERSION;
-
- ADDR_CTRL:
- tmp_read_data = {31'h00000000, start_reg};
-
- ADDR_STATUS:
- tmp_read_data = {31'h00000000, ready};
-
- ADDR_CYCLES_HIGH:
- tmp_read_data = cycles[63 : 32];
-
- ADDR_CYCLES_LOW:
- tmp_read_data = cycles[31 : 0];
-
- ADDR_MODULUS_LENGTH:
- tmp_read_data = {24'h000000, modulus_length_reg};
-
- ADDR_EXPONENT_LENGTH:
- tmp_read_data = {24'h000000, exponent_length_reg};
-
- ADDR_MODULUS_DATA:
- begin
- modulus_mem_api_cs = 1'b1;
- tmp_read_data = modulus_mem_api_read_data;
- end
-
- ADDR_EXPONENT_DATA:
- begin
- exponent_mem_api_cs = 1'b1;
- tmp_read_data = exponent_mem_api_read_data;
- end
-
- ADDR_MESSAGE_DATA:
- begin
- message_mem_api_cs = 1'b1;
- tmp_read_data = message_mem_api_read_data;
- end
-
- ADDR_RESULT_DATA:
- begin
- result_mem_api_cs = 1'b1;
- tmp_read_data = result_mem_api_read_data;
- end
-
- default:
- begin
- end
- endcase // case (address[7 : 0])
- end
- end
-
- default:
- begin
-
- end
- endcase // case (address[11 : 8])
+ if (we)
+ begin
+ case (address)
+ ADDR_CTRL:
+ begin
+ start_new = write_data[0];
+ end
+
+ ADDR_MODULUS_LENGTH:
+ begin
+ modulus_length_we = 1'b1;
+ end
+
+ ADDR_EXPONENT_LENGTH:
+ begin
+ exponent_length_we = 1'b1;
+ end
+
+ ADDR_MODULUS_PTR_RST:
+ begin
+ modulus_mem_api_rst = 1'b1;
+ end
+
+ ADDR_MODULUS_DATA:
+ begin
+ modulus_mem_api_cs = 1'b1;
+ modulus_mem_api_wr = 1'b1;
+ end
+
+ ADDR_EXPONENT_PTR_RST:
+ begin
+ exponent_mem_api_rst = 1'b1;
+ end
+
+ ADDR_EXPONENT_DATA:
+ begin
+ exponent_mem_api_cs = 1'b1;
+ exponent_mem_api_wr = 1'b1;
+ end
+
+ ADDR_MESSAGE_PTR_RST:
+ begin
+ message_mem_api_rst = 1'b1;
+ end
+
+ ADDR_MESSAGE_DATA:
+ begin
+ message_mem_api_cs = 1'b1;
+ message_mem_api_wr = 1'b1;
+ end
+
+ ADDR_RESULT_PTR_RST:
+ begin
+ result_mem_api_rst = 1'b1;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (address[7 : 0])
+ end // if (we)
+ else
+ begin
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = CORE_NAME0;
+
+ ADDR_NAME1:
+ tmp_read_data = CORE_NAME1;
+
+ ADDR_VERSION:
+ tmp_read_data = CORE_VERSION;
+
+ ADDR_CTRL:
+ tmp_read_data = {31'h00000000, start_reg};
+
+ ADDR_STATUS:
+ tmp_read_data = {31'h00000000, ready};
+
+ ADDR_CYCLES_HIGH:
+ tmp_read_data = cycles[63 : 32];
+
+ ADDR_CYCLES_LOW:
+ tmp_read_data = cycles[31 : 0];
+
+ ADDR_MODULUS_LENGTH:
+ tmp_read_data = {24'h000000, modulus_length_reg};
+
+ ADDR_EXPONENT_LENGTH:
+ tmp_read_data = {24'h000000, exponent_length_reg};
+
+ ADDR_MODULUS_DATA:
+ begin
+ modulus_mem_api_cs = 1'b1;
+ tmp_read_data = modulus_mem_api_read_data;
+ end
+
+ ADDR_EXPONENT_DATA:
+ begin
+ exponent_mem_api_cs = 1'b1;
+ tmp_read_data = exponent_mem_api_read_data;
+ end
+
+ ADDR_MESSAGE_DATA:
+ begin
+ message_mem_api_cs = 1'b1;
+ tmp_read_data = message_mem_api_read_data;
+ end
+
+ ADDR_RESULT_DATA:
+ begin
+ result_mem_api_cs = 1'b1;
+ tmp_read_data = result_mem_api_read_data;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (address)
+ end // else: !if(we)
end // if (cs)
- end // api
+ end // block: api
endmodule // modexp
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