[Cryptech-Commits] [core/hash/sha512] 01/02: Adding ports in the core to do state restore. Added wires in the top to connect the state restore ports.

[git at cryptech.is]

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joachim at secworks.se pushed a commit to branch state_restore
in repository core/hash/sha512.

commit b8228ec9568830b561f4826ce54748229f140655
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sat Jul 18 12:22:31 2015 +0200

    Adding ports in the core to do state restore. Added wires in the top to connect the state restore ports.
---
 src/rtl/sha512.v      | 40 ++++++++++++++++++++++++++++++++++++++--
 src/rtl/sha512_core.v | 19 +++++++++++++++++++
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/src/rtl/sha512.v b/src/rtl/sha512.v
index 0d26b85..e1bf745 100644
--- a/src/rtl/sha512.v
+++ b/src/rtl/sha512.v
@@ -243,8 +243,26 @@ module sha512(
   wire [511 : 0]  core_digest;
   wire            core_digest_valid;
 
-  reg [31 : 0] tmp_read_data;
-  reg          tmp_error;
+  reg             state00_we;
+  reg             state01_we;
+  reg             state02_we;
+  reg             state03_we;
+  reg             state04_we;
+  reg             state05_we;
+  reg             state06_we;
+  reg             state07_we;
+  reg             state08_we;
+  reg             state09_we;
+  reg             state10_we;
+  reg             state11_we;
+  reg             state12_we;
+  reg             state13_we;
+  reg             state14_we;
+  reg             state15_we;
+
+
+  reg [31 : 0]    tmp_read_data;
+  reg             tmp_error;
 
 
   //----------------------------------------------------------------
@@ -289,6 +307,24 @@ module sha512(
 
                    .ready(core_ready),
 
+                   .state_wr_data(write_data),
+                   .state00_we(state00_we),
+                   .state01_we(state01_we),
+                   .state02_we(state02_we),
+                   .state03_we(state03_we),
+                   .state04_we(state04_we),
+                   .state05_we(state05_we),
+                   .state06_we(state06_we),
+                   .state07_we(state07_we),
+                   .state08_we(state08_we),
+                   .state09_we(state09_we),
+                   .state10_we(state10_we),
+                   .state11_we(state11_we),
+                   .state12_we(state12_we),
+                   .state13_we(state13_we),
+                   .state14_we(state14_we),
+                   .state15_we(state15_we),
+
                    .digest(core_digest),
                    .digest_valid(core_digest_valid)
                   );
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index 12742a8..895c22f 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -51,6 +51,25 @@ module sha512_core(
                    input wire [1023 : 0] block,
 
                    output wire           ready,
+
+                   input wire [31 : 0]   state_wr_data,
+                   input wire            state00_we,
+                   input wire            state01_we,
+                   input wire            state02_we,
+                   input wire            state03_we,
+                   input wire            state04_we,
+                   input wire            state05_we,
+                   input wire            state06_we,
+                   input wire            state07_we,
+                   input wire            state08_we,
+                   input wire            state09_we,
+                   input wire            state10_we,
+                   input wire            state11_we,
+                   input wire            state12_we,
+                   input wire            state13_we,
+                   input wire            state14_we,
+                   input wire            state15_we,
+
                    output wire [511 : 0] digest,
                    output wire           digest_valid
                   );