[Cryptech-Commits] [core/platform/novena] 01/01: update lint for new ipcore modules

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch modexps6
in repository core/platform/novena.

commit 5f1de63e3bc6043ee10683a2c9fd8a7c03a3983a
Author: Paul Selkirk <paul at psgd.org>
Date:   Sat Jul 18 06:06:55 2015 -0400

    update lint for new ipcore modules
---
 common/rtl/ipcore/clkmgr_dcm.v |  4 +++
 common/rtl/lint-dummy.v        | 61 ++++++++++++++++++++++++++++++++++++++++++
 eim/build/Makefile             |  2 +-
 3 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v
index 71477a8..6e57c3d 100644
--- a/common/rtl/ipcore/clkmgr_dcm.v
+++ b/common/rtl/ipcore/clkmgr_dcm.v
@@ -62,6 +62,10 @@
 //----------------------------------------------------------------------------
 // __primary______________50____________0.010
 
+/*verilator lint_off PINCONNECTEMPTY*/
+/*verilator lint_off UNDRIVEN*/
+/*verilator lint_off UNUSED*/
+
 `timescale 1ps/1ps
 
 (* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANU [...]
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v
index 9016622..9d4d2d3 100644
--- a/common/rtl/lint-dummy.v
+++ b/common/rtl/lint-dummy.v
@@ -62,3 +62,64 @@ module FDCE (Q, C, CE, CLR, D);
     output Q;
     input  C, CE, CLR, D;
 endmodule
+
+module FD (Q, C, D);
+    parameter INIT = 1'b0;
+    output Q;
+    input  C, D;
+endmodule
+
+module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP); 
+    parameter integer A0REG = 0;
+    parameter integer A1REG = 1;
+    parameter integer B0REG = 0;
+    parameter integer B1REG = 1;
+    parameter integer CARRYINREG = 1;
+    parameter integer CARRYOUTREG = 1;
+    parameter CARRYINSEL = "OPMODE5";
+    parameter integer CREG = 1;
+    parameter integer DREG = 1;
+    parameter integer MREG = 1;
+    parameter integer OPMODEREG = 1;
+    parameter integer PREG = 1;
+    parameter RSTTYPE = "SYNC";
+    output [17:0] BCOUT; 
+    output CARRYOUT; 
+    output CARRYOUTF; 
+    output [35:0] M; 
+    output [47:0] P; 
+    output [47:0] PCOUT;
+    input [17:0] A;
+    input [17:0] B;
+    input [47:0] C;
+    input CARRYIN;
+    input CEA;
+    input CEB;
+    input CEC;
+    input CECARRYIN;
+    input CED;
+    input CEM;
+    input CEOPMODE;
+    input CEP;
+    input CLK;
+    input [17:0] D;
+    input [7:0] OPMODE;
+    input [47:0] PCIN;
+    input RSTA;
+    input RSTB;
+    input RSTC;
+    input RSTCARRYIN;
+    input RSTD;
+    input RSTM;  
+    input RSTOPMODE;
+    input RSTP;
+endmodule
+
+module GND(G);
+    output G;
+endmodule
+
+module VCC(P);
+    output P;
+endmodule
+
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 59f792f..6b251f2 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -71,4 +71,4 @@ vfiles = \
 include xilinx.mk
 
 lint:
-	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.v ../../../../math/modexps6/src/rtl/ipcore/subtractor_s6..v ../../common/rtl/lint-dummy.v
+	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v