[Cryptech-Commits] [test/modexps6] 01/01: Initial commit

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paul at psgd.org pushed a commit to branch master
in repository test/modexps6.

commit a778dbbf0c88853ccc30f7ca8623eb5cef45d51c
Author: Paul Selkirk <paul at psgd.org>
Date:   Fri Jul 17 09:57:23 2015 -0400

    Initial commit
---
 src/rtl/ipcore/_xmsgs/cg.xmsgs                     |   39 +
 src/rtl/ipcore/_xmsgs/pn_parser.xmsgs              |   15 +
 src/rtl/ipcore/coregen.cgp                         |    9 +
 src/rtl/ipcore/edit_multiplier_s6.tcl              |   37 +
 src/rtl/ipcore/edit_subtractor_s6.tcl              |   37 +
 src/rtl/ipcore/multiplier_s6.asy                   |   21 +
 src/rtl/ipcore/multiplier_s6.gise                  |   53 +
 src/rtl/ipcore/multiplier_s6.ncf                   |    0
 src/rtl/ipcore/multiplier_s6.ngc                   |    3 +
 src/rtl/ipcore/multiplier_s6.sym                   |   21 +
 src/rtl/ipcore/multiplier_s6.v                     | 1485 ++++++++++++++++++++
 src/rtl/ipcore/multiplier_s6.veo                   |   65 +
 src/rtl/ipcore/multiplier_s6.xco                   |   68 +
 src/rtl/ipcore/multiplier_s6.xise                  |   73 +
 .../ipcore/multiplier_s6/doc/mult_gen_ds255.pdf    |  Bin 0 -> 302354 bytes
 .../multiplier_s6/doc/mult_gen_v11_2_readme.txt    |  184 +++
 .../multiplier_s6/doc/mult_gen_v11_2_vinfo.html    |  195 +++
 src/rtl/ipcore/multiplier_s6_flist.txt             |   14 +
 src/rtl/ipcore/multiplier_s6_xmdf.tcl              |   83 ++
 src/rtl/ipcore/subtractor_s6.asy                   |   25 +
 src/rtl/ipcore/subtractor_s6.gise                  |   53 +
 src/rtl/ipcore/subtractor_s6.ncf                   |    0
 src/rtl/ipcore/subtractor_s6.ngc                   |    3 +
 src/rtl/ipcore/subtractor_s6.sym                   |   24 +
 src/rtl/ipcore/subtractor_s6.v                     |  364 +++++
 src/rtl/ipcore/subtractor_s6.veo                   |   71 +
 src/rtl/ipcore/subtractor_s6.xco                   |   73 +
 src/rtl/ipcore/subtractor_s6.xise                  |   73 +
 .../subtractor_s6/doc/c_addsub_v11_0_readme.txt    |  164 +++
 .../subtractor_s6/doc/c_addsub_v11_0_vinfo.html    |  175 +++
 src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf  |  Bin 0 -> 317089 bytes
 src/rtl/ipcore/subtractor_s6_flist.txt             |   14 +
 src/rtl/ipcore/subtractor_s6_xmdf.tcl              |   83 ++
 src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs             |   12 +
 src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs          |   15 +
 src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs                |   84 ++
 src/rtl/ipcore/tmp/multiplier_s6.lso               |    1 +
 src/rtl/ipcore/tmp/subtractor_s6.lso               |    1 +
 src/rtl/modexps6_adder64_carry32.v                 |   70 +
 src/rtl/modexps6_buffer_core.v                     |  202 +++
 src/rtl/modexps6_buffer_user.v                     |  185 +++
 src/rtl/modexps6_modinv32.v                        |  116 ++
 src/rtl/modexps6_montgomery_coeff.v                |  410 ++++++
 src/rtl/modexps6_montgomery_multiplier.v           |  392 ++++++
 src/rtl/modexps6_top.v                             |  696 +++++++++
 src/rtl/modexps6_wrapper.v                         |  187 +++
 src/rtl/ram_1rw_1ro_readfirst.v                    |   69 +
 47 files changed, 5964 insertions(+)

diff --git a/src/rtl/ipcore/_xmsgs/cg.xmsgs b/src/rtl/ipcore/_xmsgs/cg.xmsgs
new file mode 100644
index 0000000..f165d5f
--- /dev/null
+++ b/src/rtl/ipcore/_xmsgs/cg.xmsgs
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'multiplier_s6'...</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'.</arg>
+</msg>
+
+<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs b/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..cd873b7
--- /dev/null
+++ b/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/core/math/modexps6/src/rtl/ipcore/subtractor_s6.v" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/coregen.cgp b/src/rtl/ipcore/coregen.cgp
new file mode 100644
index 0000000..8bc2e70
--- /dev/null
+++ b/src/rtl/ipcore/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
diff --git a/src/rtl/ipcore/edit_multiplier_s6.tcl b/src/rtl/ipcore/edit_multiplier_s6.tcl
new file mode 100644
index 0000000..b2357d5
--- /dev/null
+++ b/src/rtl/ipcore/edit_multiplier_s6.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "multiplier_s6" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/src/rtl/ipcore/edit_subtractor_s6.tcl b/src/rtl/ipcore/edit_subtractor_s6.tcl
new file mode 100644
index 0000000..49f4d27
--- /dev/null
+++ b/src/rtl/ipcore/edit_subtractor_s6.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "subtractor_s6" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/src/rtl/ipcore/multiplier_s6.asy b/src/rtl/ipcore/multiplier_s6.asy
new file mode 100644
index 0000000..4bcf909
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.asy
@@ -0,0 +1,21 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 multiplier_s6
+RECTANGLE Normal 32 32 544 416
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName a[31:0]
+PINATTR Polarity IN
+LINE Wide 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName b[31:0]
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName p[63:0]
+PINATTR Polarity OUT
+
diff --git a/src/rtl/ipcore/multiplier_s6.gise b/src/rtl/ipcore/multiplier_s6.gise
new file mode 100644
index 0000000..bfafdc6
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.gise
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="multiplier_s6.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="multiplier_s6.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="multiplier_s6.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="multiplier_s6.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-480660529792370684" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1432244621186928363" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6211771399160386746" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/src/rtl/ipcore/multiplier_s6.ncf b/src/rtl/ipcore/multiplier_s6.ncf
new file mode 100644
index 0000000..e69de29
diff --git a/src/rtl/ipcore/multiplier_s6.ngc b/src/rtl/ipcore/multiplier_s6.ngc
new file mode 100644
index 0000000..10fa0cc
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$5`544<,[o}e~g`n;"2*73>(-80!<?400285=<NFY__6L2>7;2=55=603CE\XZ5B=34>586;2;36D at _UU8AGLH;9>0;2<>4198JJUSS2M6:;7>11492<?IR\Y__6OM at UU>23?6990196B[[PTV9^@THWMO_INZ31;2=55=4:3CE\XZ5A=12>58682996D at _UU8A867=87;;7><5IORVP?g;;80;2<>4338JJUSS2k68=7>110902?IR\Y__6 at 2<5;2=55=303CE\XZ5C=64>586;2>36D at _UU8SGLH;<>0;2<?4498LQQVR\3Z78:4?>0780=<H]]Z^X7^LARA?02<768?0854 at UURVP?VDG\^78:4?>03821<H]]Z^X7^36283:47<>=0DYY^ZT;r?26<76l1=av;5bqd772*;89047GAPTV9KUKHLL6<6=0:;@2QAB3<I8XNK95N<1<6?D:687?0M1?>>49B8449=2K7 [...]
\ No newline at end of file
diff --git a/src/rtl/ipcore/multiplier_s6.sym b/src/rtl/ipcore/multiplier_s6.sym
new file mode 100644
index 0000000..4e151ee
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.sym
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="multiplier_s6">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2015-7-10T14:52:9</timestamp>
+    <pin polarity="Input" x="0" y="80" name="a[31:0]" />
+    <pin polarity="Input" x="0" y="144" name="b[31:0]" />
+    <pin polarity="Input" x="0" y="240" name="clk" />
+    <pin polarity="Output" x="576" y="80" name="p[63:0]" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">multiplier_s6</text>
+        <rect width="512" x="32" y="32" height="384" />
+        <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin a[31:0]" />
+        <line x2="32" y1="144" y2="144" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin b[31:0]" />
+        <line x2="32" y1="240" y2="240" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin clk" />
+        <line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin p[63:0]" />
+    </graph>
+</symbol>
diff --git a/src/rtl/ipcore/multiplier_s6.v b/src/rtl/ipcore/multiplier_s6.v
new file mode 100644
index 0000000..7a7cb5e
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.v
@@ -0,0 +1,1485 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: P.20131013
+//  \   \         Application: netgen
+//  /   /         Filename: multiplier_s6.v
+// /___/   /\     Timestamp: Fri Jul 10 17:52:08 2015
+// \   \  /  \ 
+//  \___\/\___\
+//             
+// Command	: -w -sim -ofmt verilog E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.ngc E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v 
+// Device	: 6slx45csg324-3
+// Input file	: E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.ngc
+// Output file	: E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v
+// # of Modules	: 1
+// Design Name	: multiplier_s6
+// Xilinx        : e:\Xilinx\14.7\ISE_DS\ISE\
+//             
+// Purpose:    
+//     This verilog netlist is a verification model and uses simulation 
+//     primitives which may not represent the true implementation of the 
+//     device, however the netlist is functionally correct and should not 
+//     be modified. This file cannot be synthesized and should only be used 
+//     with supported simulation tools.
+//             
+// Reference:  
+//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//             
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module multiplier_s6 (
+  clk, a, b, p
+)/* synthesis syn_black_box syn_noprune=1 */;
+  input clk;
+  input [31 : 0] a;
+  input [31 : 0] b;
+  output [63 : 0] p;
+  
+  // synthesis translate_off
+  
+  wire \blk00000001/sig000001c7 ;
+  wire \blk00000001/sig000001c6 ;
+  wire \blk00000001/sig000001c5 ;
+  wire \blk00000001/sig000001c4 ;
+  wire \blk00000001/sig000001c3 ;
+  wire \blk00000001/sig000001c2 ;
+  wire \blk00000001/sig000001c1 ;
+  wire \blk00000001/sig000001c0 ;
+  wire \blk00000001/sig000001bf ;
+  wire \blk00000001/sig000001be ;
+  wire \blk00000001/sig000001bd ;
+  wire \blk00000001/sig000001bc ;
+  wire \blk00000001/sig000001bb ;
+  wire \blk00000001/sig000001ba ;
+  wire \blk00000001/sig000001b9 ;
+  wire \blk00000001/sig000001b8 ;
+  wire \blk00000001/sig000001b7 ;
+  wire \blk00000001/sig000001b6 ;
+  wire \blk00000001/sig000001b5 ;
+  wire \blk00000001/sig000001b4 ;
+  wire \blk00000001/sig000001b3 ;
+  wire \blk00000001/sig000001b2 ;
+  wire \blk00000001/sig000001b1 ;
+  wire \blk00000001/sig000001b0 ;
+  wire \blk00000001/sig000001af ;
+  wire \blk00000001/sig000001ae ;
+  wire \blk00000001/sig000001ad ;
+  wire \blk00000001/sig000001ac ;
+  wire \blk00000001/sig000001ab ;
+  wire \blk00000001/sig000001aa ;
+  wire \blk00000001/sig000001a9 ;
+  wire \blk00000001/sig000001a8 ;
+  wire \blk00000001/sig000001a7 ;
+  wire \blk00000001/sig000001a6 ;
+  wire \blk00000001/sig000001a5 ;
+  wire \blk00000001/sig000001a4 ;
+  wire \blk00000001/sig000001a3 ;
+  wire \blk00000001/sig000001a2 ;
+  wire \blk00000001/sig000001a1 ;
+  wire \blk00000001/sig000001a0 ;
+  wire \blk00000001/sig0000019f ;
+  wire \blk00000001/sig0000019e ;
+  wire \blk00000001/sig0000019d ;
+  wire \blk00000001/sig0000019c ;
+  wire \blk00000001/sig0000019b ;
+  wire \blk00000001/sig0000019a ;
+  wire \blk00000001/sig00000199 ;
+  wire \blk00000001/sig00000198 ;
+  wire \blk00000001/sig00000197 ;
+  wire \blk00000001/sig00000196 ;
+  wire \blk00000001/sig00000195 ;
+  wire \blk00000001/sig00000194 ;
+  wire \blk00000001/sig00000193 ;
+  wire \blk00000001/sig00000192 ;
+  wire \blk00000001/sig00000191 ;
+  wire \blk00000001/sig00000190 ;
+  wire \blk00000001/sig0000018f ;
+  wire \blk00000001/sig0000018e ;
+  wire \blk00000001/sig0000018d ;
+  wire \blk00000001/sig0000018c ;
+  wire \blk00000001/sig0000018b ;
+  wire \blk00000001/sig0000018a ;
+  wire \blk00000001/sig00000189 ;
+  wire \blk00000001/sig00000188 ;
+  wire \blk00000001/sig00000187 ;
+  wire \blk00000001/sig00000186 ;
+  wire \blk00000001/sig00000185 ;
+  wire \blk00000001/sig00000184 ;
+  wire \blk00000001/sig00000183 ;
+  wire \blk00000001/sig00000182 ;
+  wire \blk00000001/sig00000181 ;
+  wire \blk00000001/sig00000180 ;
+  wire \blk00000001/sig0000017f ;
+  wire \blk00000001/sig0000017e ;
+  wire \blk00000001/sig0000017d ;
+  wire \blk00000001/sig0000017c ;
+  wire \blk00000001/sig0000017b ;
+  wire \blk00000001/sig0000017a ;
+  wire \blk00000001/sig00000179 ;
+  wire \blk00000001/sig00000178 ;
+  wire \blk00000001/sig00000177 ;
+  wire \blk00000001/sig00000176 ;
+  wire \blk00000001/sig00000175 ;
+  wire \blk00000001/sig00000174 ;
+  wire \blk00000001/sig00000173 ;
+  wire \blk00000001/sig00000172 ;
+  wire \blk00000001/sig00000171 ;
+  wire \blk00000001/sig00000170 ;
+  wire \blk00000001/sig0000016f ;
+  wire \blk00000001/sig0000016e ;
+  wire \blk00000001/sig0000016d ;
+  wire \blk00000001/sig0000016c ;
+  wire \blk00000001/sig0000016b ;
+  wire \blk00000001/sig0000016a ;
+  wire \blk00000001/sig00000169 ;
+  wire \blk00000001/sig00000168 ;
+  wire \blk00000001/sig00000167 ;
+  wire \blk00000001/sig00000166 ;
+  wire \blk00000001/sig00000165 ;
+  wire \blk00000001/sig00000164 ;
+  wire \blk00000001/sig00000163 ;
+  wire \blk00000001/sig00000162 ;
+  wire \blk00000001/sig00000161 ;
+  wire \blk00000001/sig00000160 ;
+  wire \blk00000001/sig0000015f ;
+  wire \blk00000001/sig0000015e ;
+  wire \blk00000001/sig0000015d ;
+  wire \blk00000001/sig0000015c ;
+  wire \blk00000001/sig0000015b ;
+  wire \blk00000001/sig0000015a ;
+  wire \blk00000001/sig00000159 ;
+  wire \blk00000001/sig00000158 ;
+  wire \blk00000001/sig00000157 ;
+  wire \blk00000001/sig00000156 ;
+  wire \blk00000001/sig00000155 ;
+  wire \blk00000001/sig00000154 ;
+  wire \blk00000001/sig00000153 ;
+  wire \blk00000001/sig00000152 ;
+  wire \blk00000001/sig00000151 ;
+  wire \blk00000001/sig00000150 ;
+  wire \blk00000001/sig0000014f ;
+  wire \blk00000001/sig0000014e ;
+  wire \blk00000001/sig0000014d ;
+  wire \blk00000001/sig0000014c ;
+  wire \blk00000001/sig0000014b ;
+  wire \blk00000001/sig0000014a ;
+  wire \blk00000001/sig00000149 ;
+  wire \blk00000001/sig00000148 ;
+  wire \blk00000001/sig00000147 ;
+  wire \blk00000001/sig00000146 ;
+  wire \blk00000001/sig00000145 ;
+  wire \blk00000001/sig00000144 ;
+  wire \blk00000001/sig00000143 ;
+  wire \blk00000001/sig00000142 ;
+  wire \blk00000001/sig00000141 ;
+  wire \blk00000001/sig00000140 ;
+  wire \blk00000001/sig0000013f ;
+  wire \blk00000001/sig0000013e ;
+  wire \blk00000001/sig0000013d ;
+  wire \blk00000001/sig0000013c ;
+  wire \blk00000001/sig0000013b ;
+  wire \blk00000001/sig0000013a ;
+  wire \blk00000001/sig00000139 ;
+  wire \blk00000001/sig00000138 ;
+  wire \blk00000001/sig00000137 ;
+  wire \blk00000001/sig00000136 ;
+  wire \blk00000001/sig00000135 ;
+  wire \blk00000001/sig00000134 ;
+  wire \blk00000001/sig00000133 ;
+  wire \blk00000001/sig00000132 ;
+  wire \blk00000001/sig00000131 ;
+  wire \blk00000001/sig00000130 ;
+  wire \blk00000001/sig0000012f ;
+  wire \blk00000001/sig0000012e ;
+  wire \blk00000001/sig0000012d ;
+  wire \blk00000001/sig0000012c ;
+  wire \blk00000001/sig0000012b ;
+  wire \blk00000001/sig0000012a ;
+  wire \blk00000001/sig00000129 ;
+  wire \blk00000001/sig00000128 ;
+  wire \blk00000001/sig00000127 ;
+  wire \blk00000001/sig00000126 ;
+  wire \blk00000001/sig00000125 ;
+  wire \blk00000001/sig00000124 ;
+  wire \blk00000001/sig00000123 ;
+  wire \blk00000001/sig00000122 ;
+  wire \blk00000001/sig00000121 ;
+  wire \blk00000001/sig00000120 ;
+  wire \blk00000001/sig0000011f ;
+  wire \blk00000001/sig0000011e ;
+  wire \blk00000001/sig0000011d ;
+  wire \blk00000001/sig0000011c ;
+  wire \blk00000001/sig0000011b ;
+  wire \blk00000001/sig0000011a ;
+  wire \blk00000001/sig00000119 ;
+  wire \blk00000001/sig00000118 ;
+  wire \blk00000001/sig00000117 ;
+  wire \blk00000001/sig00000116 ;
+  wire \blk00000001/sig00000115 ;
+  wire \blk00000001/sig00000114 ;
+  wire \blk00000001/sig00000113 ;
+  wire \blk00000001/sig00000112 ;
+  wire \blk00000001/sig00000111 ;
+  wire \blk00000001/sig00000110 ;
+  wire \blk00000001/sig0000010f ;
+  wire \blk00000001/sig0000010e ;
+  wire \blk00000001/sig0000010d ;
+  wire \blk00000001/sig0000010c ;
+  wire \blk00000001/sig0000010b ;
+  wire \blk00000001/sig0000010a ;
+  wire \blk00000001/sig00000109 ;
+  wire \blk00000001/sig00000108 ;
+  wire \blk00000001/sig00000107 ;
+  wire \blk00000001/sig00000106 ;
+  wire \blk00000001/sig00000105 ;
+  wire \blk00000001/sig00000104 ;
+  wire \blk00000001/sig00000103 ;
+  wire \blk00000001/sig00000102 ;
+  wire \blk00000001/sig00000101 ;
+  wire \blk00000001/sig00000100 ;
+  wire \blk00000001/sig000000ff ;
+  wire \blk00000001/sig000000fe ;
+  wire \blk00000001/sig000000fd ;
+  wire \blk00000001/sig000000fc ;
+  wire \blk00000001/sig000000fb ;
+  wire \blk00000001/sig000000fa ;
+  wire \blk00000001/sig000000f9 ;
+  wire \blk00000001/sig000000f8 ;
+  wire \blk00000001/sig000000f7 ;
+  wire \blk00000001/sig000000f6 ;
+  wire \blk00000001/sig000000f5 ;
+  wire \blk00000001/sig000000f4 ;
+  wire \blk00000001/sig000000f3 ;
+  wire \blk00000001/sig000000f2 ;
+  wire \blk00000001/sig000000f1 ;
+  wire \blk00000001/sig000000f0 ;
+  wire \blk00000001/sig000000ef ;
+  wire \blk00000001/sig000000ee ;
+  wire \blk00000001/sig000000ed ;
+  wire \blk00000001/sig000000ec ;
+  wire \blk00000001/sig000000eb ;
+  wire \blk00000001/sig000000ea ;
+  wire \blk00000001/sig000000e9 ;
+  wire \blk00000001/sig000000e8 ;
+  wire \blk00000001/sig000000e7 ;
+  wire \blk00000001/sig000000e6 ;
+  wire \blk00000001/sig000000e5 ;
+  wire \blk00000001/sig000000e4 ;
+  wire \blk00000001/sig000000e3 ;
+  wire \blk00000001/sig000000e2 ;
+  wire \blk00000001/sig000000e1 ;
+  wire \blk00000001/sig000000e0 ;
+  wire \blk00000001/sig000000df ;
+  wire \blk00000001/sig000000de ;
+  wire \blk00000001/sig000000dd ;
+  wire \blk00000001/sig000000dc ;
+  wire \blk00000001/sig000000db ;
+  wire \blk00000001/sig000000da ;
+  wire \blk00000001/sig000000d9 ;
+  wire \blk00000001/sig000000d8 ;
+  wire \blk00000001/sig000000d7 ;
+  wire \blk00000001/sig000000d6 ;
+  wire \blk00000001/sig000000d5 ;
+  wire \blk00000001/sig000000d4 ;
+  wire \blk00000001/sig000000d3 ;
+  wire \blk00000001/sig000000d2 ;
+  wire \blk00000001/sig000000d1 ;
+  wire \blk00000001/sig000000d0 ;
+  wire \blk00000001/sig000000cf ;
+  wire \blk00000001/sig000000ce ;
+  wire \blk00000001/sig000000cd ;
+  wire \blk00000001/sig000000cc ;
+  wire \blk00000001/sig000000cb ;
+  wire \blk00000001/sig000000ca ;
+  wire \blk00000001/sig000000c9 ;
+  wire \blk00000001/sig000000c8 ;
+  wire \blk00000001/sig000000c7 ;
+  wire \blk00000001/sig000000c6 ;
+  wire \blk00000001/sig000000c5 ;
+  wire \blk00000001/sig000000c4 ;
+  wire \blk00000001/sig000000c3 ;
+  wire \blk00000001/sig000000c2 ;
+  wire \blk00000001/sig000000c1 ;
+  wire \blk00000001/sig000000c0 ;
+  wire \blk00000001/sig000000bf ;
+  wire \blk00000001/sig000000be ;
+  wire \blk00000001/sig000000bd ;
+  wire \blk00000001/sig000000bc ;
+  wire \blk00000001/sig000000bb ;
+  wire \blk00000001/sig000000ba ;
+  wire \blk00000001/sig000000b9 ;
+  wire \blk00000001/sig000000b8 ;
+  wire \blk00000001/sig000000b7 ;
+  wire \blk00000001/sig000000b6 ;
+  wire \blk00000001/sig000000b5 ;
+  wire \blk00000001/sig000000b4 ;
+  wire \blk00000001/sig000000b3 ;
+  wire \blk00000001/sig000000b2 ;
+  wire \blk00000001/sig000000b1 ;
+  wire \blk00000001/sig000000b0 ;
+  wire \blk00000001/sig000000af ;
+  wire \blk00000001/sig000000ae ;
+  wire \blk00000001/sig000000ad ;
+  wire \blk00000001/sig000000ac ;
+  wire \blk00000001/sig000000ab ;
+  wire \blk00000001/sig000000aa ;
+  wire \blk00000001/sig000000a9 ;
+  wire \blk00000001/sig000000a8 ;
+  wire \blk00000001/sig000000a7 ;
+  wire \blk00000001/sig000000a6 ;
+  wire \blk00000001/sig000000a5 ;
+  wire \blk00000001/sig000000a4 ;
+  wire \blk00000001/sig000000a3 ;
+  wire \blk00000001/sig000000a2 ;
+  wire \blk00000001/sig000000a1 ;
+  wire \blk00000001/sig000000a0 ;
+  wire \blk00000001/sig0000009f ;
+  wire \blk00000001/sig0000009e ;
+  wire \blk00000001/sig0000009d ;
+  wire \blk00000001/sig0000009c ;
+  wire \blk00000001/sig0000009b ;
+  wire \blk00000001/sig0000009a ;
+  wire \blk00000001/sig00000099 ;
+  wire \blk00000001/sig00000098 ;
+  wire \blk00000001/sig00000097 ;
+  wire \blk00000001/sig00000096 ;
+  wire \blk00000001/sig00000095 ;
+  wire \blk00000001/sig00000094 ;
+  wire \blk00000001/sig00000093 ;
+  wire \blk00000001/sig00000092 ;
+  wire \blk00000001/sig00000091 ;
+  wire \blk00000001/sig00000090 ;
+  wire \blk00000001/sig0000008f ;
+  wire \blk00000001/sig0000008e ;
+  wire \blk00000001/sig0000008d ;
+  wire \blk00000001/sig0000008c ;
+  wire \blk00000001/sig0000008b ;
+  wire \blk00000001/sig0000008a ;
+  wire \blk00000001/sig00000089 ;
+  wire \blk00000001/sig00000088 ;
+  wire \blk00000001/sig00000087 ;
+  wire \blk00000001/sig00000086 ;
+  wire \blk00000001/sig00000085 ;
+  wire \blk00000001/sig00000084 ;
+  wire \blk00000001/sig00000083 ;
+  wire \blk00000001/sig00000082 ;
+  wire \NLW_blk00000001/blk00000007_CARRYOUTF_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_CARRYOUT_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_C<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000007_M<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_CARRYOUTF_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_CARRYOUT_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_C<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000006_M<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_P<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000005_M<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ;
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000029  (
+    .C(clk),
+    .D(\blk00000001/sig000001a5 ),
+    .Q(p[0])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000028  (
+    .C(clk),
+    .D(\blk00000001/sig000001a6 ),
+    .Q(p[1])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000027  (
+    .C(clk),
+    .D(\blk00000001/sig000001a7 ),
+    .Q(p[2])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000026  (
+    .C(clk),
+    .D(\blk00000001/sig000001a8 ),
+    .Q(p[3])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000025  (
+    .C(clk),
+    .D(\blk00000001/sig000001a9 ),
+    .Q(p[4])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000024  (
+    .C(clk),
+    .D(\blk00000001/sig000001aa ),
+    .Q(p[5])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000023  (
+    .C(clk),
+    .D(\blk00000001/sig000001ab ),
+    .Q(p[6])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000022  (
+    .C(clk),
+    .D(\blk00000001/sig000001ac ),
+    .Q(p[7])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000021  (
+    .C(clk),
+    .D(\blk00000001/sig000001ad ),
+    .Q(p[8])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000020  (
+    .C(clk),
+    .D(\blk00000001/sig000001ae ),
+    .Q(p[9])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001f  (
+    .C(clk),
+    .D(\blk00000001/sig000001af ),
+    .Q(p[10])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001e  (
+    .C(clk),
+    .D(\blk00000001/sig000001b0 ),
+    .Q(p[11])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001d  (
+    .C(clk),
+    .D(\blk00000001/sig000001b1 ),
+    .Q(p[12])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001c  (
+    .C(clk),
+    .D(\blk00000001/sig000001b2 ),
+    .Q(p[13])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001b  (
+    .C(clk),
+    .D(\blk00000001/sig000001b3 ),
+    .Q(p[14])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000001a  (
+    .C(clk),
+    .D(\blk00000001/sig000001b4 ),
+    .Q(p[15])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000019  (
+    .C(clk),
+    .D(\blk00000001/sig000001b5 ),
+    .Q(p[16])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000018  (
+    .C(clk),
+    .D(\blk00000001/sig00000133 ),
+    .Q(p[17])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000017  (
+    .C(clk),
+    .D(\blk00000001/sig00000134 ),
+    .Q(p[18])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000016  (
+    .C(clk),
+    .D(\blk00000001/sig00000135 ),
+    .Q(p[19])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000015  (
+    .C(clk),
+    .D(\blk00000001/sig00000136 ),
+    .Q(p[20])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000014  (
+    .C(clk),
+    .D(\blk00000001/sig00000137 ),
+    .Q(p[21])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000013  (
+    .C(clk),
+    .D(\blk00000001/sig00000138 ),
+    .Q(p[22])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000012  (
+    .C(clk),
+    .D(\blk00000001/sig00000139 ),
+    .Q(p[23])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000011  (
+    .C(clk),
+    .D(\blk00000001/sig0000013a ),
+    .Q(p[24])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000010  (
+    .C(clk),
+    .D(\blk00000001/sig0000013b ),
+    .Q(p[25])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000f  (
+    .C(clk),
+    .D(\blk00000001/sig0000013c ),
+    .Q(p[26])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000e  (
+    .C(clk),
+    .D(\blk00000001/sig0000013d ),
+    .Q(p[27])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000d  (
+    .C(clk),
+    .D(\blk00000001/sig0000013e ),
+    .Q(p[28])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000c  (
+    .C(clk),
+    .D(\blk00000001/sig0000013f ),
+    .Q(p[29])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000b  (
+    .C(clk),
+    .D(\blk00000001/sig00000140 ),
+    .Q(p[30])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk0000000a  (
+    .C(clk),
+    .D(\blk00000001/sig00000141 ),
+    .Q(p[31])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000009  (
+    .C(clk),
+    .D(\blk00000001/sig00000142 ),
+    .Q(p[32])
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \blk00000001/blk00000008  (
+    .C(clk),
+    .D(\blk00000001/sig00000143 ),
+    .Q(p[33])
+  );
+  DSP48A1 #(
+    .A0REG ( 0 ),
+    .A1REG ( 1 ),
+    .B0REG ( 0 ),
+    .B1REG ( 1 ),
+    .CARRYINREG ( 0 ),
+    .CARRYINSEL ( "OPMODE5" ),
+    .CREG ( 0 ),
+    .DREG ( 0 ),
+    .MREG ( 0 ),
+    .OPMODEREG ( 0 ),
+    .PREG ( 0 ),
+    .RSTTYPE ( "SYNC" ),
+    .CARRYOUTREG ( 0 ))
+  \blk00000001/blk00000007  (
+    .CECARRYIN(\blk00000001/sig000000b3 ),
+    .RSTC(\blk00000001/sig000000b3 ),
+    .RSTCARRYIN(\blk00000001/sig000000b3 ),
+    .CED(\blk00000001/sig000000b3 ),
+    .RSTD(\blk00000001/sig000000b3 ),
+    .CEOPMODE(\blk00000001/sig000000b3 ),
+    .CEC(\blk00000001/sig000000b3 ),
+    .CARRYOUTF(\NLW_blk00000001/blk00000007_CARRYOUTF_UNCONNECTED ),
+    .RSTOPMODE(\blk00000001/sig000000b3 ),
+    .RSTM(\blk00000001/sig000000b3 ),
+    .CLK(clk),
+    .RSTB(\blk00000001/sig000000b3 ),
+    .CEM(\blk00000001/sig000000b3 ),
+    .CEB(\blk00000001/sig000000b2 ),
+    .CARRYIN(\blk00000001/sig000000b3 ),
+    .CEP(\blk00000001/sig000000b3 ),
+    .CEA(\blk00000001/sig000000b2 ),
+    .CARRYOUT(\NLW_blk00000001/blk00000007_CARRYOUT_UNCONNECTED ),
+    .RSTA(\blk00000001/sig000000b3 ),
+    .RSTP(\blk00000001/sig000000b3 ),
+    .B({\blk00000001/sig000000b3 , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+    .BCOUT({\blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 , \blk00000001/sig000001c3 , 
+\blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001bf , \blk00000001/sig000001be , 
+\blk00000001/sig000001bd , \blk00000001/sig000001bc , \blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 , 
+\blk00000001/sig000001b8 , \blk00000001/sig000001b7 , \blk00000001/sig000001b6 }),
+    .PCIN({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }),
+    .C({\NLW_blk00000001/blk00000007_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<43>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<37>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000007_C<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_C<0>_UNCONNECTED }),
+    .P({\blk00000001/sig000001a4 , \blk00000001/sig000001a3 , \blk00000001/sig000001a2 , \blk00000001/sig000001a1 , \blk00000001/sig000001a0 , 
+\blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d , \blk00000001/sig0000019c , \blk00000001/sig0000019b , 
+\blk00000001/sig0000019a , \blk00000001/sig00000199 , \blk00000001/sig00000198 , \blk00000001/sig00000197 , \blk00000001/sig00000196 , 
+\blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , \blk00000001/sig00000192 , \blk00000001/sig00000191 , 
+\blk00000001/sig00000190 , \blk00000001/sig0000018f , \blk00000001/sig0000018e , \blk00000001/sig0000018d , \blk00000001/sig0000018c , 
+\blk00000001/sig0000018b , \blk00000001/sig0000018a , \blk00000001/sig00000189 , \blk00000001/sig00000188 , \blk00000001/sig00000187 , 
+\blk00000001/sig00000186 , \blk00000001/sig000001b5 , \blk00000001/sig000001b4 , \blk00000001/sig000001b3 , \blk00000001/sig000001b2 , 
+\blk00000001/sig000001b1 , \blk00000001/sig000001b0 , \blk00000001/sig000001af , \blk00000001/sig000001ae , \blk00000001/sig000001ad , 
+\blk00000001/sig000001ac , \blk00000001/sig000001ab , \blk00000001/sig000001aa , \blk00000001/sig000001a9 , \blk00000001/sig000001a8 , 
+\blk00000001/sig000001a7 , \blk00000001/sig000001a6 , \blk00000001/sig000001a5 }),
+    .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }),
+    .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }),
+    .PCOUT({\blk00000001/sig00000185 , \blk00000001/sig00000184 , \blk00000001/sig00000183 , \blk00000001/sig00000182 , \blk00000001/sig00000181 , 
+\blk00000001/sig00000180 , \blk00000001/sig0000017f , \blk00000001/sig0000017e , \blk00000001/sig0000017d , \blk00000001/sig0000017c , 
+\blk00000001/sig0000017b , \blk00000001/sig0000017a , \blk00000001/sig00000179 , \blk00000001/sig00000178 , \blk00000001/sig00000177 , 
+\blk00000001/sig00000176 , \blk00000001/sig00000175 , \blk00000001/sig00000174 , \blk00000001/sig00000173 , \blk00000001/sig00000172 , 
+\blk00000001/sig00000171 , \blk00000001/sig00000170 , \blk00000001/sig0000016f , \blk00000001/sig0000016e , \blk00000001/sig0000016d , 
+\blk00000001/sig0000016c , \blk00000001/sig0000016b , \blk00000001/sig0000016a , \blk00000001/sig00000169 , \blk00000001/sig00000168 , 
+\blk00000001/sig00000167 , \blk00000001/sig00000166 , \blk00000001/sig00000165 , \blk00000001/sig00000164 , \blk00000001/sig00000163 , 
+\blk00000001/sig00000162 , \blk00000001/sig00000161 , \blk00000001/sig00000160 , \blk00000001/sig0000015f , \blk00000001/sig0000015e , 
+\blk00000001/sig0000015d , \blk00000001/sig0000015c , \blk00000001/sig0000015b , \blk00000001/sig0000015a , \blk00000001/sig00000159 , 
+\blk00000001/sig00000158 , \blk00000001/sig00000157 , \blk00000001/sig00000156 }),
+    .A({\blk00000001/sig000000b3 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
+    .M({\NLW_blk00000001/blk00000007_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000007_M<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000007_M<0>_UNCONNECTED })
+  );
+  DSP48A1 #(
+    .A0REG ( 0 ),
+    .A1REG ( 1 ),
+    .B0REG ( 0 ),
+    .B1REG ( 1 ),
+    .CARRYINREG ( 0 ),
+    .CARRYINSEL ( "OPMODE5" ),
+    .CREG ( 0 ),
+    .DREG ( 0 ),
+    .MREG ( 0 ),
+    .OPMODEREG ( 0 ),
+    .PREG ( 0 ),
+    .RSTTYPE ( "SYNC" ),
+    .CARRYOUTREG ( 0 ))
+  \blk00000001/blk00000006  (
+    .CECARRYIN(\blk00000001/sig000000b3 ),
+    .RSTC(\blk00000001/sig000000b3 ),
+    .RSTCARRYIN(\blk00000001/sig000000b3 ),
+    .CED(\blk00000001/sig000000b3 ),
+    .RSTD(\blk00000001/sig000000b3 ),
+    .CEOPMODE(\blk00000001/sig000000b3 ),
+    .CEC(\blk00000001/sig000000b3 ),
+    .CARRYOUTF(\NLW_blk00000001/blk00000006_CARRYOUTF_UNCONNECTED ),
+    .RSTOPMODE(\blk00000001/sig000000b3 ),
+    .RSTM(\blk00000001/sig000000b3 ),
+    .CLK(clk),
+    .RSTB(\blk00000001/sig000000b3 ),
+    .CEM(\blk00000001/sig000000b3 ),
+    .CEB(\blk00000001/sig000000b2 ),
+    .CARRYIN(\blk00000001/sig000000b3 ),
+    .CEP(\blk00000001/sig000000b3 ),
+    .CEA(\blk00000001/sig000000b2 ),
+    .CARRYOUT(\NLW_blk00000001/blk00000006_CARRYOUT_UNCONNECTED ),
+    .RSTA(\blk00000001/sig000000b3 ),
+    .RSTP(\blk00000001/sig000000b3 ),
+    .B({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , b[31], b[30], b[29], b[28], b[27], b[26], b[25], b[24], b[23]
+, b[22], b[21], b[20], b[19], b[18], b[17]}),
+    .BCOUT({\blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 , \blk00000001/sig00000152 , \blk00000001/sig00000151 , 
+\blk00000001/sig00000150 , \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000014d , \blk00000001/sig0000014c , 
+\blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 , \blk00000001/sig00000148 , \blk00000001/sig00000147 , 
+\blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000144 }),
+    .PCIN({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , 
+\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , 
+\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , 
+\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , 
+\blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , 
+\blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , 
+\blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 , 
+\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , 
+\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 , 
+\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 }),
+    .C({\NLW_blk00000001/blk00000006_C<47>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<45>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<44>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<43>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<42>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<41>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<39>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<38>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<37>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<36>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<35>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<33>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<32>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<30>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<29>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<27>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<26>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<24>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<23>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<21>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<20>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<18>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_C<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_C<0>_UNCONNECTED }),
+    .P({\blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , \blk00000001/sig0000012f , \blk00000001/sig0000012e , 
+\blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a , \blk00000001/sig00000129 , 
+\blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 , \blk00000001/sig00000124 , 
+\blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 , \blk00000001/sig0000011f , 
+\blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , \blk00000001/sig0000011b , \blk00000001/sig0000011a , 
+\blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 , \blk00000001/sig00000115 , 
+\blk00000001/sig00000114 , \blk00000001/sig00000143 , \blk00000001/sig00000142 , \blk00000001/sig00000141 , \blk00000001/sig00000140 , 
+\blk00000001/sig0000013f , \blk00000001/sig0000013e , \blk00000001/sig0000013d , \blk00000001/sig0000013c , \blk00000001/sig0000013b , 
+\blk00000001/sig0000013a , \blk00000001/sig00000139 , \blk00000001/sig00000138 , \blk00000001/sig00000137 , \blk00000001/sig00000136 , 
+\blk00000001/sig00000135 , \blk00000001/sig00000134 , \blk00000001/sig00000133 }),
+    .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }),
+    .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }),
+    .PCOUT({\blk00000001/sig00000113 , \blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , 
+\blk00000001/sig0000010e , \blk00000001/sig0000010d , \blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , 
+\blk00000001/sig00000109 , \blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , 
+\blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 , 
+\blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , 
+\blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000f6 , 
+\blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , 
+\blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ed , \blk00000001/sig000000ec , 
+\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , 
+\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 }),
+    .A({\blk00000001/sig000000b3 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
+    .M({\NLW_blk00000001/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000006_M<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000006_M<0>_UNCONNECTED })
+  );
+  DSP48A1 #(
+    .A0REG ( 0 ),
+    .A1REG ( 1 ),
+    .B0REG ( 0 ),
+    .B1REG ( 0 ),
+    .CARRYINREG ( 0 ),
+    .CARRYINSEL ( "OPMODE5" ),
+    .CREG ( 0 ),
+    .DREG ( 0 ),
+    .MREG ( 0 ),
+    .OPMODEREG ( 0 ),
+    .PREG ( 0 ),
+    .RSTTYPE ( "SYNC" ),
+    .CARRYOUTREG ( 0 ))
+  \blk00000001/blk00000005  (
+    .CECARRYIN(\blk00000001/sig000000b3 ),
+    .RSTC(\blk00000001/sig000000b3 ),
+    .RSTCARRYIN(\blk00000001/sig000000b3 ),
+    .CED(\blk00000001/sig000000b3 ),
+    .RSTD(\blk00000001/sig000000b3 ),
+    .CEOPMODE(\blk00000001/sig000000b3 ),
+    .CEC(\blk00000001/sig000000b3 ),
+    .CARRYOUTF(\NLW_blk00000001/blk00000005_CARRYOUTF_UNCONNECTED ),
+    .RSTOPMODE(\blk00000001/sig000000b3 ),
+    .RSTM(\blk00000001/sig000000b3 ),
+    .CLK(clk),
+    .RSTB(\blk00000001/sig000000b3 ),
+    .CEM(\blk00000001/sig000000b3 ),
+    .CEB(\blk00000001/sig000000b3 ),
+    .CARRYIN(\blk00000001/sig000000b3 ),
+    .CEP(\blk00000001/sig000000b3 ),
+    .CEA(\blk00000001/sig000000b2 ),
+    .CARRYOUT(\NLW_blk00000001/blk00000005_CARRYOUT_UNCONNECTED ),
+    .RSTA(\blk00000001/sig000000b3 ),
+    .RSTP(\blk00000001/sig000000b3 ),
+    .B({\blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 , \blk00000001/sig000001c3 , 
+\blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001bf , \blk00000001/sig000001be , 
+\blk00000001/sig000001bd , \blk00000001/sig000001bc , \blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 , 
+\blk00000001/sig000001b8 , \blk00000001/sig000001b7 , \blk00000001/sig000001b6 }),
+    .BCOUT({\NLW_blk00000001/blk00000005_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<14>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<12>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<8>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<6>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<2>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000005_BCOUT<0>_UNCONNECTED }),
+    .PCIN({\blk00000001/sig00000185 , \blk00000001/sig00000184 , \blk00000001/sig00000183 , \blk00000001/sig00000182 , \blk00000001/sig00000181 , 
+\blk00000001/sig00000180 , \blk00000001/sig0000017f , \blk00000001/sig0000017e , \blk00000001/sig0000017d , \blk00000001/sig0000017c , 
+\blk00000001/sig0000017b , \blk00000001/sig0000017a , \blk00000001/sig00000179 , \blk00000001/sig00000178 , \blk00000001/sig00000177 , 
+\blk00000001/sig00000176 , \blk00000001/sig00000175 , \blk00000001/sig00000174 , \blk00000001/sig00000173 , \blk00000001/sig00000172 , 
+\blk00000001/sig00000171 , \blk00000001/sig00000170 , \blk00000001/sig0000016f , \blk00000001/sig0000016e , \blk00000001/sig0000016d , 
+\blk00000001/sig0000016c , \blk00000001/sig0000016b , \blk00000001/sig0000016a , \blk00000001/sig00000169 , \blk00000001/sig00000168 , 
+\blk00000001/sig00000167 , \blk00000001/sig00000166 , \blk00000001/sig00000165 , \blk00000001/sig00000164 , \blk00000001/sig00000163 , 
+\blk00000001/sig00000162 , \blk00000001/sig00000161 , \blk00000001/sig00000160 , \blk00000001/sig0000015f , \blk00000001/sig0000015e , 
+\blk00000001/sig0000015d , \blk00000001/sig0000015c , \blk00000001/sig0000015b , \blk00000001/sig0000015a , \blk00000001/sig00000159 , 
+\blk00000001/sig00000158 , \blk00000001/sig00000157 , \blk00000001/sig00000156 }),
+    .C({\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , 
+\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , 
+\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , 
+\blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a4 , \blk00000001/sig000001a3 , \blk00000001/sig000001a2 , 
+\blk00000001/sig000001a1 , \blk00000001/sig000001a0 , \blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d , 
+\blk00000001/sig0000019c , \blk00000001/sig0000019b , \blk00000001/sig0000019a , \blk00000001/sig00000199 , \blk00000001/sig00000198 , 
+\blk00000001/sig00000197 , \blk00000001/sig00000196 , \blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , 
+\blk00000001/sig00000192 , \blk00000001/sig00000191 , \blk00000001/sig00000190 , \blk00000001/sig0000018f , \blk00000001/sig0000018e , 
+\blk00000001/sig0000018d , \blk00000001/sig0000018c , \blk00000001/sig0000018b , \blk00000001/sig0000018a , \blk00000001/sig00000189 , 
+\blk00000001/sig00000188 , \blk00000001/sig00000187 , \blk00000001/sig00000186 }),
+    .P({\NLW_blk00000001/blk00000005_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<43>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<37>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_P<0>_UNCONNECTED }),
+    .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 , 
+\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }),
+    .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }),
+    .PCOUT({\blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , 
+\blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , 
+\blk00000001/sig000000d9 , \blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , 
+\blk00000001/sig000000d4 , \blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 , 
+\blk00000001/sig000000cf , \blk00000001/sig000000ce , \blk00000001/sig000000cd , \blk00000001/sig000000cc , \blk00000001/sig000000cb , 
+\blk00000001/sig000000ca , \blk00000001/sig000000c9 , \blk00000001/sig000000c8 , \blk00000001/sig000000c7 , \blk00000001/sig000000c6 , 
+\blk00000001/sig000000c5 , \blk00000001/sig000000c4 , \blk00000001/sig000000c3 , \blk00000001/sig000000c2 , \blk00000001/sig000000c1 , 
+\blk00000001/sig000000c0 , \blk00000001/sig000000bf , \blk00000001/sig000000be , \blk00000001/sig000000bd , \blk00000001/sig000000bc , 
+\blk00000001/sig000000bb , \blk00000001/sig000000ba , \blk00000001/sig000000b9 , \blk00000001/sig000000b8 , \blk00000001/sig000000b7 , 
+\blk00000001/sig000000b6 , \blk00000001/sig000000b5 , \blk00000001/sig000000b4 }),
+    .A({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23]
+, a[22], a[21], a[20], a[19], a[18], a[17]}),
+    .M({\NLW_blk00000001/blk00000005_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000005_M<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000005_M<0>_UNCONNECTED })
+  );
+  DSP48A1 #(
+    .A0REG ( 0 ),
+    .A1REG ( 1 ),
+    .B0REG ( 0 ),
+    .B1REG ( 0 ),
+    .CARRYINREG ( 0 ),
+    .CARRYINSEL ( "OPMODE5" ),
+    .CREG ( 0 ),
+    .DREG ( 0 ),
+    .MREG ( 0 ),
+    .OPMODEREG ( 0 ),
+    .PREG ( 1 ),
+    .RSTTYPE ( "SYNC" ),
+    .CARRYOUTREG ( 0 ))
+  \blk00000001/blk00000004  (
+    .CECARRYIN(\blk00000001/sig000000b3 ),
+    .RSTC(\blk00000001/sig000000b3 ),
+    .RSTCARRYIN(\blk00000001/sig000000b3 ),
+    .CED(\blk00000001/sig000000b3 ),
+    .RSTD(\blk00000001/sig000000b3 ),
+    .CEOPMODE(\blk00000001/sig000000b3 ),
+    .CEC(\blk00000001/sig000000b3 ),
+    .CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ),
+    .RSTOPMODE(\blk00000001/sig000000b3 ),
+    .RSTM(\blk00000001/sig000000b3 ),
+    .CLK(clk),
+    .RSTB(\blk00000001/sig000000b3 ),
+    .CEM(\blk00000001/sig000000b3 ),
+    .CEB(\blk00000001/sig000000b3 ),
+    .CARRYIN(\blk00000001/sig000000b3 ),
+    .CEP(\blk00000001/sig000000b2 ),
+    .CEA(\blk00000001/sig000000b2 ),
+    .CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ),
+    .RSTA(\blk00000001/sig000000b3 ),
+    .RSTP(\blk00000001/sig000000b3 ),
+    .B({\blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 , \blk00000001/sig00000152 , \blk00000001/sig00000151 , 
+\blk00000001/sig00000150 , \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000014d , \blk00000001/sig0000014c , 
+\blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 , \blk00000001/sig00000148 , \blk00000001/sig00000147 , 
+\blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000144 }),
+    .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }),
+    .PCIN({\blk00000001/sig00000113 , \blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , 
+\blk00000001/sig0000010e , \blk00000001/sig0000010d , \blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , 
+\blk00000001/sig00000109 , \blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , 
+\blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 , 
+\blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd , \blk00000001/sig000000fc , \blk00000001/sig000000fb , 
+\blk00000001/sig000000fa , \blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000f6 , 
+\blk00000001/sig000000f5 , \blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig000000f2 , \blk00000001/sig000000f1 , 
+\blk00000001/sig000000f0 , \blk00000001/sig000000ef , \blk00000001/sig000000ee , \blk00000001/sig000000ed , \blk00000001/sig000000ec , 
+\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 , 
+\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/sig000000e4 }),
+    .C({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , 
+\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , 
+\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , 
+\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , 
+\blk00000001/sig0000012f , \blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , 
+\blk00000001/sig0000012a , \blk00000001/sig00000129 , \blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , 
+\blk00000001/sig00000125 , \blk00000001/sig00000124 , \blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , 
+\blk00000001/sig00000120 , \blk00000001/sig0000011f , \blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , 
+\blk00000001/sig0000011b , \blk00000001/sig0000011a , \blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , 
+\blk00000001/sig00000116 , \blk00000001/sig00000115 , \blk00000001/sig00000114 }),
+    .P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , p[63], p[62], p[61], p[60], p[59], p[58], p[57], p[56], p[55], p[54], p[53], p[52], p[51], p[50], 
+p[49], p[48], p[47], p[46], p[45], p[44], p[43], p[42], p[41], p[40], p[39], p[38], p[37], p[36], p[35], p[34]}),
+    .OPMODE({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 , 
+\blk00000001/sig000000b2 , \blk00000001/sig000000b3 , \blk00000001/sig000000b2 }),
+    .D({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , 
+\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 }),
+    .PCOUT({\blk00000001/sig00000082 , \blk00000001/sig00000083 , \blk00000001/sig00000084 , \blk00000001/sig00000085 , \blk00000001/sig00000086 , 
+\blk00000001/sig00000087 , \blk00000001/sig00000088 , \blk00000001/sig00000089 , \blk00000001/sig0000008a , \blk00000001/sig0000008b , 
+\blk00000001/sig0000008c , \blk00000001/sig0000008d , \blk00000001/sig0000008e , \blk00000001/sig0000008f , \blk00000001/sig00000090 , 
+\blk00000001/sig00000091 , \blk00000001/sig00000092 , \blk00000001/sig00000093 , \blk00000001/sig00000094 , \blk00000001/sig00000095 , 
+\blk00000001/sig00000096 , \blk00000001/sig00000097 , \blk00000001/sig00000098 , \blk00000001/sig00000099 , \blk00000001/sig0000009a , 
+\blk00000001/sig0000009b , \blk00000001/sig0000009c , \blk00000001/sig0000009d , \blk00000001/sig0000009e , \blk00000001/sig0000009f , 
+\blk00000001/sig000000a0 , \blk00000001/sig000000a1 , \blk00000001/sig000000a2 , \blk00000001/sig000000a3 , \blk00000001/sig000000a4 , 
+\blk00000001/sig000000a5 , \blk00000001/sig000000a6 , \blk00000001/sig000000a7 , \blk00000001/sig000000a8 , \blk00000001/sig000000a9 , 
+\blk00000001/sig000000aa , \blk00000001/sig000000ab , \blk00000001/sig000000ac , \blk00000001/sig000000ad , \blk00000001/sig000000ae , 
+\blk00000001/sig000000af , \blk00000001/sig000000b0 , \blk00000001/sig000000b1 }),
+    .A({\blk00000001/sig000000b3 , \blk00000001/sig000000b3 , \blk00000001/sig000000b3 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23]
+, a[22], a[21], a[20], a[19], a[18], a[17]}),
+    .M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED })
+  );
+  GND   \blk00000001/blk00000003  (
+    .G(\blk00000001/sig000000b3 )
+  );
+  VCC   \blk00000001/blk00000002  (
+    .P(\blk00000001/sig000000b2 )
+  );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/src/rtl/ipcore/multiplier_s6.veo b/src/rtl/ipcore/multiplier_s6.veo
new file mode 100644
index 0000000..fede3ea
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.veo
@@ -0,0 +1,65 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2015 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:mult_gen:11.2         *
+*                                                                              *
+*     Multiplication is a fundamental DSP operation.  This core allows         *
+*     parallel and constant-coefficient multipliers to be generated.  The      *
+*     user can specify if dedicated hardware multipliers, slice logic or a     *
+*     combination of resources should be utilized.                             *
+*******************************************************************************/
+
+// Interfaces:
+//    a_intf
+//    clk_intf
+//    sclr_intf
+//    ce_intf
+//    b_intf
+//    zero_detect_intf
+//    p_intf
+//    pcasc_intf
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+multiplier_s6 your_instance_name (
+  .clk(clk), // input clk
+  .a(a), // input [31 : 0] a
+  .b(b), // input [31 : 0] b
+  .p(p) // output [63 : 0] p
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file multiplier_s6.v when simulating
+// the core, multiplier_s6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/src/rtl/ipcore/multiplier_s6.xco b/src/rtl/ipcore/multiplier_s6.xco
new file mode 100644
index 0000000..5dcc8fd
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.xco
@@ -0,0 +1,68 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Fri Jul 10 14:51:47 2015
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:mult_gen:11.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Multiplier xilinx.com:ip:mult_gen:11.2
+# END Select
+# BEGIN Parameters
+CSET ccmimp=Distributed_Memory
+CSET clockenable=false
+CSET component_name=multiplier_s6
+CSET constvalue=129
+CSET internaluser=0
+CSET multiplier_construction=Use_Mults
+CSET multtype=Parallel_Multiplier
+CSET optgoal=Speed
+CSET outputwidthhigh=63
+CSET outputwidthlow=0
+CSET pipestages=2
+CSET portatype=Unsigned
+CSET portawidth=32
+CSET portbtype=Unsigned
+CSET portbwidth=32
+CSET roundpoint=0
+CSET sclrcepriority=SCLR_Overrides_CE
+CSET syncclear=false
+CSET use_custom_output_width=false
+CSET userounding=false
+CSET zerodetect=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2013-07-22T11:36:26Z
+# END Extra information
+GENERATE
+# CRC: 66788057
diff --git a/src/rtl/ipcore/multiplier_s6.xise b/src/rtl/ipcore/multiplier_s6.xise
new file mode 100644
index 0000000..483e01a
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="multiplier_s6.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="multiplier_s6.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|multiplier_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="multiplier_s6.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/multiplier_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="multiplier_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-07-10T17:52:14" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7F8BDEE2A3114E3F8A92547B65F9CA26" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf
new file mode 100644
index 0000000..b589be0
Binary files /dev/null and b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_ds255.pdf differ
diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt
new file mode 100644
index 0000000..e50dfe8
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_readme.txt
@@ -0,0 +1,184 @@
+CHANGE LOG for Xilinx LogiCORE Multiplier 11.2
+
+Release Date:  October 2, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1.   INTRODUCTION
+2.   DEVICE SUPPORT
+3.   NEW FEATURE HISTORY
+4.   RESOLVED ISSUES
+5.   KNOWN ISSUES & LIMITATIONS
+6.   TECHNICAL SUPPORT & FEEDBACK
+7.   CORE RELEASE HISTORY
+8.   LEGAL DISCLAIMER
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+  This file contains the change log for all released versions of the Xilinx
+  LogiCORE IP Multiplier.
+
+  For the latest core updates, see the product page at:
+
+    http://www.xilinx.com/products/ipcenter/multiplier.htm
+
+  For installation instructions for this release, please go to:
+
+    http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+  For system requirements:
+
+    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+
+2. DEVICE SUPPORT
+
+  2.1. ISE
+
+    The following device families are supported by the core for this release:
+
+    All Series 7 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Virtex-4 devices
+    All Spartan-3 devices
+
+
+3. NEW FEATURE HISTORY
+
+  3.1 ISE
+
+  v11.2
+    - Ongoing new device support.
+
+
+4. RESOLVED ISSUES
+
+  4.1 ISE
+
+    - N/A
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+  The following are known issues for this core at time of release:
+
+  5.1 ISE
+    - Output bus indices in .ASY file do not match instantiation template bus indices
+      when a custom output width is selected.
+       - The indices of the P output bus will be P[X:Y] in the .ASY file and P[X-Y:0] in
+         the core instantiation template.
+       - Affects schematic flow only.
+       - Manually editing the .ASY file to correct the bus width can work around this issue.
+       - CR456322 and CR435084
+       - Answer Record 30807
+
+    - Block Memory resource estimates may be inaccurate for constant-coefficient multipliers
+      with large constants and large A input widths (> 35 bits)
+       - The map report should be consulted to determine the true block memory count
+       - CR469169
+       - Answer Record 30810
+
+  - For a comprehensive listing of Known Issues for this core, please see the IP
+    Release Notes Guide,
+
+    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+  To obtain technical support, create a WebCase at www.xilinx.com/support.
+  Questions are routed to a team with expertise using this product.
+  Please feel free to leave feedback on this IP under the "Leave Feedback"
+  menu item in Vivado/PlanAhead.
+
+  Xilinx provides technical support for use of this product when used
+  according to the guidelines described in the core documentation, and
+  cannot guarantee timing, functionality, or support of this product for
+  designs that do not follow specified guidelines.
+
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+  www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+7. CORE RELEASE HISTORY
+
+Date        By            Version      Description
+================================================================================
+02/10/2013  Xilinx, Inc.  11.2         ISE 14.7 support and Production support for Series 7
+06/19/2012  Xilinx, Inc.  11.2         ISE 14.6 support
+03/20/2012  Xilinx, Inc.  11.2         ISE 14.5 support. 
+12/18/2012  Xilinx, Inc.  11.2         ISE 14.4 and Vivado 2012.4 support
+10/16/2012  Xilinx, Inc.  11.2         ISE 14.3 and Vivado 2012.3 support
+07/25/2012  Xilinx, Inc.  11.2         ISE 14.2 and Vivado 2012.2 support
+04/24/2012  Xilinx, Inc.  11.2         ISE 14.1 and Vivado 2012.1 support
+01/11/2012  Xilinx, Inc.  11.2         ISE 13.4 support
+10/19/2011  Xilinx, Inc.  11.2         ISE 13.3 support
+06/22/2011  Xilinx, Inc.  11.2         ISE 13.2 support, Artix-7 support
+03/01/2011  Xilinx, Inc.  11.2         ISE 13.1 support, Virtex-7 and Kintex-7 support
+10/29/2010  Xilinx, Inc.  11.2         ISE 7 Series Monthly Snapshot - (O.28), ISE 13.0.2 support
+07/30/2010  Xilinx, Inc.  11.2         ISE 13.0.1, Virtex-7 and Kintex-7 support
+04/19/2010  Xilinx, Inc.  11.2         ISE 12.1, Virtex-6Q and Spartan-6Q support
+12/02/2009  Xilinx, Inc.  11.2         ISE 11.4 support, Spartan-6L and Automotive Spartan6 support
+09/16/2009  Xilinx, Inc.  11.2         ISE 11.3 support, area optimized LUT multiplier
+04/24/2009  Xilinx, Inc.  11.0         ISE 11.1 support, Virtex-6, Spartan-6 support
+04/25/2008  Xilinx, Inc.  10.1         ISE 10.1 support
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+  (c) Copyright 2000 - 2013 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same.
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical
+  Applications"). Customer assumes the sole risk and
+  liability of any use of Xilinx products in Critical
+  Applications, subject only to applicable laws and
+  regulations governing limitations on product liability.
+
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
diff --git a/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html
new file mode 100644
index 0000000..ebe6f62
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6/doc/mult_gen_v11_2_vinfo.html
@@ -0,0 +1,195 @@
+<HTML>
+<HEAD>
+<TITLE>mult_gen_v11_2_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for Xilinx LogiCORE Multiplier 11.2
+
+Release Date:  October 2, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1.   INTRODUCTION
+2.   DEVICE SUPPORT
+3.   NEW FEATURE HISTORY
+4.   RESOLVED ISSUES
+5.   KNOWN ISSUES & LIMITATIONS
+6.   TECHNICAL SUPPORT & FEEDBACK
+7.   CORE RELEASE HISTORY
+8.   LEGAL DISCLAIMER
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+  This file contains the change log for all released versions of the Xilinx
+  LogiCORE IP Multiplier.
+
+  For the latest core updates, see the product page at:
+
+    <A HREF="http://www.xilinx.com/products/ipcenter/multiplier.htm">www.xilinx.com/products/ipcenter/multiplier.htm</A>
+
+  For installation instructions for this release, please go to:
+
+    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+  For system requirements:
+
+    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+
+2. DEVICE SUPPORT
+
+  2.1. ISE
+
+    The following device families are supported by the core for this release:
+
+    All Series 7 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Virtex-4 devices
+    All Spartan-3 devices
+
+
+3. NEW FEATURE HISTORY
+
+  3.1 ISE
+
+  v11.2
+    - Ongoing new device support.
+
+
+4. RESOLVED ISSUES
+
+  4.1 ISE
+
+    - N/A
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+  The following are known issues for this core at time of release:
+
+  5.1 ISE
+    - Output bus indices in .ASY file do not match instantiation template bus indices
+      when a custom output width is selected.
+       - The indices of the P output bus will be P[X:Y] in the .ASY file and P[X-Y:0] in
+         the core instantiation template.
+       - Affects schematic flow only.
+       - Manually editing the .ASY file to correct the bus width can work around this issue.
+       - CR456322 and CR435084
+       - Answer Record 30807
+
+    - Block Memory resource estimates may be inaccurate for constant-coefficient multipliers
+      with large constants and large A input widths (> 35 bits)
+       - The map report should be consulted to determine the true block memory count
+       - CR469169
+       - Answer Record 30810
+
+  - For a comprehensive listing of Known Issues for this core, please see the IP
+    Release Notes Guide,
+
+    <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+  To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+  Questions are routed to a team with expertise using this product.
+  Please feel free to leave feedback on this IP under the "Leave Feedback"
+  menu item in Vivado/PlanAhead.
+
+  Xilinx provides technical support for use of this product when used
+  according to the guidelines described in the core documentation, and
+  cannot guarantee timing, functionality, or support of this product for
+  designs that do not follow specified guidelines.
+
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+  <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+
+7. CORE RELEASE HISTORY
+
+Date        By            Version      Description
+================================================================================
+02/10/2013  Xilinx, Inc.  11.2         ISE 14.7 support and Production support for Series 7
+06/19/2012  Xilinx, Inc.  11.2         ISE 14.6 support
+03/20/2012  Xilinx, Inc.  11.2         ISE 14.5 support. 
+12/18/2012  Xilinx, Inc.  11.2         ISE 14.4 and Vivado 2012.4 support
+10/16/2012  Xilinx, Inc.  11.2         ISE 14.3 and Vivado 2012.3 support
+07/25/2012  Xilinx, Inc.  11.2         ISE 14.2 and Vivado 2012.2 support
+04/24/2012  Xilinx, Inc.  11.2         ISE 14.1 and Vivado 2012.1 support
+01/11/2012  Xilinx, Inc.  11.2         ISE 13.4 support
+10/19/2011  Xilinx, Inc.  11.2         ISE 13.3 support
+06/22/2011  Xilinx, Inc.  11.2         ISE 13.2 support, Artix-7 support
+03/01/2011  Xilinx, Inc.  11.2         ISE 13.1 support, Virtex-7 and Kintex-7 support
+10/29/2010  Xilinx, Inc.  11.2         ISE 7 Series Monthly Snapshot - (O.28), ISE 13.0.2 support
+07/30/2010  Xilinx, Inc.  11.2         ISE 13.0.1, Virtex-7 and Kintex-7 support
+04/19/2010  Xilinx, Inc.  11.2         ISE 12.1, Virtex-6Q and Spartan-6Q support
+12/02/2009  Xilinx, Inc.  11.2         ISE 11.4 support, Spartan-6L and Automotive Spartan6 support
+09/16/2009  Xilinx, Inc.  11.2         ISE 11.3 support, area optimized LUT multiplier
+04/24/2009  Xilinx, Inc.  11.0         ISE 11.1 support, Virtex-6, Spartan-6 support
+04/25/2008  Xilinx, Inc.  10.1         ISE 10.1 support
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+  (c) Copyright 2000 - 2013 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same.
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical
+  Applications"). Customer assumes the sole risk and
+  liability of any use of Xilinx products in Critical
+  Applications, subject only to applicable laws and
+  regulations governing limitations on product liability.
+
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/src/rtl/ipcore/multiplier_s6_flist.txt b/src/rtl/ipcore/multiplier_s6_flist.txt
new file mode 100644
index 0000000..4896d2e
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6_flist.txt
@@ -0,0 +1,14 @@
+# Output products list for <multiplier_s6>
+multiplier_s6.asy
+multiplier_s6.gise
+multiplier_s6.ngc
+multiplier_s6.sym
+multiplier_s6.v
+multiplier_s6.veo
+multiplier_s6.xco
+multiplier_s6.xise
+multiplier_s6\doc\mult_gen_ds255.pdf
+multiplier_s6\doc\mult_gen_v11_2_readme.txt
+multiplier_s6\doc\mult_gen_v11_2_vinfo.html
+multiplier_s6_flist.txt
+multiplier_s6_xmdf.tcl
diff --git a/src/rtl/ipcore/multiplier_s6_xmdf.tcl b/src/rtl/ipcore/multiplier_s6_xmdf.tcl
new file mode 100644
index 0000000..d528e82
--- /dev/null
+++ b/src/rtl/ipcore/multiplier_s6_xmdf.tcl
@@ -0,0 +1,83 @@
+# The package naming convention is <core_name>_xmdf
+package provide multiplier_s6_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::multiplier_s6_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::multiplier_s6_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name multiplier_s6
+}
+# ::multiplier_s6_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::multiplier_s6_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_ds255.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_v11_2_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6/doc/mult_gen_v11_2_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path multiplier_s6_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module multiplier_s6
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/src/rtl/ipcore/subtractor_s6.asy b/src/rtl/ipcore/subtractor_s6.asy
new file mode 100644
index 0000000..560370c
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.asy
@@ -0,0 +1,25 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 subtractor_s6
+RECTANGLE Normal 32 32 256 416
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName a[31:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName b[31:0]
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName c_in
+PINATTR Polarity IN
+LINE Normal 288 80 256 80
+PIN 288 80 RIGHT 36
+PINATTR PinName c_out
+PINATTR Polarity OUT
+LINE Wide 288 112 256 112
+PIN 288 112 RIGHT 36
+PINATTR PinName s[31:0]
+PINATTR Polarity OUT
+
diff --git a/src/rtl/ipcore/subtractor_s6.gise b/src/rtl/ipcore/subtractor_s6.gise
new file mode 100644
index 0000000..c2a3b35
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.gise
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="subtractor_s6.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="subtractor_s6.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="subtractor_s6.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="subtractor_s6.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8902187064276878470" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7048037620017930327" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1436912095" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3171076194908862408" xil_pn:start_ts="1436912095">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/src/rtl/ipcore/subtractor_s6.ncf b/src/rtl/ipcore/subtractor_s6.ncf
new file mode 100644
index 0000000..e69de29
diff --git a/src/rtl/ipcore/subtractor_s6.ngc b/src/rtl/ipcore/subtractor_s6.ngc
new file mode 100644
index 0000000..4a930b6
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$3g544<,[o}e~g`n;"2*73>(-80!<??;0:9MKVR\3K7=:4?>0285=<NFY__6O2>7;2=56=603CE\XZ5BBKM841=87;;7<65IORVP?B;9>0;2<;4198LQQVR\3HHCXZ31683:46<;;0BB][[:@>05?699918>7GAPTV9F956294:<6==:HLSQQ<f4:;1<3??;209MKVR\3h7?<4?>03877<H]]Z^X7]33083:47<;;0DYY^ZT;q?74<768;0?;4 at UURVP?K;;<0;2<>4498JJUSS2J6?;7>11297<?OIX\^1\NGA<5594;763=21CXZ_UU8S811=87;>7965OTVSQQ<WKF__09950?g82vj<<ixk><;-230?=<NFY__6B^BOEG?3?69=2K;^HI:;@3QAB2<I5:596O311<6?D:697?0M1?=>49B8459=2K7=90:;@>21;3<I5;=2:5N<0594;3<I5;<285N<0:=1>G;904? [...]
\ No newline at end of file
diff --git a/src/rtl/ipcore/subtractor_s6.sym b/src/rtl/ipcore/subtractor_s6.sym
new file mode 100644
index 0000000..23973dc
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.sym
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="subtractor_s6">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2015-7-10T14:50:53</timestamp>
+    <pin polarity="Input" x="0" y="80" name="a[31:0]" />
+    <pin polarity="Input" x="0" y="112" name="b[31:0]" />
+    <pin polarity="Input" x="0" y="208" name="c_in" />
+    <pin polarity="Output" x="288" y="80" name="c_out" />
+    <pin polarity="Output" x="288" y="112" name="s[31:0]" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">subtractor_s6</text>
+        <rect width="224" x="32" y="32" height="384" />
+        <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin a[31:0]" />
+        <line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin b[31:0]" />
+        <line x2="32" y1="208" y2="208" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin c_in" />
+        <line x2="256" y1="80" y2="80" x1="288" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="80" type="pin c_out" />
+        <line x2="256" y1="112" y2="112" style="linewidth:W" x1="288" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="252" y="112" type="pin s[31:0]" />
+    </graph>
+</symbol>
diff --git a/src/rtl/ipcore/subtractor_s6.v b/src/rtl/ipcore/subtractor_s6.v
new file mode 100644
index 0000000..f86097d
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.v
@@ -0,0 +1,364 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: P.20131013
+//  \   \         Application: netgen
+//  /   /         Filename: subtractor_s6.v
+// /___/   /\     Timestamp: Fri Jul 10 17:50:53 2015
+// \   \  /  \ 
+//  \___\/\___\
+//             
+// Command	: -w -sim -ofmt verilog E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.ngc E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.v 
+// Device	: 6slx45csg324-3
+// Input file	: E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.ngc
+// Output file	: E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/subtractor_s6.v
+// # of Modules	: 1
+// Design Name	: subtractor_s6
+// Xilinx        : e:\Xilinx\14.7\ISE_DS\ISE\
+//             
+// Purpose:    
+//     This verilog netlist is a verification model and uses simulation 
+//     primitives which may not represent the true implementation of the 
+//     device, however the netlist is functionally correct and should not 
+//     be modified. This file cannot be synthesized and should only be used 
+//     with supported simulation tools.
+//             
+// Reference:  
+//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//             
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module subtractor_s6 (
+  c_in, c_out, a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+  input c_in;
+  output c_out;
+  input [31 : 0] a;
+  input [31 : 0] b;
+  output [31 : 0] s;
+  
+  // synthesis translate_off
+  
+  wire \blk00000001/sig00000064 ;
+  wire \blk00000001/sig00000063 ;
+  wire \NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<47>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<46>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<45>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<44>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<43>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<42>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<41>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<40>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<39>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<38>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<37>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<36>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_PCOUT<0>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<35>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<33>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<30>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<27>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<24>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<21>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<18>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<15>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<12>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<9>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<6>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<3>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED ;
+  wire \NLW_blk00000001/blk00000004_M<0>_UNCONNECTED ;
+  DSP48A1 #(
+    .A0REG ( 0 ),
+    .A1REG ( 0 ),
+    .B0REG ( 0 ),
+    .B1REG ( 0 ),
+    .CARRYINREG ( 0 ),
+    .CARRYINSEL ( "OPMODE5" ),
+    .CREG ( 0 ),
+    .DREG ( 0 ),
+    .MREG ( 0 ),
+    .OPMODEREG ( 0 ),
+    .PREG ( 0 ),
+    .RSTTYPE ( "SYNC" ),
+    .CARRYOUTREG ( 0 ))
+  \blk00000001/blk00000004  (
+    .CECARRYIN(\blk00000001/sig00000064 ),
+    .RSTC(\blk00000001/sig00000064 ),
+    .RSTCARRYIN(\blk00000001/sig00000064 ),
+    .CED(\blk00000001/sig00000064 ),
+    .RSTD(\blk00000001/sig00000064 ),
+    .CEOPMODE(\blk00000001/sig00000064 ),
+    .CEC(\blk00000001/sig00000064 ),
+    .CARRYOUTF(\NLW_blk00000001/blk00000004_CARRYOUTF_UNCONNECTED ),
+    .RSTOPMODE(\blk00000001/sig00000064 ),
+    .RSTM(\blk00000001/sig00000064 ),
+    .CLK(\blk00000001/sig00000064 ),
+    .RSTB(\blk00000001/sig00000064 ),
+    .CEM(\blk00000001/sig00000064 ),
+    .CEB(\blk00000001/sig00000064 ),
+    .CARRYIN(\blk00000001/sig00000064 ),
+    .CEP(\blk00000001/sig00000064 ),
+    .CEA(\blk00000001/sig00000064 ),
+    .CARRYOUT(\NLW_blk00000001/blk00000004_CARRYOUT_UNCONNECTED ),
+    .RSTA(\blk00000001/sig00000064 ),
+    .RSTP(\blk00000001/sig00000064 ),
+    .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+    .BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED }),
+    .PCIN({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 }),
+    .C({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], 
+a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
+    .P({\NLW_blk00000001/blk00000004_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<43>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<37>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , c_out, s[31], s[30], s[29], s[28], s[27], s[26], s[25], s[24], s[23], s[22], s[21], s[20], s[19], 
+s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+    .OPMODE({\blk00000001/sig00000063 , \blk00000001/sig00000064 , c_in, \blk00000001/sig00000064 , \blk00000001/sig00000063 , 
+\blk00000001/sig00000063 , \blk00000001/sig00000063 , \blk00000001/sig00000063 }),
+    .D({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , 
+\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 }),
+    .PCOUT({\NLW_blk00000001/blk00000004_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<46>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<44>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<42>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<40>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<38>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<36>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<32>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<30>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<26>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<24>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<20>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<18>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<14>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<12>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<8>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<6>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<2>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_PCOUT<0>_UNCONNECTED }),
+    .A({\blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , \blk00000001/sig00000064 , b[31], b[30], b[29], b[28], b[27]
+, b[26], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}),
+    .M({\NLW_blk00000001/blk00000004_M<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<34>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<31>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<28>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<25>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<22>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<19>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<16>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<14>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<13>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<12>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<10>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<8>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<7>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<6>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<4>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<2>_UNCONNECTED , \NLW_blk00000001/blk00000004_M<1>_UNCONNECTED , 
+\NLW_blk00000001/blk00000004_M<0>_UNCONNECTED })
+  );
+  GND   \blk00000001/blk00000003  (
+    .G(\blk00000001/sig00000064 )
+  );
+  VCC   \blk00000001/blk00000002  (
+    .P(\blk00000001/sig00000063 )
+  );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/src/rtl/ipcore/subtractor_s6.veo b/src/rtl/ipcore/subtractor_s6.veo
new file mode 100644
index 0000000..e78cc7a
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.veo
@@ -0,0 +1,71 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2015 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+
+/*******************************************************************************
+*     Generated from core with identifier: xilinx.com:ip:c_addsub:11.0         *
+*                                                                              *
+*     The Xilinx LogiCORE Adder Subtracter can create adders, subtracters,     *
+*     and adders/subtracters that operate on signed or unsigned data. In       *
+*     fabric, the module supports inputs ranging from 1 to 256 bits wide,      *
+*     and outputs ranging from 1 to 258 bits wide.  I/O widths are family      *
+*     dependent for dsp48 implementations.                                     *
+*******************************************************************************/
+
+// Interfaces:
+//    a_intf
+//    clk_intf
+//    sclr_intf
+//    ce_intf
+//    b_intf
+//    add_intf
+//    c_in_intf
+//    bypass_intf
+//    sset_intf
+//    sinit_intf
+//    c_out_intf
+//    s_intf
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+subtractor_s6 your_instance_name (
+  .a(a), // input [31 : 0] a
+  .b(b), // input [31 : 0] b
+  .c_in(c_in), // input c_in
+  .c_out(c_out), // output c_out
+  .s(s) // output [31 : 0] s
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file subtractor_s6.v when simulating
+// the core, subtractor_s6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/src/rtl/ipcore/subtractor_s6.xco b/src/rtl/ipcore/subtractor_s6.xco
new file mode 100644
index 0000000..3c4f664
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Fri Jul 10 14:50:21 2015
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Unsigned
+CSET a_width=32
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Unsigned
+CSET b_value=00000000000000000000000000000000
+CSET b_width=32
+CSET borrow_sense=Active_High
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=true
+CSET c_out=true
+CSET ce=false
+CSET component_name=subtractor_s6
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=32
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2013-07-22T10:35:41Z
+# END Extra information
+GENERATE
+# CRC: aaca9d7a
diff --git a/src/rtl/ipcore/subtractor_s6.xise b/src/rtl/ipcore/subtractor_s6.xise
new file mode 100644
index 0000000..9be6a8b
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6.xise
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="subtractor_s6.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="subtractor_s6.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|subtractor_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="subtractor_s6.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/subtractor_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="subtractor_s6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-07-10T17:51:04" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DE7096E1188B4223AAFDCBA79BA57B43" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt
new file mode 100644
index 0000000..9cd0739
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_readme.txt
@@ -0,0 +1,164 @@
+CHANGE LOG for Xilinx LogiCORE Adder/Subtracter v11.0
+
+Release Date:  October 2, 2013 
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK   
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+  This file contains the change log for all released versions of the Xilinx 
+  LogiCORE IP Adder/Subtracter. 
+
+  For the latest core updates, see the product page at:
+
+    http://www.xilinx.com/products/ipcenter/Adder_Subtracter.htm
+
+  For installation instructions for this release, please go to:
+
+    http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+  For system requirements:
+
+    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+
+2. DEVICE SUPPORT 
+
+  2.1. ISE
+
+    The following device families are supported by the core for this release:
+
+    All Series 7 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Virtex-4 devices
+    All Spartan-3 devices
+
+
+3. NEW FEATURE HISTORY
+
+  3.1 ISE
+ 
+  v11.0
+    Ongoing new device support.
+
+
+4. RESOLVED ISSUES 
+
+  4.1 ISE
+
+    - GUI would allow CE pin to be set when Latency was zero.
+      CE is now set false and disabled.
+     CR667406
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+  The following are known issues for this core at time of release:
+
+  5.1 ISE
+    - None
+
+  - For a comprehensive listing of Known Issues for this core, please see the IP 
+    Release Notes Guide,  
+    
+    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT & FEEDBACK 
+
+  To obtain technical support, create a WebCase at www.xilinx.com/support.
+  Questions are routed to a team with expertise using this product.
+  Please feel free to leave feedback on this IP under the "Leave Feedback"
+  menu item in Vivado/PlanAhead.
+
+  Xilinx provides technical support for use of this product when used
+  according to the guidelines described in the core documentation, and
+  cannot guarantee timing, functionality, or support of this product for
+  designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+
+Date        By            Version      Description
+================================================================================
+10/02/2013  Xilinx, Inc.  11.0         ISE 14.7 support and Production support for Series 7
+06/19/2012  Xilinx, Inc.  11.0         ISE 14.6 support
+03/20/2012  Xilinx, Inc.  11.0         ISE 14.5 support. 
+10/16/2012  Xilinx, Inc.  11.0         ISE 14.3 and Vivado 2012.3 support
+07/25/2012  Xilinx, Inc.  11.0         ISE 14.2 and Vivado 2012.2 support
+04/24/2012  Xilinx, Inc.  11.0         ISE 14.1 and Vivado 2012.1 support
+01/11/2012  Xilinx, Inc.  11.0         ISE 13.4 support
+10/19/2011  Xilinx, Inc.  11.0         ISE 13.3 support
+06/22/2011  Xilinx, Inc.  11.0         ISE 13.2 support, Artix-7 support
+03/01/2011  Xilinx, Inc   11.0         ISE 13.1 support
+04/19/2010  Xilinx, Inc.  11.0         ISE 12.1 support, Virtex-6Q and Spartan-6Q support
+12/02/2009  Xilinx, Inc.  11.0         ISE 11.4 support, Spartan-6l and Automotive Spartan6 support
+09/16/2009  Xilinx, Inc.  11.0         ISE 11.3 support, Virtex-6l support
+04/24/2009  Xilinx, Inc.  11.0         ISE 11.1 support
+09/19/2008  Xilinx, Inc.  10.0         ISE 10.1.3 support
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+  (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+  
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+  
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same.
+  
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical
+  Applications"). Customer assumes the sole risk and
+  liability of any use of Xilinx products in Critical
+  Applications, subject only to applicable laws and
+  regulations governing limitations on product liability.
+  
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+  
diff --git a/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html
new file mode 100644
index 0000000..a043172
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6/doc/c_addsub_v11_0_vinfo.html
@@ -0,0 +1,175 @@
+<HTML>
+<HEAD>
+<TITLE>c_addsub_v11_0_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for Xilinx LogiCORE Adder/Subtracter v11.0
+
+Release Date:  October 2, 2013 
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK   
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+  This file contains the change log for all released versions of the Xilinx 
+  LogiCORE IP Adder/Subtracter. 
+
+  For the latest core updates, see the product page at:
+
+    <A HREF="http://www.xilinx.com/products/ipcenter/Adder_Subtracter.htm">www.xilinx.com/products/ipcenter/Adder_Subtracter.htm</A>
+
+  For installation instructions for this release, please go to:
+
+    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+  For system requirements:
+
+    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+
+2. DEVICE SUPPORT 
+
+  2.1. ISE
+
+    The following device families are supported by the core for this release:
+
+    All Series 7 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Virtex-4 devices
+    All Spartan-3 devices
+
+
+3. NEW FEATURE HISTORY
+
+  3.1 ISE
+ 
+  v11.0
+    Ongoing new device support.
+
+
+4. RESOLVED ISSUES 
+
+  4.1 ISE
+
+    - GUI would allow CE pin to be set when Latency was zero.
+      CE is now set false and disabled.
+     CR667406
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+  The following are known issues for this core at time of release:
+
+  5.1 ISE
+    - None
+
+  - For a comprehensive listing of Known Issues for this core, please see the IP 
+    Release Notes Guide,  
+    
+    <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+
+6. TECHNICAL SUPPORT & FEEDBACK 
+
+  To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+  Questions are routed to a team with expertise using this product.
+  Please feel free to leave feedback on this IP under the "Leave Feedback"
+  menu item in Vivado/PlanAhead.
+
+  Xilinx provides technical support for use of this product when used
+  according to the guidelines described in the core documentation, and
+  cannot guarantee timing, functionality, or support of this product for
+  designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+
+Date        By            Version      Description
+================================================================================
+10/02/2013  Xilinx, Inc.  11.0         ISE 14.7 support and Production support for Series 7
+06/19/2012  Xilinx, Inc.  11.0         ISE 14.6 support
+03/20/2012  Xilinx, Inc.  11.0         ISE 14.5 support. 
+10/16/2012  Xilinx, Inc.  11.0         ISE 14.3 and Vivado 2012.3 support
+07/25/2012  Xilinx, Inc.  11.0         ISE 14.2 and Vivado 2012.2 support
+04/24/2012  Xilinx, Inc.  11.0         ISE 14.1 and Vivado 2012.1 support
+01/11/2012  Xilinx, Inc.  11.0         ISE 13.4 support
+10/19/2011  Xilinx, Inc.  11.0         ISE 13.3 support
+06/22/2011  Xilinx, Inc.  11.0         ISE 13.2 support, Artix-7 support
+03/01/2011  Xilinx, Inc   11.0         ISE 13.1 support
+04/19/2010  Xilinx, Inc.  11.0         ISE 12.1 support, Virtex-6Q and Spartan-6Q support
+12/02/2009  Xilinx, Inc.  11.0         ISE 11.4 support, Spartan-6l and Automotive Spartan6 support
+09/16/2009  Xilinx, Inc.  11.0         ISE 11.3 support, Virtex-6l support
+04/24/2009  Xilinx, Inc.  11.0         ISE 11.1 support
+09/19/2008  Xilinx, Inc.  10.0         ISE 10.1.3 support
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+  (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+  
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+  
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same.
+  
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical
+  Applications"). Customer assumes the sole risk and
+  liability of any use of Xilinx products in Critical
+  Applications, subject only to applicable laws and
+  regulations governing limitations on product liability.
+  
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+  
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf b/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf
new file mode 100644
index 0000000..6030595
Binary files /dev/null and b/src/rtl/ipcore/subtractor_s6/doc/ds214_addsub.pdf differ
diff --git a/src/rtl/ipcore/subtractor_s6_flist.txt b/src/rtl/ipcore/subtractor_s6_flist.txt
new file mode 100644
index 0000000..63b0075
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6_flist.txt
@@ -0,0 +1,14 @@
+# Output products list for <subtractor_s6>
+subtractor_s6.asy
+subtractor_s6.gise
+subtractor_s6.ngc
+subtractor_s6.sym
+subtractor_s6.v
+subtractor_s6.veo
+subtractor_s6.xco
+subtractor_s6.xise
+subtractor_s6\doc\c_addsub_v11_0_readme.txt
+subtractor_s6\doc\c_addsub_v11_0_vinfo.html
+subtractor_s6\doc\ds214_addsub.pdf
+subtractor_s6_flist.txt
+subtractor_s6_xmdf.tcl
diff --git a/src/rtl/ipcore/subtractor_s6_xmdf.tcl b/src/rtl/ipcore/subtractor_s6_xmdf.tcl
new file mode 100644
index 0000000..e081cd7
--- /dev/null
+++ b/src/rtl/ipcore/subtractor_s6_xmdf.tcl
@@ -0,0 +1,83 @@
+# The package naming convention is <core_name>_xmdf
+package provide subtractor_s6_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::subtractor_s6_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::subtractor_s6_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name subtractor_s6
+}
+# ::subtractor_s6_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::subtractor_s6_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/c_addsub_v11_0_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/c_addsub_v11_0_vinfo.html
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6/doc/ds214_addsub.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path subtractor_s6_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module subtractor_s6
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs
new file mode 100644
index 0000000..00fafd8
--- /dev/null
+++ b/src/rtl/ipcore/tmp/_xmsgs/netgen.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation. 
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..b73af21
--- /dev/null
+++ b/src/rtl/ipcore/tmp/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/FPGA/ModExpS6_Novena/src/modexps6/ipcore/tmp/_cg/multiplier_s6.v" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs b/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..8f5c63c
--- /dev/null
+++ b/src/rtl/ipcore/tmp/_xmsgs/xst.xmsgs
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1836: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1842: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1848: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1849: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1850: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1851: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\xbip_utils_v2_0\bip_utils_pkg_v2_0.vhd" Line 1852: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="746" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\mult_gen_pkg_v11_2.vhd" Line 2242: Range is empty (null range)
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="871" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3441: Using initial value <arg fmt="%s" index="1">'0'</arg> for <arg fmt="%s" index="2">ce_opmode</arg> since it is never assigned
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 260: Net <<arg fmt="%s" index="1">c[0][1][47]</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 264: Net <<arg fmt="%s" index="1">d[0][0][17]</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3436: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cec</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3437: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].ced</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3438: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cem</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3439: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cep</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3440: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].ce_carryin</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3443: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].cin_dsp48a</arg>> does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\mult_gen_v11_2\dsp.vhd" Line 3435: Net <<arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[0].ceb</arg>> does not have a driver.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\multiplier_s6.vhd</arg>" line <arg fmt="%s" index="2">110</arg>: Output port <<arg fmt="%s" index="3">zero_detect</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">E:\FPGA\ModExpS6_Novena\src\modexps6\ipcore\tmp\_cg\_dbg\multiplier_s6.vhd</arg>" line <arg fmt="%s" index="2">110</arg>: Output port <<arg fmt="%s" index="3">pcasc</arg>> of the instance <<arg fmt="%s" index="4">U0</arg>> is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[0].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+
+<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[0].bppDSP48A[1].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+
+<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[0].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+
+<msg type="info" file="Xst" num="1901" delta="new" >Instance <arg fmt="%s" index="1">use_DSP48a.appDSP48A[1].bppDSP48A[1].iDSP48A</arg> in unit <arg fmt="%s" index="2">dsp</arg> of type <arg fmt="%s" index="3">DSP48A</arg> has been replaced by <arg fmt="%s" index="4">DSP48A1</arg>
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
diff --git a/src/rtl/ipcore/tmp/multiplier_s6.lso b/src/rtl/ipcore/tmp/multiplier_s6.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/src/rtl/ipcore/tmp/multiplier_s6.lso
@@ -0,0 +1 @@
+work
diff --git a/src/rtl/ipcore/tmp/subtractor_s6.lso b/src/rtl/ipcore/tmp/subtractor_s6.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/src/rtl/ipcore/tmp/subtractor_s6.lso
@@ -0,0 +1 @@
+work
diff --git a/src/rtl/modexps6_adder64_carry32.v b/src/rtl/modexps6_adder64_carry32.v
new file mode 100644
index 0000000..87869d1
--- /dev/null
+++ b/src/rtl/modexps6_adder64_carry32.v
@@ -0,0 +1,70 @@
+`timescale 1ns / 1ps
+
+module modexps6_adder64_carry32
+	(
+		clk, t, x, y, s, c_in, c_out
+	);
+	
+	
+		//
+		// Ports
+		//
+	input		wire				clk;
+	input		wire	[31: 0]	t;
+	input		wire	[31: 0]	x;
+	input		wire	[31: 0]	y;
+	output	wire	[31: 0]	s;
+	input		wire	[31: 0]	c_in;
+	output	wire	[31: 0]	c_out;
+	
+	
+		//
+		// Multiplier
+		//
+	wire	[63: 0]	multiplier_out;
+	
+	multiplier_s6 dsp_multiplier
+	(
+		.clk	(clk),
+		.a		(x),
+		.b		(y),
+		.p		(multiplier_out)
+	);
+	
+	
+		//
+		// Carry and T
+		//
+	wire	[63: 0]	t_ext = {{32{1'b0}}, t};
+	wire	[63: 0]	c_ext = {{32{1'b0}}, c_in};
+	
+	
+		//
+		// Sum
+		//
+	wire	[63: 0]	sum = multiplier_out + c_in + t;
+		
+		
+		//
+		// Output
+		//
+	assign s = sum[31: 0];
+	assign c_out = sum[63:32];
+		
+	/*
+	reg	[31: 0]	s_reg;
+	reg	[31: 0]	c_out_reg;
+	
+	assign s = s_reg;
+	assign c_out = c_out_reg;
+	
+	always @(posedge clk) begin
+		//
+		s_reg			<= sum[31: 0];
+		c_out_reg	<= sum[63:32];
+		//
+	end
+	*/
+	
+	
+endmodule
diff --git a/src/rtl/modexps6_buffer_core.v b/src/rtl/modexps6_buffer_core.v
new file mode 100644
index 0000000..86a6a4d
--- /dev/null
+++ b/src/rtl/modexps6_buffer_core.v
@@ -0,0 +1,202 @@
+`timescale 1ns / 1ps
+
+module modexps6_buffer_core
+	(
+		clk,
+		rw_coeff_bram_addr, rw_coeff_bram_wr, rw_coeff_bram_in, rw_coeff_bram_out, ro_coeff_bram_addr, ro_coeff_bram_out,
+		rw_mm_bram_addr,    rw_mm_bram_wr,    rw_mm_bram_in,    rw_mm_bram_out,    ro_mm_bram_addr,    ro_mm_bram_out,
+		rw_nn_bram_addr,    rw_nn_bram_wr,    rw_nn_bram_in,                       ro_nn_bram_addr,    ro_nn_bram_out,
+		rw_y_bram_addr,     rw_y_bram_wr,     rw_y_bram_in,     rw_y_bram_out,
+		rw_r_bram_addr,     rw_r_bram_wr,     rw_r_bram_in,     rw_r_bram_out,     ro_r_bram_addr,     ro_r_bram_out,
+		rw_t_bram_addr,     rw_t_bram_wr,     rw_t_bram_in,     rw_t_bram_out,     ro_t_bram_addr,     ro_t_bram_out
+	);
+
+		//
+		// Parameters
+		//
+	parameter OPERAND_ADDR_WIDTH	=  5;		// 1024 / 32 = 32 -> 5 bits
+	
+	
+		//
+		// Ports
+		//
+	input		wire									clk;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_coeff_bram_addr;
+	input		wire									rw_coeff_bram_wr;
+	input		wire	[                31:0]	rw_coeff_bram_in;
+	output	wire	[                31:0]	rw_coeff_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_mm_bram_addr;
+	input		wire									rw_mm_bram_wr;
+	input		wire	[                31:0]	rw_mm_bram_in;
+	output	wire	[                31:0]	rw_mm_bram_out;	
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_nn_bram_addr;
+	input		wire									rw_nn_bram_wr;
+	input		wire	[                31:0]	rw_nn_bram_in;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_y_bram_addr;
+	input		wire									rw_y_bram_wr;
+	input		wire	[                31:0]	rw_y_bram_in;
+	output	wire	[                31:0]	rw_y_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_r_bram_addr;
+	input		wire									rw_r_bram_wr;
+	input		wire	[                31:0]	rw_r_bram_in;
+	output	wire	[                31:0]	rw_r_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	rw_t_bram_addr;
+	input		wire									rw_t_bram_wr;
+	input		wire	[                31:0]	rw_t_bram_in;
+	output	wire	[                31:0]	rw_t_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	ro_coeff_bram_addr;
+	output	wire	[                31:0]	ro_coeff_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	ro_mm_bram_addr;
+	output	wire	[                31:0]	ro_mm_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	ro_nn_bram_addr;
+	output	wire	[                31:0]	ro_nn_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	ro_r_bram_addr;
+	output	wire	[                31:0]	ro_r_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH:0]	ro_t_bram_addr;
+	output	wire	[                31:0]	ro_t_bram_out;
+	
+	
+		//
+		// Montgomery Coefficient
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_coeff
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_coeff_bram_addr),
+		.a_wr		(rw_coeff_bram_wr),
+		.a_in		(rw_coeff_bram_in),
+		.a_out	(rw_coeff_bram_out),
+		
+		.b_addr	(ro_coeff_bram_addr),
+		.b_out	(ro_coeff_bram_out)
+	);
+	
+	
+		//
+		// Powers of Message
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_mm
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_mm_bram_addr),
+		.a_wr		(rw_mm_bram_wr),
+		.a_in		(rw_mm_bram_in),
+		.a_out	(rw_mm_bram_out),
+		
+		.b_addr	(ro_mm_bram_addr),
+		.b_out	(ro_mm_bram_out)
+	);
+	
+	
+		//
+		// Extended Modulus
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_nn
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_nn_bram_addr),
+		.a_wr		(rw_nn_bram_wr),
+		.a_in		(rw_nn_bram_in),
+		.a_out	(),
+		
+		.b_addr	(ro_nn_bram_addr),
+		.b_out	(ro_nn_bram_out)
+	);
+	
+	
+		//
+		// Output
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_y
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_y_bram_addr),
+		.a_wr		(rw_y_bram_wr),
+		.a_in		(rw_y_bram_in),
+		.a_out	(rw_y_bram_out),
+		
+		.b_addr	({(OPERAND_ADDR_WIDTH+1){1'b0}}),
+		.b_out	()
+	);
+		
+		
+		//
+		// Result of Multiplication
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_r
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_r_bram_addr),
+		.a_wr		(rw_r_bram_wr),
+		.a_in		(rw_r_bram_in),
+		.a_out	(rw_r_bram_out),
+		
+		.b_addr	(ro_r_bram_addr),
+		.b_out	(ro_r_bram_out)
+	);
+	
+	
+		//
+		// Temporary Buffer
+		//
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH+1)
+	)
+	mem_t
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_t_bram_addr),
+		.a_wr		(rw_t_bram_wr),
+		.a_in		(rw_t_bram_in),
+		.a_out	(rw_t_bram_out),
+		
+		.b_addr	(ro_t_bram_addr),
+		.b_out	(ro_t_bram_out)
+	);
+	
+	
+endmodule
diff --git a/src/rtl/modexps6_buffer_user.v b/src/rtl/modexps6_buffer_user.v
new file mode 100644
index 0000000..6072fc9
--- /dev/null
+++ b/src/rtl/modexps6_buffer_user.v
@@ -0,0 +1,185 @@
+`timescale 1ns / 1ps
+
+module modexps6_buffer_user
+	(
+		clk,
+		
+		bus_cs, bus_we,
+		bus_addr, bus_data_wr, bus_data_rd,
+		
+		ro_modulus_bram_addr,  ro_modulus_bram_out,
+		ro_message_bram_addr,  ro_message_bram_out,
+		ro_exponent_bram_addr, ro_exponent_bram_out,
+		rw_result_bram_addr,
+		rw_result_bram_wr,     rw_result_bram_in
+	);
+	
+	
+		//
+		// Parameters
+		//
+	parameter OPERAND_ADDR_WIDTH	=  5;		// 1024 / 32 = 32 -> 5 bits
+	
+	
+		//
+		// Locals
+		//
+	localparam	ADDR_WIDTH_TOTAL	= OPERAND_ADDR_WIDTH + 2;
+	
+	localparam	[ 1: 0]	BUS_ADDR_BANK_MODULUS	= 2'b00;
+	localparam	[ 1: 0]	BUS_ADDR_BANK_MESSAGE	= 2'b01;
+	localparam	[ 1: 0]	BUS_ADDR_BANK_EXPONENT	= 2'b10;
+	localparam	[ 1: 0]	BUS_ADDR_BANK_RESULT		= 2'b11;
+	
+		//
+		// Ports
+		//
+	input		wire										clk;
+		
+	input		wire										bus_cs;
+	input		wire										bus_we;
+	input		wire	[  ADDR_WIDTH_TOTAL-1:0]	bus_addr;
+	input		wire	[                  31:0]	bus_data_wr;
+	output	wire	[                  31:0]	bus_data_rd;
+		
+	input		wire	[OPERAND_ADDR_WIDTH-1:0]	ro_modulus_bram_addr;
+	output	wire	[                  31:0]	ro_modulus_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH-1:0]	ro_message_bram_addr;
+	output	wire	[                  31:0]	ro_message_bram_out;
+		
+	input		wire	[OPERAND_ADDR_WIDTH-1:0]	ro_exponent_bram_addr;
+	output	wire	[                  31:0]	ro_exponent_bram_out;
+	
+	input		wire	[OPERAND_ADDR_WIDTH-1:0]	rw_result_bram_addr;
+	input		wire										rw_result_bram_wr;
+	input		wire	[                  31:0]	rw_result_bram_in;
+		
+		
+		//
+		// Address Decoder
+		//
+	wire	[OPERAND_ADDR_WIDTH-1:0]	bus_addr_operand_word = bus_addr[OPERAND_ADDR_WIDTH-1:0];
+	wire	[                   1:0]	bus_addr_operand_bank = bus_addr[ADDR_WIDTH_TOTAL-1:ADDR_WIDTH_TOTAL-2];
+	
+
+		//
+		// Modulus Memory
+		//
+	wire	[31: 0]	bus_data_rd_modulus;
+	
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH)
+	)
+	mem_modulus
+	(
+		.clk		(clk),
+		
+		.a_addr	(bus_addr_operand_word),
+		.a_wr		(bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_MODULUS)),
+		.a_in		(bus_data_wr),
+		.a_out	(bus_data_rd_modulus),
+		
+		.b_addr	(ro_modulus_bram_addr),
+		.b_out	(ro_modulus_bram_out)
+	);
+	
+	
+		//
+		// Message Memory
+		//
+	wire	[31: 0]	bus_data_rd_message;
+	
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH)
+	)
+	mem_message
+	(
+		.clk		(clk),
+		
+		.a_addr	(bus_addr_operand_word),
+		.a_wr		(bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_MESSAGE)),
+		.a_in		(bus_data_wr),
+		.a_out	(bus_data_rd_message),
+		
+		.b_addr	(ro_message_bram_addr),
+		.b_out	(ro_message_bram_out)
+	);
+	
+	
+		//
+		// Exponent Memory
+		//
+	wire	[31: 0]	bus_data_rd_exponent;
+	
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH)
+	)
+	mem_exponent
+	(
+		.clk		(clk),
+		
+		.a_addr	(bus_addr_operand_word),
+		.a_wr		(bus_cs & bus_we & (bus_addr_operand_bank == BUS_ADDR_BANK_EXPONENT)),
+		.a_in		(bus_data_wr),
+		.a_out	(bus_data_rd_exponent),
+		
+		.b_addr	(ro_exponent_bram_addr),
+		.b_out	(ro_exponent_bram_out)
+	);
+	
+	
+		//
+		// Result Memory
+		//
+	wire	[31: 0]	bus_data_rd_result;
+	
+	ram_1rw_1ro_readfirst #
+	(
+		.MEM_WIDTH		(32),
+		.MEM_ADDR_BITS	(OPERAND_ADDR_WIDTH)
+	)
+	mem_result
+	(
+		.clk		(clk),
+		
+		.a_addr	(rw_result_bram_addr),
+		.a_wr		(rw_result_bram_wr),
+		.a_in		(rw_result_bram_in),
+		.a_out	(),
+		
+		.b_addr	(bus_addr_operand_word),
+		.b_out	(bus_data_rd_result)
+	);
+	
+	
+		//
+		// Output Selector
+		//
+	reg	[ 1: 0]	bus_addr_operand_bank_prev;
+	always @(posedge clk) bus_addr_operand_bank_prev = bus_addr_operand_bank;
+	
+	reg	[31: 0]	bus_data_rd_mux;
+	assign bus_data_rd = bus_data_rd_mux;	
+	
+	always @(*)
+		//
+		case (bus_addr_operand_bank_prev)
+			//
+			BUS_ADDR_BANK_MODULUS:		bus_data_rd_mux = bus_data_rd_modulus;
+			BUS_ADDR_BANK_MESSAGE:		bus_data_rd_mux = bus_data_rd_message;
+			BUS_ADDR_BANK_EXPONENT:		bus_data_rd_mux = bus_data_rd_exponent;
+			BUS_ADDR_BANK_RESULT:		bus_data_rd_mux = bus_data_rd_result;
+			//
+			default:							bus_data_rd_mux = {32{1'bX}};
+			//
+		endcase
+
+	
+endmodule
diff --git a/src/rtl/modexps6_modinv32.v b/src/rtl/modexps6_modinv32.v
new file mode 100644
index 0000000..dc08b7b
--- /dev/null
+++ b/src/rtl/modexps6_modinv32.v
@@ -0,0 +1,116 @@
+`timescale 1ns / 1ps
+
+module modexps6_modinv32
+	(
+		clk,
+		ena, rdy,
+		n0, n0_modinv
+	);
+	
+	
+		//
+		// Ports
+		//
+	input		wire				clk;
+	
+	input		wire				ena;
+	output	wire				rdy;
+	
+	input		wire	[31: 0]	n0;
+	output	wire	[31: 0]	n0_modinv;	
+
+
+		//
+		// Trigger
+		//
+	reg ena_dly = 1'b0;
+	wire ena_trig = ena && !ena_dly;
+	always @(posedge clk) ena_dly <= ena;
+
+
+		//
+		// Ready Register
+		//
+	reg rdy_reg = 1'b0;
+	assign rdy = rdy_reg;
+	
+	
+		//
+		// Counter
+		//
+	reg	[ 7: 0]	cnt		= 8'd0;
+	wire	[ 7: 0]	cnt_zero = 8'd0;
+	wire	[ 7: 0]	cnt_last	= 8'd132;
+	wire	[ 7: 0]	cnt_next	= cnt + 1'b1;
+	wire	[ 1: 0]	cnt_phase = cnt[1:0];
+	wire	[ 5: 0]	cnt_cycle = cnt[7:2];
+	
+	always @(posedge clk)
+		//
+		if (cnt == cnt_zero)	cnt <= (!rdy_reg && ena_trig) ? cnt_next : cnt_zero;
+		else cnt <= (cnt == cnt_last) ? cnt_zero : cnt_next;
+		
+	
+		//
+		// Enable / Ready Logic
+		//
+	always @(posedge clk)
+		//
+		if (cnt == cnt_last) rdy_reg <= 1'b1;
+		else if ((cnt == cnt_zero) && (rdy_reg && !ena)) rdy_reg <= 1'b0;
+		
+		
+		//
+		// Output Register
+		//
+	reg	[31: 0]	n0_modinv_reg;
+	assign n0_modinv = n0_modinv_reg;
+	
+	
+		//
+		// Multiplier
+		//
+	wire	[63: 0]	multiplier_out;
+	wire	[31: 0]	multiplier_out_masked = multiplier_out[31: 0] & {mask_reg, 1'b1};
+	
+	multiplier_s6 dsp_multiplier
+	(
+		.clk	(clk),
+		.a		(n0),
+		.b		(n0_modinv_reg),
+		.p		(multiplier_out)
+	);
+	
+	
+		//
+		// Mask and Power
+		//
+	reg	[30: 0]	mask_reg;
+	reg	[31: 0]	power_reg;
+	
+	always @(posedge clk)
+		//
+		if (cnt_phase == 2'd1) begin
+			//
+			if (cnt_cycle == 6'd0) begin
+				//
+				mask_reg			<= 31'd0;
+				power_reg		<= 32'd1;
+				//
+				n0_modinv_reg	<= 32'd0;
+				//
+			end else begin
+				//
+				mask_reg			<= { mask_reg[29:0], 1'b1};
+				power_reg		<= {power_reg[30:0], 1'b0};
+				//
+				if (multiplier_out_masked != 32'd1)
+					//
+					n0_modinv_reg <= n0_modinv_reg + power_reg;
+				//
+			end
+			//
+		end
+			
+	
+endmodule
diff --git a/src/rtl/modexps6_montgomery_coeff.v b/src/rtl/modexps6_montgomery_coeff.v
new file mode 100644
index 0000000..c3ceeee
--- /dev/null
+++ b/src/rtl/modexps6_montgomery_coeff.v
@@ -0,0 +1,410 @@
+`timescale 1ns / 1ps
+
+module modexps6_montgomery_coeff
+	(
+		clk,
+		ena, rdy,
+		modulus_width,
+		coeff_bram_addr, coeff_bram_wr, coeff_bram_in, coeff_bram_out,
+		nn_bram_addr,    nn_bram_wr,    nn_bram_in,
+		modulus_bram_addr, modulus_bram_out,
+		modinv_n0, modinv_ena, modinv_rdy
+	);
+
+
+		//
+		// Parameters
+		//
+	parameter MODULUS_NUM_BITS		= 11;		// 1024 -> 11 bits
+	parameter OPERAND_ADDR_WIDTH	=  5;		// 1024 / 32 = 32 -> 5 bits
+	
+	
+		//
+		// Locals
+		//
+	localparam	[  MODULUS_NUM_BITS  :0]	round_count_zero			= {1'b0, {MODULUS_NUM_BITS{1'b0}}};
+	localparam	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr_zero		= {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+	localparam	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr_zero	= {OPERAND_ADDR_WIDTH{1'b0}};
+	
+	
+		//
+		// Ports
+		//
+	input		wire										clk;
+	
+	input		wire										ena;
+	output	wire										rdy;
+	
+	input		wire	[  MODULUS_NUM_BITS-1:0]	modulus_width;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr;
+	output	wire										coeff_bram_wr;
+	output	wire	[                  31:0]	coeff_bram_in;
+	input		wire	[                  31:0]	coeff_bram_out;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	nn_bram_addr;
+	output	wire										nn_bram_wr;
+	output	wire	[                  31:0]	nn_bram_in;
+	
+	output	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr;
+	input		wire	[                  31:0]	modulus_bram_out;
+	
+	output	wire	[                  31:0]	modinv_n0;
+	output	wire										modinv_ena;
+	input		wire										modinv_rdy;
+	
+
+		//
+		// FSM
+		//
+	localparam FSM_STATE_IDLE					= 6'd0;
+	
+	localparam FSM_STATE_INIT					= 6'd10;
+	
+	localparam FSM_STATE_SHIFT_READ			= 6'd21;
+	localparam FSM_STATE_SHIFT_WRITE			= 6'd22;
+
+	localparam FSM_STATE_COMPARE_READ		= 6'd31;
+	localparam FSM_STATE_COMPARE_COMPARE	= 6'd32;
+	
+	localparam FSM_STATE_SUBTRACT_READ		= 6'd41;
+	localparam FSM_STATE_SUBTRACT_WRITE		= 6'd42;
+	
+	localparam FSM_STATE_ROUND					= 6'd50;
+	
+	localparam FSM_STATE_FINAL					= 6'd60;
+	
+	reg	[ 5: 0]	fsm_state = FSM_STATE_IDLE;
+	
+	
+		//
+		// Trigger
+		//
+	reg ena_dly = 1'b0;
+	
+	wire ena_trig = ena && !ena_dly;
+	
+	always @(posedge clk) ena_dly <= ena;
+	
+	
+		//
+		// Ready Register
+		//
+	reg rdy_reg = 1'b0;
+	
+	assign rdy = rdy_reg;
+	
+	
+		//
+		// ModInv Control
+		//
+	reg				modinv_ena_reg = 1'b0;
+	reg	[31: 0]	modinv_n0_reg;
+	
+	assign modinv_ena = modinv_ena_reg;
+	assign modinv_n0 = modinv_n0_reg;
+	
+	
+		//
+		// Enable / Ready Logic
+		//
+	always @(posedge clk)
+		//
+		if (fsm_state == FSM_STATE_FINAL) begin
+			//
+			if (modinv_rdy) rdy_reg <= 1'b1;
+			//
+		end else if (fsm_state == FSM_STATE_IDLE) begin
+			//
+			if (rdy_reg && !ena) rdy_reg <= 1'b0;
+			//
+		end
+		
+	
+		//
+		// Flags
+		//
+	reg	reg_shift_carry = 1'b0;
+	reg	reg_subtractor_borrow = 1'b0;
+	
+	
+		//
+		// Round Counter
+		//
+	reg	[MODULUS_NUM_BITS:0]	round_count			= round_count_zero;
+	wire	[MODULUS_NUM_BITS:0]	round_count_last	= {modulus_width, 1'b0} + 6'd63;
+	wire	[MODULUS_NUM_BITS:0]	round_count_next	= (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero;
+	
+
+		//
+		// Modulus BRAM Interface
+		//
+	reg	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr_reg = modulus_bram_addr_zero;
+	
+	assign modulus_bram_addr = modulus_bram_addr_reg;	
+
+	
+		//
+		// Coeff BRAM Interface
+		//
+	reg	[OPERAND_ADDR_WIDTH:0]	coeff_bram_addr_reg	= coeff_bram_addr_zero;
+	reg									coeff_bram_wr_reg		= 1'b0;
+	
+	assign coeff_bram_addr = coeff_bram_addr_reg;
+	assign coeff_bram_wr = coeff_bram_wr_reg;
+	
+	
+		//
+		// NN BRAM Interface
+		//
+	reg	[OPERAND_ADDR_WIDTH:0]	nn_bram_addr_reg	= coeff_bram_addr_zero;
+	reg									nn_bram_wr_reg		= 1'b0;
+	
+	assign nn_bram_addr = nn_bram_addr_reg;
+	assign nn_bram_wr = nn_bram_wr_reg;	
+
+
+		//
+		// Hardware Subtractor
+		//
+	wire	[31: 0]	subtractor_out;
+	wire				subtractor_out_nonzero = |subtractor_out;
+	wire				subtractor_borrow_out;
+	wire				subtractor_borrow_in;
+	
+	assign subtractor_borrow_in = (fsm_state == FSM_STATE_COMPARE_COMPARE) ? 1'b0 : reg_subtractor_borrow;
+	
+	subtractor_s6 dsp_subtractor
+	(
+		.a			(coeff_bram_out),
+		.b			(modulus_bram_out),
+		.s			(subtractor_out),
+		.c_in		(subtractor_borrow_in),
+		.c_out	(subtractor_borrow_out)
+	);
+	
+	
+		//
+		// Handy Wires
+		//
+	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_width_msb						= modulus_width[MODULUS_NUM_BITS-1:MODULUS_NUM_BITS-OPERAND_ADDR_WIDTH];
+
+	wire	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr_last					= {modulus_width_msb, 1'b0};
+	wire	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr_next_or_zero		= (coeff_bram_addr_reg < coeff_bram_addr_last) ? coeff_bram_addr_reg + 1'b1 : coeff_bram_addr_zero;
+	wire	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr_next_or_last		= (coeff_bram_addr_reg < coeff_bram_addr_last) ? coeff_bram_addr_reg + 1'b1 : coeff_bram_addr_last;
+	wire	[OPERAND_ADDR_WIDTH  :0]	coeff_bram_addr_prev_or_zero		= (coeff_bram_addr_reg > coeff_bram_addr_zero) ? coeff_bram_addr_reg - 1'b1 : coeff_bram_addr_zero;
+	
+	wire	[OPERAND_ADDR_WIDTH  :0]	modulus_bram_addr_last_ext			= coeff_bram_addr_last - 1'b1;
+	
+	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr_last				= modulus_bram_addr_last_ext[OPERAND_ADDR_WIDTH-1:0];
+	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr_next_or_zero	= (modulus_bram_addr_reg < modulus_bram_addr_last) ? modulus_bram_addr_reg + 1'b1 : modulus_bram_addr_zero;
+	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_bram_addr_prev_or_zero	= (modulus_bram_addr_reg > modulus_bram_addr_zero) ? modulus_bram_addr_reg - 1'b1 : modulus_bram_addr_zero;
+
+	
+		//
+		// Coeff BRAM Input Logic
+		//
+	reg	[31: 0]	coeff_bram_in_mux;
+	
+	assign coeff_bram_in = coeff_bram_in_mux;
+	
+	always @(*)
+		//
+		case (fsm_state)
+
+			FSM_STATE_INIT:
+				//
+				if (coeff_bram_addr_reg == coeff_bram_addr_zero)	coeff_bram_in_mux = 32'h00000001;
+				else																coeff_bram_in_mux = 32'h00000000;
+			
+			FSM_STATE_SHIFT_WRITE:
+				//
+				coeff_bram_in_mux = {coeff_bram_out[30:0], reg_shift_carry};
+			
+			FSM_STATE_SUBTRACT_WRITE:
+				//
+				if (coeff_bram_addr_reg == coeff_bram_addr_last)	coeff_bram_in_mux = 32'h00000000;
+				else																coeff_bram_in_mux = subtractor_out;
+			
+			default:
+				//
+				coeff_bram_in_mux	= {32{1'bX}};
+
+		endcase
+		
+		
+		//
+		// NN BRAM Input Logic
+		//
+	reg	[31: 0]	nn_bram_in_mux;
+	
+	assign nn_bram_in = nn_bram_in_mux;
+	
+	always @(*)
+		//
+		case (fsm_state)
+
+			FSM_STATE_INIT:
+				//
+				if (coeff_bram_addr_reg == coeff_bram_addr_last)	nn_bram_in_mux = {32{1'b0}};
+				else																nn_bram_in_mux = modulus_bram_out;
+
+			default:
+				//
+				nn_bram_in_mux	= {32{1'bX}};
+
+		endcase		
+
+
+		//
+		// Comparison Functions
+		//
+	reg	compare_greater_or_equal;
+	reg	compare_less_than;
+
+	wire compare_done = compare_greater_or_equal | compare_less_than;
+
+	always @(*)
+		//
+		if (coeff_bram_addr_reg == coeff_bram_addr_last)			compare_greater_or_equal = coeff_bram_out[0];
+		//
+		else if (coeff_bram_addr_reg == coeff_bram_addr_zero)		compare_greater_or_equal = !subtractor_borrow_out;
+		//
+		else																		compare_greater_or_equal = !subtractor_borrow_out && subtractor_out_nonzero;		
+	
+	always @(*)
+		//
+		if (coeff_bram_addr_reg == coeff_bram_addr_last)			compare_less_than = 1'b0;
+		//
+		else																		compare_less_than = subtractor_borrow_out;
+
+	
+	
+		//
+		// Main Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+			
+			FSM_STATE_INIT: begin
+				//
+				coeff_bram_wr_reg		<= (coeff_bram_addr_reg < coeff_bram_addr_last) ? 1'b1 : 1'b0;
+				coeff_bram_addr_reg	<= coeff_bram_wr_reg ? coeff_bram_addr_next_or_zero : coeff_bram_addr_zero;
+				//
+				nn_bram_wr_reg			<= (coeff_bram_addr_reg < coeff_bram_addr_last) ? 1'b1 : 1'b0;
+				nn_bram_addr_reg		<= coeff_bram_wr_reg ? coeff_bram_addr_next_or_zero : coeff_bram_addr_zero;
+				//
+				if (!coeff_bram_wr_reg) begin
+					//
+					modinv_ena_reg		<= 1'b1;
+					modinv_n0_reg		<= modulus_bram_out;
+					//
+				end
+				//
+				if (modulus_bram_addr_reg == modulus_bram_addr_zero) begin
+					//
+					if (!coeff_bram_wr_reg)
+						//
+						modulus_bram_addr_reg	<= modulus_bram_addr_next_or_zero;
+					//
+				end else begin
+					//
+					modulus_bram_addr_reg	<= modulus_bram_addr_next_or_zero;
+					//
+				end
+				//
+			end
+			
+			FSM_STATE_SHIFT_READ: begin
+				//
+				coeff_bram_wr_reg <= 1'b1;
+				//
+				if (coeff_bram_addr_reg == coeff_bram_addr_zero)
+					//
+					reg_shift_carry <= 1'b0;
+				//
+			end
+			
+			FSM_STATE_SHIFT_WRITE: begin
+				//
+				coeff_bram_wr_reg			<= 1'b0;
+				coeff_bram_addr_reg		<= coeff_bram_addr_next_or_last;
+				//
+				reg_shift_carry			<= coeff_bram_out[31];
+				//
+			end
+			
+			FSM_STATE_COMPARE_COMPARE: begin
+				//
+				coeff_bram_addr_reg		<= compare_done ? coeff_bram_addr_zero : coeff_bram_addr_prev_or_zero;
+				//
+				modulus_bram_addr_reg	<= compare_done ? modulus_bram_addr_zero : ((coeff_bram_addr_reg == coeff_bram_addr_last) ? modulus_bram_addr_last : modulus_bram_addr_prev_or_zero);
+				//
+			end
+			
+			FSM_STATE_SUBTRACT_READ: begin
+				//
+				coeff_bram_wr_reg <= 1'b1;
+				//
+				if (coeff_bram_addr_reg == coeff_bram_addr_zero)
+					//
+					reg_subtractor_borrow <= 1'b0;
+				//
+			end
+			
+			FSM_STATE_SUBTRACT_WRITE: begin
+				//
+				coeff_bram_wr_reg			<= 1'b0;
+				coeff_bram_addr_reg		<= coeff_bram_addr_next_or_zero;
+				//
+				modulus_bram_addr_reg	<= (coeff_bram_addr_reg == coeff_bram_addr_last) ? modulus_bram_addr_zero : modulus_bram_addr_next_or_zero;
+				//
+				reg_subtractor_borrow	<= subtractor_borrow_out;
+				//
+			end			
+			
+			FSM_STATE_ROUND: begin
+				//
+				round_count <= round_count_next;
+				//
+			end
+			
+			FSM_STATE_FINAL: begin
+				//
+				if (modinv_rdy) modinv_ena_reg <= 1'b0;
+				//
+			end
+			
+		endcase
+		
+		
+		//
+		// FSM Transition Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+			
+			FSM_STATE_IDLE:					fsm_state <= (!rdy_reg && !modinv_rdy && ena_trig) ? FSM_STATE_INIT : FSM_STATE_IDLE;
+			
+			FSM_STATE_SHIFT_READ:			fsm_state <= FSM_STATE_SHIFT_WRITE;
+			FSM_STATE_COMPARE_READ:			fsm_state <= FSM_STATE_COMPARE_COMPARE;
+			FSM_STATE_SUBTRACT_READ:		fsm_state <= FSM_STATE_SUBTRACT_WRITE;
+
+			FSM_STATE_INIT:					fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_INIT          : FSM_STATE_SHIFT_READ;
+			FSM_STATE_SHIFT_WRITE:			fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_SHIFT_READ    : FSM_STATE_COMPARE_READ;
+			FSM_STATE_SUBTRACT_WRITE:		fsm_state <= (coeff_bram_addr_reg < coeff_bram_addr_last) ? FSM_STATE_SUBTRACT_READ : FSM_STATE_ROUND;
+			
+			FSM_STATE_ROUND:					fsm_state <= (round_count < round_count_last) ? FSM_STATE_SHIFT_READ : FSM_STATE_FINAL;
+			
+			FSM_STATE_COMPARE_COMPARE:		fsm_state <= compare_done ? (compare_greater_or_equal ? FSM_STATE_SUBTRACT_READ : FSM_STATE_ROUND) : FSM_STATE_COMPARE_READ;
+
+			FSM_STATE_FINAL:					fsm_state <= modinv_rdy ? FSM_STATE_IDLE : FSM_STATE_FINAL;
+			
+			default:								fsm_state <= FSM_STATE_IDLE;
+			
+		endcase
+		
+	
+endmodule
diff --git a/src/rtl/modexps6_montgomery_multiplier.v b/src/rtl/modexps6_montgomery_multiplier.v
new file mode 100644
index 0000000..f22f93d
--- /dev/null
+++ b/src/rtl/modexps6_montgomery_multiplier.v
@@ -0,0 +1,392 @@
+`timescale 1ns / 1ps
+
+module modexps6_montgomery_multiplier
+	(
+		clk,
+		ena, rdy,
+		operand_width,
+		x_bram_addr, x_bram_out,
+		y_bram_addr, y_bram_out,
+		n_bram_addr, n_bram_out,
+		z_bram_addr, z_bram_wr, z_bram_in, z_bram_out,
+		n0_modinv
+	);
+	
+		//
+		// Parameters
+		//
+	parameter OPERAND_NUM_BITS		= 11;		// 1024 -> 11 bits
+	parameter OPERAND_ADDR_WIDTH	=  5;		// 1024 / 32 = 32 -> 5 bits		
+	
+	
+		//
+		// Locals
+		//
+	localparam	[OPERAND_ADDR_WIDTH:0]	round_count_zero	= {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+	localparam	[OPERAND_ADDR_WIDTH:0]	bram_addr_zero		= {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};	
+	
+	
+		//
+		// Ports
+		//
+	input		wire										clk;
+	
+	input		wire										ena;
+	output	wire										rdy;
+	
+	input		wire	[  OPERAND_NUM_BITS-1:0]	operand_width;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	x_bram_addr;
+	input		wire	[                  31:0]	x_bram_out;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	y_bram_addr;
+	input		wire	[                  31:0]	y_bram_out;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	n_bram_addr;
+	input		wire	[                  31:0]	n_bram_out;
+	
+	output	wire	[OPERAND_ADDR_WIDTH  :0]	z_bram_addr;
+	output	wire										z_bram_wr;
+	output	wire	[                  31:0]	z_bram_in;
+	input		wire	[                  31:0]	z_bram_out;
+	
+	input		wire	[                  31:0]	n0_modinv;
+	
+	
+		//
+		// FSM
+		//
+	localparam FSM_STATE_IDLE					= 6'd0;
+	
+	localparam FSM_STATE_INIT					= 6'd10;
+	
+	localparam FSM_STATE_MUL_XY_CALC			= 6'd21;
+	localparam FSM_STATE_MUL_XY_PIPELINE	= 6'd22;
+	localparam FSM_STATE_MUL_XY_REGISTER	= 6'd23;
+	localparam FSM_STATE_MUL_XY_WRITE		= 6'd24;
+	
+	localparam FSM_STATE_MAGIC_CALC			= 6'd31;
+	localparam FSM_STATE_MAGIC_PIPELINE		= 6'd32;
+	localparam FSM_STATE_MAGIC_REGISTER		= 6'd33;
+	
+	localparam FSM_STATE_MUL_MN_CALC			= 6'd41;
+	localparam FSM_STATE_MUL_MN_PIPELINE	= 6'd42;
+	localparam FSM_STATE_MUL_MN_REGISTER	= 6'd43;
+	localparam FSM_STATE_MUL_MN_WRITE		= 6'd44;
+	
+	localparam FSM_STATE_SHIFT					= 6'd50;
+	
+	localparam FSM_STATE_ROUND					= 6'd55;
+	
+	localparam FSM_STATE_FINAL					= 6'd60;
+	
+	reg	[ 5: 0]	fsm_state = FSM_STATE_IDLE;
+	
+	
+		//
+		// Trigger
+		//
+	reg ena_dly = 1'b0;
+	always @(posedge clk) ena_dly <= ena;
+	wire ena_trig = (ena == 1'b1) && (ena_dly == 1'b0);
+
+	
+		//
+		// Ready Register
+		//
+	reg rdy_reg = 1'b0;
+	assign rdy = rdy_reg;
+	
+	
+		//
+		// Enable / Ready Logic
+		//
+	always @(posedge clk)
+		//
+		if (fsm_state == FSM_STATE_FINAL) begin
+			//
+			rdy_reg <= 1'b1;
+			//
+		end else if (fsm_state == FSM_STATE_IDLE) begin
+			//
+			if (rdy_reg && !ena) rdy_reg <= 1'b0;
+			//
+		end
+		
+		
+		//
+		// X, Y, N BRAM Interface
+		//
+	reg	[OPERAND_ADDR_WIDTH:0]	x_bram_addr_reg = bram_addr_zero;
+	reg	[OPERAND_ADDR_WIDTH:0]	y_bram_addr_reg = bram_addr_zero;
+	reg	[OPERAND_ADDR_WIDTH:0]	n_bram_addr_reg = bram_addr_zero;
+	
+	assign x_bram_addr = x_bram_addr_reg;
+	assign y_bram_addr = y_bram_addr_reg;
+	assign n_bram_addr = n_bram_addr_reg;
+	
+	
+		//
+		// Z BRAM Interface
+		//
+	reg	[OPERAND_ADDR_WIDTH:0]	z_bram_addr_reg	= bram_addr_zero;
+	reg									z_bram_wr_reg		= 1'b0;
+	reg	[                 31:0]	z_bram_in_mux;
+	
+	assign z_bram_addr = z_bram_addr_reg;
+	assign z_bram_wr = z_bram_wr_reg;
+	assign z_bram_in = z_bram_in_mux;
+	
+			
+		//
+		// Handy Wires
+		//
+	wire	[OPERAND_ADDR_WIDTH-1:0]	operand_width_msb = operand_width[OPERAND_NUM_BITS-1:OPERAND_NUM_BITS-OPERAND_ADDR_WIDTH];
+	
+	wire	[OPERAND_ADDR_WIDTH  :0]	bram_addr_last				= {operand_width_msb, 1'b1};	// +1
+		
+
+		//
+		// Hardware Multiplier (X * Y)
+		//
+	reg	[31: 0]	multiplier_xy_carry_in;
+	wire	[31: 0]	multiplier_xy_out;
+	wire	[31: 0]	multiplier_xy_carry_out;
+	
+	modexps6_adder64_carry32 dsp_multiplier_xy
+	(
+		.clk		(clk),
+		.t			(/*(z_bram_addr_reg < bram_addr_last) ? */z_bram_out/* : {32{1'b0}}*/),
+		.x			(/*(z_bram_addr_reg < bram_addr_last) ? */x_bram_out/* : {32{1'b0}}*/),
+		.y			(/*(z_bram_addr_reg < bram_addr_last) ? */y_bram_out/* : {32{1'b0}}*/),
+		.s			(multiplier_xy_out),
+		.c_in		(multiplier_xy_carry_in),
+		.c_out	(multiplier_xy_carry_out)
+	);
+	
+	
+		//
+		// Hardware Multiplier (Magic)
+		//
+	wire	[63: 0]	multiplier_magic_out;
+	reg	[31: 0]	magic_value_reg;
+	
+	multiplier_s6 dsp_multiplier_magic
+	(
+		.clk	(clk),
+		.a		(z_bram_out),
+		.b		(n0_modinv),
+		.p		(multiplier_magic_out)
+	);
+	
+	
+		//
+		// Hardware Multiplier (M * N)
+		//
+	reg	[31: 0]	multiplier_mn_carry_in;
+	wire	[31: 0]	multiplier_mn_out;
+	wire	[31: 0]	multiplier_mn_carry_out;
+	
+	modexps6_adder64_carry32 dsp_multiplier_mn
+	(
+		.clk		(clk),
+		.t			(z_bram_out),
+		.x			(magic_value_reg),
+		.y			(/*(z_bram_addr_reg < bram_addr_last) ? */n_bram_out/* : {32{1'b0}}*/),
+		.s			(multiplier_mn_out),
+		.c_in		(multiplier_mn_carry_in),
+		.c_out	(multiplier_mn_carry_out)
+	);
+	
+	
+		//
+		// Z BRAM Input Selector
+		//
+	always @(*)
+		//
+		case (fsm_state)
+		
+			FSM_STATE_INIT:
+				//
+				z_bram_in_mux	= {32{1'b0}};
+				
+			FSM_STATE_MUL_XY_WRITE:
+				//
+				if (z_bram_addr_reg < bram_addr_last)	z_bram_in_mux	= multiplier_xy_out;
+				else												z_bram_in_mux	= multiplier_xy_carry_in;
+				
+			FSM_STATE_MUL_MN_WRITE:
+				//
+				if (z_bram_addr_reg < bram_addr_last)	z_bram_in_mux	= multiplier_mn_out;
+				else												z_bram_in_mux	= multiplier_mn_carry_in + z_bram_out;
+				
+			FSM_STATE_SHIFT:
+				//
+				z_bram_in_mux	= z_bram_out;
+		
+			default:
+				//
+				z_bram_in_mux	= {32{1'bX}};
+				
+		endcase
+
+	
+		//
+		// Handy Functions
+		//
+	function	[OPERAND_ADDR_WIDTH:0]	bram_addr_next_or_zero;
+		input	[OPERAND_ADDR_WIDTH:0]	bram_addr;
+		begin
+			bram_addr_next_or_zero = (bram_addr < bram_addr_last) ? bram_addr + 1'b1 : bram_addr_zero;
+		end
+	endfunction
+	
+	function	[OPERAND_ADDR_WIDTH:0]	bram_addr_next_or_last;
+		input	[OPERAND_ADDR_WIDTH:0]	bram_addr;
+		begin
+			bram_addr_next_or_last = (bram_addr < bram_addr_last) ? bram_addr + 1'b1 : bram_addr_last;
+		end
+	endfunction
+	
+	function	[OPERAND_ADDR_WIDTH:0]	bram_addr_prev_or_zero;
+		input	[OPERAND_ADDR_WIDTH:0]	bram_addr;
+		begin
+			bram_addr_prev_or_zero = (bram_addr > bram_addr_zero) ? bram_addr - 1'b1 : bram_addr_zero;
+		end
+	endfunction
+	
+	
+		//
+		// Round Counter
+		//
+	reg	[OPERAND_ADDR_WIDTH:0]	round_count			= round_count_zero;
+	wire	[OPERAND_ADDR_WIDTH:0]	round_count_last	= {operand_width_msb, 1'b0};
+	wire	[OPERAND_ADDR_WIDTH:0]	round_count_next	= (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero;
+	
+	
+		//
+		// Main Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+
+			FSM_STATE_INIT: begin
+				//
+				z_bram_wr_reg		<= (z_bram_addr_reg < bram_addr_last) ? 1'b1 : 1'b0;
+				z_bram_addr_reg	<= z_bram_wr_reg ? bram_addr_next_or_zero(z_bram_addr_reg) : bram_addr_zero;
+				//
+			end
+			
+			FSM_STATE_MUL_XY_CALC: begin
+				//
+				if (z_bram_addr_reg == bram_addr_zero) begin
+					//
+					multiplier_xy_carry_in <= {32{1'b0}};
+					//
+				end
+				//
+			end
+			
+			FSM_STATE_MUL_XY_REGISTER: begin
+				//
+				z_bram_wr_reg <= 1'b1;
+				//
+			end
+			
+			FSM_STATE_MUL_XY_WRITE: begin
+				//
+				z_bram_wr_reg			<= 1'b0;
+				z_bram_addr_reg		<= bram_addr_next_or_zero(z_bram_addr_reg);
+				//
+				x_bram_addr_reg		<= bram_addr_next_or_zero(x_bram_addr_reg);
+				//
+				multiplier_xy_carry_in	<= multiplier_xy_carry_out;
+				//
+			end
+			
+			FSM_STATE_MUL_MN_CALC: begin
+				//
+				if (z_bram_addr_reg == bram_addr_zero) begin
+					//
+					multiplier_mn_carry_in <= {32{1'b0}};
+					//
+					magic_value_reg <= multiplier_magic_out[31:0];
+					//
+				end
+				//
+			end
+			
+			FSM_STATE_MUL_MN_REGISTER: begin
+				//
+				z_bram_wr_reg <= 1'b1;
+				//
+			end
+			
+			FSM_STATE_MUL_MN_WRITE: begin
+				//
+				z_bram_wr_reg			<= 1'b0;
+				z_bram_addr_reg		<= bram_addr_next_or_last(z_bram_addr_reg);
+				//
+				n_bram_addr_reg		<= bram_addr_next_or_zero(n_bram_addr_reg);
+				//
+				multiplier_mn_carry_in	<= multiplier_mn_carry_out;
+				//
+			end
+			
+			FSM_STATE_SHIFT: begin
+				//
+				if (z_bram_wr_reg == 1'b0)							z_bram_wr_reg <= 1'b1;
+				else if (z_bram_addr_reg == bram_addr_zero)	z_bram_wr_reg <= 1'b0;
+				
+				z_bram_addr_reg	<= bram_addr_prev_or_zero(z_bram_addr_reg);
+				//
+			end
+			
+			FSM_STATE_ROUND: begin
+				//
+				y_bram_addr_reg	<= (round_count < round_count_last) ? bram_addr_next_or_zero(y_bram_addr_reg) : bram_addr_zero;
+				//
+				round_count <= round_count_next;
+				//
+			end
+
+		endcase
+	
+	
+		//
+		// FSM Transition Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+			//
+			FSM_STATE_IDLE:					fsm_state <= (!rdy_reg && ena_trig) ? FSM_STATE_INIT : FSM_STATE_IDLE;
+			
+			FSM_STATE_INIT:					fsm_state <= (z_bram_addr < bram_addr_last  ) ? FSM_STATE_INIT        : FSM_STATE_MUL_XY_CALC;
+			FSM_STATE_ROUND:					fsm_state <= (round_count < round_count_last) ? FSM_STATE_MUL_XY_CALC : FSM_STATE_FINAL;
+
+			FSM_STATE_MUL_XY_CALC:			fsm_state <= FSM_STATE_MUL_XY_PIPELINE;
+			FSM_STATE_MAGIC_CALC:			fsm_state <= FSM_STATE_MAGIC_PIPELINE;
+			FSM_STATE_MUL_MN_CALC:			fsm_state <= FSM_STATE_MUL_MN_PIPELINE;
+			
+			FSM_STATE_MUL_XY_PIPELINE:		fsm_state <= FSM_STATE_MUL_XY_REGISTER;
+			FSM_STATE_MAGIC_PIPELINE:		fsm_state <= FSM_STATE_MAGIC_REGISTER;
+			FSM_STATE_MUL_MN_PIPELINE:		fsm_state <= FSM_STATE_MUL_MN_REGISTER;
+			
+			FSM_STATE_MUL_XY_REGISTER:		fsm_state <= FSM_STATE_MUL_XY_WRITE;
+			FSM_STATE_MAGIC_REGISTER:		fsm_state <= FSM_STATE_MUL_MN_CALC;
+			FSM_STATE_MUL_MN_REGISTER:		fsm_state <= FSM_STATE_MUL_MN_WRITE;
+			
+			FSM_STATE_MUL_XY_WRITE:			fsm_state <= (z_bram_addr < bram_addr_last) ? FSM_STATE_MUL_XY_CALC : FSM_STATE_MAGIC_CALC;
+			FSM_STATE_MUL_MN_WRITE:			fsm_state <= (z_bram_addr < bram_addr_last) ? FSM_STATE_MUL_MN_CALC : FSM_STATE_SHIFT;
+			FSM_STATE_SHIFT:					fsm_state <= (z_bram_addr > bram_addr_zero) ? FSM_STATE_SHIFT       : FSM_STATE_ROUND;
+			
+			FSM_STATE_FINAL:					fsm_state <= FSM_STATE_IDLE;
+			
+			default:								fsm_state <= FSM_STATE_IDLE;
+
+		endcase
+
+
+endmodule
diff --git a/src/rtl/modexps6_top.v b/src/rtl/modexps6_top.v
new file mode 100644
index 0000000..29845f8
--- /dev/null
+++ b/src/rtl/modexps6_top.v
@@ -0,0 +1,696 @@
+`timescale 1ns / 1ps
+
+module modexps6_top
+	(
+		clk,
+		
+		init, ready,
+		next, valid,
+		
+		modulus_width,
+		exponent_width,
+		
+		fast_public_mode,
+		
+		bus_cs, bus_we,
+		bus_addr, bus_data_wr, bus_data_rd
+	);
+	
+	
+		//
+		// Parameters
+		//
+	parameter	MAX_MODULUS_WIDTH		= 1024;
+	
+	
+		//
+		// modexps6_clog2()
+		//
+	function	integer modexps6_clog2;
+		input	integer value;
+		integer ret;
+		begin
+			value = value - 1;
+			for (ret = 0; value > 0; ret = ret + 1)
+				value = value >> 1;
+			modexps6_clog2 = ret;
+		end
+	endfunction
+
+
+		//
+		// Locals
+		//
+	localparam	OPERAND_ADDR_WIDTH	= modexps6_clog2(MAX_MODULUS_WIDTH / 32);
+	localparam	MODULUS_NUM_BITS		= modexps6_clog2(MAX_MODULUS_WIDTH + 1);
+	localparam	ADDR_WIDTH_TOTAL		= OPERAND_ADDR_WIDTH + 2;
+	
+	localparam	[OPERAND_ADDR_WIDTH-1:0]	bram_user_addr_zero = {OPERAND_ADDR_WIDTH{1'b0}};
+	localparam	[OPERAND_ADDR_WIDTH  :0]	bram_core_addr_zero = {1'b0, {OPERAND_ADDR_WIDTH{1'b0}}};
+	
+	localparam	[    MODULUS_NUM_BITS:0]	round_count_zero = {1'b0, {MODULUS_NUM_BITS{1'b0}}};
+		
+		
+		//
+		// Ports
+		//
+	input		wire									clk;
+	
+	input		wire									init;
+	output	wire									ready;
+	
+	input		wire									next;
+	output	wire									valid;
+	
+	input		wire	[MODULUS_NUM_BITS-1:0]	modulus_width;
+	input		wire	[MODULUS_NUM_BITS-1:0]	exponent_width;
+
+	input		wire									fast_public_mode;
+	
+	input		wire									bus_cs;
+	input		wire									bus_we;
+	input		wire	[ADDR_WIDTH_TOTAL-1:0]	bus_addr;
+	input		wire	[                31:0]	bus_data_wr;
+	output	wire	[                31:0]	bus_data_rd;
+	
+		
+		//
+		// User Memory
+		//
+	wire	[OPERAND_ADDR_WIDTH-1:0]	ro_modulus_bram_addr;
+	wire	[                  31:0]	ro_modulus_bram_out;
+	
+	reg	[OPERAND_ADDR_WIDTH-1:0]	ro_message_bram_addr		= bram_user_addr_zero;
+	wire	[                  31:0]	ro_message_bram_out;
+		
+	reg	[OPERAND_ADDR_WIDTH-1:0]	ro_exponent_bram_addr	= bram_user_addr_zero;
+	wire	[                  31:0]	ro_exponent_bram_out;
+	
+	reg	[OPERAND_ADDR_WIDTH-1:0]	rw_result_bram_addr 		= bram_user_addr_zero;
+	wire	[                  31:0]	rw_result_bram_out;
+	reg										rw_result_bram_wr			= 1'b0;
+	wire	[                  31:0]	rw_result_bram_in;
+	
+	modexps6_buffer_user #
+	(
+		.OPERAND_ADDR_WIDTH		(OPERAND_ADDR_WIDTH)
+	)
+	mem_user
+	(
+		.clk							(clk),
+		
+		.bus_cs						(bus_cs),
+		.bus_we						(bus_we),
+		.bus_addr					(bus_addr),
+		.bus_data_wr				(bus_data_wr),
+		.bus_data_rd				(bus_data_rd),
+		
+		.ro_modulus_bram_addr	(ro_modulus_bram_addr),
+		.ro_modulus_bram_out		(ro_modulus_bram_out),
+		
+		.ro_message_bram_addr	(ro_message_bram_addr),
+		.ro_message_bram_out		(ro_message_bram_out),
+		
+		.ro_exponent_bram_addr	(ro_exponent_bram_addr),
+		.ro_exponent_bram_out	(ro_exponent_bram_out),
+		
+		.rw_result_bram_addr		(rw_result_bram_addr),
+		.rw_result_bram_wr		(rw_result_bram_wr),
+		.rw_result_bram_in		(rw_result_bram_in)
+	);
+	
+	
+		//
+		// Core (Internal) Memory
+		//
+	wire	[OPERAND_ADDR_WIDTH:0]	rw_coeff_bram_addr;
+	wire									rw_coeff_bram_wr;
+	wire	[                31:0]	rw_coeff_bram_in;
+	wire	[                31:0]	rw_coeff_bram_out;
+	
+	reg	[OPERAND_ADDR_WIDTH:0]	rw_mm_bram_addr		= bram_core_addr_zero;
+	reg									rw_mm_bram_wr			= 1'b0;
+	reg	[                31:0]	rw_mm_bram_in;
+	wire	[                31:0]	rw_mm_bram_out;
+	
+	wire	[OPERAND_ADDR_WIDTH:0]	rw_nn_bram_addr;
+	wire									rw_nn_bram_wr;
+	wire	[                31:0]	rw_nn_bram_in;
+	
+	reg	[OPERAND_ADDR_WIDTH:0]	rw_y_bram_addr			= bram_core_addr_zero;
+	reg									rw_y_bram_wr			= 1'b0;
+	reg	[               31:0]	rw_y_bram_in;
+	wire	[               31:0]	rw_y_bram_out;
+	
+	wire	[OPERAND_ADDR_WIDTH:0]	rw_r_bram_addr;
+	wire									rw_r_bram_wr;
+	wire	[               31:0]	rw_r_bram_in;
+	wire	[               31:0]	rw_r_bram_out;
+
+	reg	[OPERAND_ADDR_WIDTH:0]	rw_t_bram_addr			= bram_core_addr_zero;
+	reg									rw_t_bram_wr			= 1'b0;
+	reg	[               31:0]	rw_t_bram_in;
+	wire	[               31:0]	rw_t_bram_out;
+	
+	reg	[OPERAND_ADDR_WIDTH:0]	ro_coeff_bram_addr	= bram_core_addr_zero;
+	wire	[                31:0]	ro_coeff_bram_out;
+	
+	wire	[OPERAND_ADDR_WIDTH:0]	ro_mm_bram_addr;
+	wire	[                31:0]	ro_mm_bram_out;
+	
+	wire	[OPERAND_ADDR_WIDTH:0]	ro_nn_bram_addr;
+	wire	[                31:0]	ro_nn_bram_out;		
+	
+	reg	[OPERAND_ADDR_WIDTH:0]	ro_r_bram_addr			= bram_core_addr_zero;
+	wire	[                31:0]	ro_r_bram_out;
+
+	wire	[OPERAND_ADDR_WIDTH:0]	ro_t_bram_addr;
+	wire	[               31:0]	ro_t_bram_out;
+	
+	modexps6_buffer_core #
+	(
+		.OPERAND_ADDR_WIDTH	(OPERAND_ADDR_WIDTH)
+	)
+	mem_core
+	(
+		.clk						(clk),
+		
+		.rw_coeff_bram_addr	(rw_coeff_bram_addr),
+		.rw_coeff_bram_wr		(rw_coeff_bram_wr),
+		.rw_coeff_bram_in		(rw_coeff_bram_in),
+		.rw_coeff_bram_out	(rw_coeff_bram_out),
+		
+		.rw_mm_bram_addr		(rw_mm_bram_addr),
+		.rw_mm_bram_wr			(rw_mm_bram_wr),
+		.rw_mm_bram_in			(rw_mm_bram_in),
+		.rw_mm_bram_out		(rw_mm_bram_out),
+		
+		.rw_nn_bram_addr		(rw_nn_bram_addr),
+		.rw_nn_bram_wr			(rw_nn_bram_wr),
+		.rw_nn_bram_in			(rw_nn_bram_in),
+
+		.rw_y_bram_addr		(rw_y_bram_addr),
+		.rw_y_bram_wr			(rw_y_bram_wr),
+		.rw_y_bram_in			(rw_y_bram_in),
+		.rw_y_bram_out			(rw_y_bram_out),
+		
+		.rw_r_bram_addr		(rw_r_bram_addr),
+		.rw_r_bram_wr			(rw_r_bram_wr),
+		.rw_r_bram_in			(rw_r_bram_in),
+		.rw_r_bram_out			(rw_r_bram_out),
+		
+		.rw_t_bram_addr		(rw_t_bram_addr),
+		.rw_t_bram_wr			(rw_t_bram_wr),
+		.rw_t_bram_in			(rw_t_bram_in),
+		.rw_t_bram_out			(rw_t_bram_out),
+
+		.ro_coeff_bram_addr	(ro_coeff_bram_addr),
+		.ro_coeff_bram_out	(ro_coeff_bram_out),		
+		
+		.ro_mm_bram_addr		(ro_mm_bram_addr),
+		.ro_mm_bram_out		(ro_mm_bram_out),
+		
+		.ro_nn_bram_addr		(ro_nn_bram_addr),
+		.ro_nn_bram_out		(ro_nn_bram_out),
+		
+		.ro_r_bram_addr		(ro_r_bram_addr),
+		.ro_r_bram_out			(ro_r_bram_out),
+		
+		.ro_t_bram_addr		(ro_t_bram_addr),
+		.ro_t_bram_out			(ro_t_bram_out)
+	);
+	
+	
+		//
+		// Small 32-bit ModInv Core
+		//
+	wire				modinv_ena;
+	wire				modinv_rdy;
+
+	wire	[31: 0]	modinv_n0;
+	wire	[31: 0]	modinv_n0_negative = ~modinv_n0 + 1'b1;
+	wire	[31: 0]	modinv_n0_modinv;
+	
+	modexps6_modinv32 core_modinv32
+	(
+		.clk			(clk),
+		
+		.ena			(modinv_ena),
+		.rdy			(modinv_rdy),
+		
+		.n0			(modinv_n0_negative),
+		.n0_modinv	(modinv_n0_modinv)
+	);
+	
+	
+		//
+		// Montgomery Coefficient Calculator
+		//
+	modexps6_montgomery_coeff #
+	(
+		.MODULUS_NUM_BITS		(MODULUS_NUM_BITS),
+		.OPERAND_ADDR_WIDTH	(OPERAND_ADDR_WIDTH)
+	)
+	core_montgomery_coeff
+	(
+		.clk						(clk),
+		
+		.ena						(init),
+		.rdy						(ready),
+		
+		.modulus_width			(modulus_width),
+		
+		.coeff_bram_addr		(rw_coeff_bram_addr),
+		.coeff_bram_wr			(rw_coeff_bram_wr),
+		.coeff_bram_in			(rw_coeff_bram_in),
+		.coeff_bram_out		(rw_coeff_bram_out),
+		
+		.nn_bram_addr			(rw_nn_bram_addr),
+		.nn_bram_wr				(rw_nn_bram_wr),
+		.nn_bram_in				(rw_nn_bram_in),
+	
+		.modulus_bram_addr	(ro_modulus_bram_addr),
+		.modulus_bram_out		(ro_modulus_bram_out),
+		
+		.modinv_n0				(modinv_n0),
+		.modinv_ena				(modinv_ena),
+		.modinv_rdy				(modinv_rdy)
+	);
+	
+	
+		//
+		// Montgomery Multiplier
+		//
+	reg	mul_ena = 1'b0;
+	wire	mul_rdy;
+	
+	modexps6_montgomery_multiplier #
+	(
+		.OPERAND_NUM_BITS		(MODULUS_NUM_BITS),
+		.OPERAND_ADDR_WIDTH	(OPERAND_ADDR_WIDTH)
+	)
+	core_montgomery_multiplier
+	(
+		.clk					(clk),
+		
+		.ena					(mul_ena),
+		.rdy					(mul_rdy),
+		
+		.operand_width		(modulus_width),
+		
+		.x_bram_addr		(ro_t_bram_addr),
+		.x_bram_out			(ro_t_bram_out),
+		
+		.y_bram_addr		(ro_mm_bram_addr),
+		.y_bram_out			(ro_mm_bram_out),
+		
+		.n_bram_addr		(ro_nn_bram_addr),
+		.n_bram_out			(ro_nn_bram_out),
+		
+		.z_bram_addr		(rw_r_bram_addr),
+		.z_bram_wr			(rw_r_bram_wr),
+		.z_bram_in			(rw_r_bram_in),
+		.z_bram_out			(rw_r_bram_out),
+		
+		.n0_modinv			(modinv_n0_modinv)
+	);
+
+
+		//
+		// FSM
+		//
+	localparam FSM_STATE_IDLE					= 6'd0;
+	
+	localparam FSM_STATE_INIT_LOAD			= 6'd11;
+	localparam FSM_STATE_INIT_WAIT			= 6'd12;
+	localparam FSM_STATE_INIT_UNLOAD			= 6'd13;
+	
+	localparam FSM_STATE_READ_EI				= 6'd20;
+	
+	localparam FSM_STATE_ROUND_BEGIN			= 6'd25;
+	
+	localparam FSM_STATE_MULTIPLY_LOAD		= 6'd31;
+	localparam FSM_STATE_MULTIPLY_WAIT		= 6'd32;
+	localparam FSM_STATE_MULTIPLY_UNLOAD	= 6'd33;
+
+	localparam FSM_STATE_SQUARE_LOAD			= 6'd41;
+	localparam FSM_STATE_SQUARE_WAIT			= 6'd42;
+	localparam FSM_STATE_SQUARE_UNLOAD		= 6'd43;
+	
+	localparam FSM_STATE_ROUND_END			= 6'd50;
+	
+	localparam FSM_STATE_FINAL					= 6'd60;
+	
+	reg	[ 5: 0]	fsm_state = FSM_STATE_IDLE;
+	
+	
+		//
+		// Trigger
+		//
+	reg next_dly = 1'b0;
+	always @(posedge clk) next_dly <= next;
+	wire next_trig = (next == 1'b1) && (next_dly == 1'b0);
+	
+	
+		//
+		// Valid Register
+		//
+	reg valid_reg = 1'b0;
+	assign valid = valid_reg;
+	
+	
+		//
+		// Next/ Valid Logic
+		//
+	always @(posedge clk)
+		//
+		if (fsm_state == FSM_STATE_FINAL) begin
+			//
+			valid_reg <= 1'b1;
+			//
+		end else if (fsm_state == FSM_STATE_IDLE) begin
+			//
+			if (valid_reg && !next) valid_reg <= 1'b0;
+			//
+		end
+		
+		
+		//
+		// Exponent Bit Counter
+		//
+	reg	[ 4: 0]	ei_bit_count = 5'd0;
+	wire				ei_bit = ro_exponent_bram_out[ei_bit_count];
+		
+		
+		//
+		// Round Counter
+		//
+	reg	[MODULUS_NUM_BITS:0]	round_count			= round_count_zero;
+	wire	[MODULUS_NUM_BITS:0]	round_count_last	= exponent_width - 1'b1;
+	wire	[MODULUS_NUM_BITS:0]	round_count_next	= (round_count < round_count_last) ? round_count + 1'b1 : round_count_zero;
+	
+	
+		//
+		// Handy Wires
+		//
+	wire	[OPERAND_ADDR_WIDTH-1:0]	modulus_width_msb = modulus_width[MODULUS_NUM_BITS-1:MODULUS_NUM_BITS-OPERAND_ADDR_WIDTH];
+	
+	wire	[OPERAND_ADDR_WIDTH  :0]	bram_core_addr_last	= {modulus_width_msb, 1'b0};
+	
+	wire	[OPERAND_ADDR_WIDTH  :0]	bram_user_addr_last_ext		= bram_core_addr_last - 1'b1;
+	wire	[OPERAND_ADDR_WIDTH-1:0]	bram_user_addr_last			= bram_user_addr_last_ext[OPERAND_ADDR_WIDTH-1:0];
+		
+		
+		//
+		// Handy Functions
+		//
+	function	[OPERAND_ADDR_WIDTH:0]	bram_core_addr_next_or_zero;
+		input	[OPERAND_ADDR_WIDTH:0]	bram_core_addr;
+		begin
+			bram_core_addr_next_or_zero = (bram_core_addr < bram_core_addr_last) ? bram_core_addr + 1'b1 : bram_core_addr_zero;
+		end
+	endfunction
+	
+	function	[OPERAND_ADDR_WIDTH-1:0]	bram_user_addr_next_or_zero;
+		input	[OPERAND_ADDR_WIDTH-1:0]	bram_user_addr;
+		begin
+			bram_user_addr_next_or_zero = (bram_user_addr < bram_user_addr_last) ? bram_user_addr + 1'b1 : bram_user_addr_zero;
+		end
+	endfunction
+	
+	
+		//
+		// Result BRAM Input
+		//
+	assign rw_result_bram_in = ei_bit ? ro_r_bram_out : rw_t_bram_out;
+	
+	
+		//
+		// MM BRAM Input Selector
+		//
+	always @(*)
+		//
+		case (fsm_state)
+			
+			FSM_STATE_INIT_LOAD:
+				//
+				rw_mm_bram_in = (rw_mm_bram_addr < bram_core_addr_last) ? ro_message_bram_out : {32{1'b0}};
+			
+			FSM_STATE_INIT_UNLOAD:
+				//
+				rw_mm_bram_in = ro_r_bram_out;
+				
+			FSM_STATE_SQUARE_UNLOAD:
+				//
+				rw_mm_bram_in = ro_r_bram_out;
+			
+			default:
+				//
+				rw_mm_bram_in	= {32{1'bX}};
+			
+		endcase
+		
+		
+		//
+		// Y BRAM Input Selector
+		//
+	always @(*)
+		//
+		case (fsm_state)
+		
+			FSM_STATE_INIT_LOAD:
+				//
+				rw_y_bram_in = (rw_mm_bram_addr == bram_core_addr_zero) ? 32'h00000001 : 32'h00000000;
+				
+			FSM_STATE_MULTIPLY_UNLOAD:
+				//
+				rw_y_bram_in = ei_bit ? ro_r_bram_out : rw_t_bram_out; // RW!
+		
+			default:
+				//
+				rw_y_bram_in	= {32{1'bX}};
+				
+		endcase
+		
+		
+		//
+		// T BRAM Input Selector
+		//
+	always @(*)
+		//
+		case (fsm_state)
+		
+			FSM_STATE_INIT_LOAD:
+				//
+				rw_t_bram_in = ro_coeff_bram_out;
+				
+			FSM_STATE_MULTIPLY_LOAD:
+				//
+				rw_t_bram_in = rw_y_bram_out;
+				
+			FSM_STATE_SQUARE_LOAD:
+				//
+				rw_t_bram_in = rw_mm_bram_out;
+		
+			default:
+				//
+				rw_t_bram_in	= {32{1'bX}};
+				
+		endcase
+	
+	
+		//
+		// Main Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+			
+			FSM_STATE_INIT_LOAD: begin
+				//
+				rw_mm_bram_wr		<= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				rw_y_bram_wr		<= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				rw_t_bram_wr		<= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_mm_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+				rw_y_bram_addr		<= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+				rw_t_bram_addr		<= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+				//
+				if (ro_coeff_bram_addr > bram_core_addr_zero) ro_coeff_bram_addr	<= bram_core_addr_next_or_zero(ro_coeff_bram_addr);
+				else ro_coeff_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_coeff_bram_addr);
+				//
+				if (ro_message_bram_addr > bram_user_addr_zero) ro_message_bram_addr	<= bram_user_addr_next_or_zero(ro_message_bram_addr);
+				else ro_message_bram_addr <= rw_mm_bram_wr ? bram_user_addr_zero : bram_user_addr_next_or_zero(ro_message_bram_addr);
+				//
+			end
+			
+			FSM_STATE_INIT_WAIT: begin
+				//
+				if (mul_ena)	mul_ena	<= mul_rdy ? 1'b0 : 1'b1;
+				else				mul_ena	<= 1'b1;
+				//
+			end
+			
+			FSM_STATE_INIT_UNLOAD: begin
+				//
+				rw_mm_bram_wr		<= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_mm_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+				//
+				if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr	<= bram_core_addr_next_or_zero(ro_r_bram_addr);
+				else ro_r_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);
+				//
+			end
+			
+			FSM_STATE_MULTIPLY_LOAD: begin
+				//
+				rw_t_bram_wr		<= (rw_t_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_t_bram_addr		<= rw_t_bram_wr ? bram_core_addr_next_or_zero(rw_t_bram_addr) : bram_core_addr_zero;
+				//
+				if (rw_y_bram_addr > bram_core_addr_zero) rw_y_bram_addr	<= bram_core_addr_next_or_zero(rw_y_bram_addr);
+				else rw_y_bram_addr	<= rw_t_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_y_bram_addr);				
+				//
+			end
+			
+			FSM_STATE_MULTIPLY_WAIT: begin
+				//
+				if (mul_ena)	mul_ena	<= mul_rdy ? 1'b0 : 1'b1;
+				else				mul_ena	<= 1'b1;				
+				//
+			end
+			
+			FSM_STATE_MULTIPLY_UNLOAD: begin
+				//
+				rw_y_bram_wr		<= (rw_y_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_y_bram_addr		<= rw_y_bram_wr ? bram_core_addr_next_or_zero(rw_y_bram_addr) : bram_core_addr_zero;
+				//
+				if (ei_bit) begin
+					//
+					if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr	<= bram_core_addr_next_or_zero(ro_r_bram_addr);
+					else ro_r_bram_addr	<= rw_y_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);				
+					//
+				end else begin
+					//
+					if (rw_t_bram_addr > bram_core_addr_zero) rw_t_bram_addr	<= bram_core_addr_next_or_zero(rw_t_bram_addr);
+					else rw_t_bram_addr	<= rw_y_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_t_bram_addr);				
+					//
+				end
+				//
+				if (round_count == round_count_last) begin
+					//
+					if (rw_result_bram_addr == bram_user_addr_zero) begin
+						//
+						if (rw_y_bram_wr) begin
+							//
+							rw_result_bram_wr		<= (rw_y_bram_addr > bram_core_addr_zero) ? 1'b0 : 1'b1;
+							rw_result_bram_addr	<= (rw_y_bram_addr > bram_core_addr_zero) ? bram_user_addr_zero : bram_user_addr_next_or_zero(rw_result_bram_addr);
+							//
+						end else begin
+							//
+							rw_result_bram_wr		<= 1'b1;
+							rw_result_bram_addr	<= bram_user_addr_zero;
+							//
+						end
+						//
+					end else begin
+						//
+						rw_result_bram_wr		<= (rw_result_bram_addr < bram_user_addr_last) ? 1'b1 : 1'b0;
+						rw_result_bram_addr	<= bram_user_addr_next_or_zero(rw_result_bram_addr);
+						//
+					end
+					//
+				end
+				//
+			end
+			
+			FSM_STATE_SQUARE_LOAD: begin
+				//
+				rw_t_bram_wr		<= (rw_t_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_t_bram_addr		<= rw_t_bram_wr ? bram_core_addr_next_or_zero(rw_t_bram_addr) : bram_core_addr_zero;
+				//
+				if (rw_mm_bram_addr > bram_core_addr_zero) rw_mm_bram_addr	<= bram_core_addr_next_or_zero(rw_mm_bram_addr);
+				else rw_mm_bram_addr	<= rw_t_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(rw_mm_bram_addr);								
+				//
+			end
+			
+			FSM_STATE_SQUARE_WAIT: begin
+				//
+				if (mul_ena)	mul_ena	<= mul_rdy ? 1'b0 : 1'b1;
+				else				mul_ena	<= 1'b1;								
+				//
+			end
+			
+			FSM_STATE_SQUARE_UNLOAD: begin
+				//
+				rw_mm_bram_wr		<= (rw_mm_bram_addr < bram_core_addr_last) ? 1'b1 : 1'b0;
+				//
+				rw_mm_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_next_or_zero(rw_mm_bram_addr) : bram_core_addr_zero;
+				//
+				if (ro_r_bram_addr > bram_core_addr_zero) ro_r_bram_addr	<= bram_core_addr_next_or_zero(ro_r_bram_addr);
+				else ro_r_bram_addr	<= rw_mm_bram_wr ? bram_core_addr_zero : bram_core_addr_next_or_zero(ro_r_bram_addr);				
+				//
+			end
+			
+			FSM_STATE_ROUND_END: begin
+				//
+				round_count <= round_count_next;
+				//
+				if (round_count < round_count_last) begin
+					//
+					ei_bit_count <= ei_bit_count + 1'b1;
+					//
+					if (ei_bit_count == 5'd31)
+						//
+						ro_exponent_bram_addr <= bram_user_addr_next_or_zero(ro_exponent_bram_addr);
+					//
+				end else begin
+					//
+					ei_bit_count <= 5'd0;
+					//
+					ro_exponent_bram_addr <= bram_user_addr_zero;
+					//
+				end
+				//
+			end
+			
+		endcase
+		
+	
+		//
+		// FSM Transition Logic
+		//
+	always @(posedge clk)
+		//
+		case (fsm_state)
+			
+			FSM_STATE_IDLE:					fsm_state <= (!valid_reg && next_trig) ? FSM_STATE_INIT_LOAD : FSM_STATE_IDLE;
+			
+			FSM_STATE_INIT_LOAD:				fsm_state <= (rw_y_bram_addr < bram_core_addr_last) ? FSM_STATE_INIT_LOAD : FSM_STATE_INIT_WAIT;
+			FSM_STATE_INIT_WAIT:				fsm_state <= mul_rdy ? FSM_STATE_INIT_UNLOAD : FSM_STATE_INIT_WAIT;
+			FSM_STATE_INIT_UNLOAD:			fsm_state <= (rw_mm_bram_addr < bram_core_addr_last) ? FSM_STATE_INIT_UNLOAD : FSM_STATE_READ_EI;
+			
+			FSM_STATE_READ_EI:				fsm_state <= FSM_STATE_ROUND_BEGIN;
+			
+			FSM_STATE_ROUND_BEGIN:			fsm_state <= (!ei_bit && fast_public_mode && (round_count < round_count_last)) ? FSM_STATE_SQUARE_LOAD : FSM_STATE_MULTIPLY_LOAD;
+			
+			FSM_STATE_MULTIPLY_LOAD:		fsm_state <= (rw_t_bram_addr < bram_core_addr_last) ? FSM_STATE_MULTIPLY_LOAD : FSM_STATE_MULTIPLY_WAIT;
+			FSM_STATE_MULTIPLY_WAIT:		fsm_state <= mul_rdy ? FSM_STATE_MULTIPLY_UNLOAD : FSM_STATE_MULTIPLY_WAIT;
+			FSM_STATE_MULTIPLY_UNLOAD:		fsm_state <= (rw_y_bram_addr < bram_core_addr_last) ? FSM_STATE_MULTIPLY_UNLOAD : FSM_STATE_SQUARE_LOAD;
+			
+			FSM_STATE_SQUARE_LOAD:			fsm_state <= (rw_t_bram_addr < bram_core_addr_last) ? FSM_STATE_SQUARE_LOAD : FSM_STATE_SQUARE_WAIT;
+			FSM_STATE_SQUARE_WAIT:			fsm_state <= mul_rdy ? FSM_STATE_SQUARE_UNLOAD : FSM_STATE_SQUARE_WAIT;
+			FSM_STATE_SQUARE_UNLOAD:		fsm_state <= (rw_mm_bram_addr < bram_core_addr_last) ? FSM_STATE_SQUARE_UNLOAD : FSM_STATE_ROUND_END;
+			
+			FSM_STATE_ROUND_END:				fsm_state <= (round_count < round_count_last) ? FSM_STATE_READ_EI : FSM_STATE_FINAL;
+			
+			FSM_STATE_FINAL:					fsm_state <= FSM_STATE_IDLE;
+			
+			default:								fsm_state <= FSM_STATE_IDLE;
+			
+		endcase
+	
+	
+endmodule
diff --git a/src/rtl/modexps6_wrapper.v b/src/rtl/modexps6_wrapper.v
new file mode 100644
index 0000000..3fad0f9
--- /dev/null
+++ b/src/rtl/modexps6_wrapper.v
@@ -0,0 +1,187 @@
+module modexps6_wrapper
+	(
+		clk, rst,
+		cs, we,
+		address, write_data, read_data
+	);
+	
+	
+		//
+		// Ports
+		//
+	input		wire           clk;
+	input		wire           rst;
+
+	input		wire           cs;
+	input		wire           we;
+
+	input		wire  [ 9: 0]	address;
+	input		wire  [31: 0]	write_data;
+	output	wire	[31: 0]	read_data;
+	
+	
+		//
+		// Address Decoder
+		//
+	localparam	ADDR_MSB_REGS	= 1'b0;
+	localparam	ADDR_MSB_CORE	= 1'b1;
+	wire				address_msb = address[9];
+	wire	[ 8: 0]	address_lsb	= address[8:0];
+	
+	
+		//
+		// Output Mux
+		//
+	wire	[31: 0]	read_data_regs;
+	wire	[31: 0]	read_data_core;
+	
+	
+	  //
+	  // Registers
+	  //
+	localparam ADDR_NAME0			= 9'h000;
+	localparam ADDR_NAME1			= 9'h001;
+	localparam ADDR_VERSION			= 9'h002;
+
+	localparam ADDR_CONTROL			= 9'h008;		// {next, init}
+	localparam ADDR_STATUS			= 9'h009;		// {valid, ready}
+	localparam ADDR_MODE				= 9'h010;		// 0 = slow secure, 1 = fast unsafe (public)
+	localparam ADDR_MODULUS_BITS	= 9'h011;		// 
+	localparam ADDR_EXPONENT_BITS	= 9'h012;		// 
+	localparam ADDR_GPIO_REG		= 9'h020;		// 
+
+	localparam CONTROL_INIT_BIT	= 0;
+	localparam CONTROL_NEXT_BIT	= 1;
+
+	localparam STATUS_READY_BIT	= 0;
+	localparam STATUS_VALID_BIT	= 1;
+
+	localparam CORE_NAME0			= 32'h6D6F6465;	// "mode"
+	localparam CORE_NAME1			= 32'h78707336;	// "xps6"
+	localparam CORE_VERSION			= 32'h302E3130;	// "0.10"
+
+
+		//
+		// Registers
+		//
+	reg	[ 1: 0]	reg_control;
+	reg				reg_mode;
+	reg	[12: 0]	reg_modulus_width;
+	reg	[12: 0]	reg_exponent_width;
+	reg	[31: 0]	reg_gpio;
+	
+	
+		//
+		// Wires
+		//
+	wire	[ 1: 0]	reg_status;
+		
+		
+		//
+		// ModExpS6
+		//
+	modexps6_top #
+	(
+		.MAX_MODULUS_WIDTH	(4096)
+	)
+	modexps6_core
+	(
+		.clk						(clk),
+		
+		.init						(reg_control[CONTROL_INIT_BIT]),
+		.ready					(reg_status[STATUS_READY_BIT]),
+		.next						(reg_control[CONTROL_NEXT_BIT]),
+		.valid					(reg_status[STATUS_VALID_BIT]),
+		
+		.modulus_width			(reg_modulus_width),
+		.exponent_width		(reg_exponent_width),
+		
+		.fast_public_mode		(reg_mode),
+		
+		.bus_cs					(cs && (address_msb == ADDR_MSB_CORE)),
+		.bus_we					(we),
+		.bus_addr				(address_lsb),
+		.bus_data_wr			(write_data),
+		.bus_data_rd			(read_data_core)
+	);
+	
+	
+		//
+		// Read Latch
+		//
+	reg [31: 0] tmp_read_data;
+
+
+	//
+	// Read/Write Interface
+	//
+	always @(posedge clk)
+		//
+		if (rst) begin
+			//
+			reg_control				<= 2'b00;
+			reg_mode					<= 1'b0;
+			reg_modulus_width		<= 13'd1024;
+			reg_exponent_width	<= 13'd1024;
+			//
+		end else if (cs && (address_msb == ADDR_MSB_REGS)) begin
+			//
+			if (we) begin
+				//
+				// Write Handler
+				//
+				case (address_lsb)
+					//
+					ADDR_CONTROL:			reg_control				<= write_data[ 1: 0];
+					ADDR_MODE:				reg_mode					<= write_data[0];
+					ADDR_MODULUS_BITS:	reg_modulus_width		<= write_data[12: 0];
+					ADDR_EXPONENT_BITS:	reg_exponent_width	<= write_data[12: 0];
+					ADDR_GPIO_REG:			reg_gpio					<= write_data;
+					//
+				endcase
+				//	
+			end else begin
+				//
+				// Read Handler
+				//
+				case (address)
+					//
+					ADDR_NAME0:				tmp_read_data <= CORE_NAME0;
+					ADDR_NAME1:				tmp_read_data <= CORE_NAME1;
+					ADDR_VERSION:			tmp_read_data <= CORE_VERSION;
+					ADDR_CONTROL:			tmp_read_data <= {{30{1'b0}}, reg_control};
+					ADDR_STATUS:			tmp_read_data <= {{30{1'b0}}, reg_status};
+					ADDR_MODE:				tmp_read_data <= {{31{1'b0}}, reg_mode};
+					ADDR_MODULUS_BITS:	tmp_read_data <= {{19{1'b0}}, reg_modulus_width};
+					ADDR_EXPONENT_BITS:	tmp_read_data <= {{19{1'b0}}, reg_exponent_width};
+					ADDR_GPIO_REG:			tmp_read_data <= reg_gpio;
+					//
+					default:					tmp_read_data <= 32'h00000000;
+					//
+				endcase
+				//
+			end
+			//
+		end
+		
+		
+		//
+		// Register / Core Memory Selector
+		//
+	reg address_msb_last;
+	always @(posedge clk) address_msb_last = address_msb;
+	
+	reg	[31: 0]	read_data_mux;
+	assign read_data = read_data_mux;	
+	
+	always @(*)
+		//
+		case (address_msb_last)
+			//
+			ADDR_MSB_REGS:		read_data_mux = tmp_read_data;
+			ADDR_MSB_CORE:		read_data_mux = read_data_core;
+			//
+		endcase
+
+		
+endmodule
diff --git a/src/rtl/ram_1rw_1ro_readfirst.v b/src/rtl/ram_1rw_1ro_readfirst.v
new file mode 100644
index 0000000..7ba11ea
--- /dev/null
+++ b/src/rtl/ram_1rw_1ro_readfirst.v
@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+
+module ram_1rw_1ro_readfirst
+	(
+		clk,
+		a_addr, a_wr, a_in, a_out,
+		b_addr, b_out
+	);
+
+		
+		//
+		// Parameters
+		//
+	parameter	MEM_WIDTH		= 32;
+   parameter	MEM_ADDR_BITS	= 8;
+		
+		
+		//
+		// Ports
+		//
+	input		wire								clk;
+	
+	input		wire	[MEM_ADDR_BITS-1:0]	a_addr;
+	input		wire								a_wr;
+	input		wire	[MEM_WIDTH-1:0]		a_in;
+	output	wire	[MEM_WIDTH-1:0]		a_out;
+	
+	input		wire	[MEM_ADDR_BITS-1:0]	b_addr;
+	output	wire	[MEM_WIDTH-1:0]		b_out;
+		
+		
+		//
+		// BRAM
+		//
+   (* RAM_STYLE="BLOCK" *)
+   reg	[MEM_WIDTH-1:0]	bram[0:(2**MEM_ADDR_BITS)-1];
+	
+	
+		//
+		// Output Registers
+		//
+   reg	[MEM_WIDTH-1:0]	bram_reg_a;
+	reg	[MEM_WIDTH-1:0]	bram_reg_b;
+	
+	assign a_out = bram_reg_a;
+	assign b_out = bram_reg_b;
+
+
+		//
+		// Read-Write Port A
+		//
+   always @(posedge clk) begin
+		//
+		bram_reg_a <= bram[a_addr];
+		//
+		if (a_wr) bram[a_addr] <= a_in;
+		//
+	end
+		
+		
+		//
+		// Read-Only Port B
+		//
+	always @(posedge clk)
+		//
+		bram_reg_b <= bram[b_addr];
+		
+	
+endmodule
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