[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: (1) Moved the input buffer and clock tree insertion for the burst clock into the burst clock dll to keep it more clean. (2) Removed ddr3 comment that does not belong in the code.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 971339d43c9e8231ed06c4da921553f654348329
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Fri Jan 23 07:26:23 2015 +0100

    (1) Moved the input buffer and clock tree insertion for the burst clock into the burst clock dll to keep it more clean. (2) Removed ddr3 comment that does not belong in the code.
---
 src/macros/bclk_dll.v     | 41 +++++++++++++++++++++--------------------
 src/rtl/novena_fpga_eim.v |  8 --------
 2 files changed, 21 insertions(+), 28 deletions(-)

diff --git a/src/macros/bclk_dll.v b/src/macros/bclk_dll.v
index 5683930..427a565 100644
--- a/src/macros/bclk_dll.v
+++ b/src/macros/bclk_dll.v
@@ -63,32 +63,24 @@
 //----------------------------------------------------------------------------
 // __primary_________133.014_____________0.01
 
-`timescale 1ps/1ps
 
 (* CORE_GENERATION_INFO = "bclk_dll,clk_wiz_v4_1,{component_name=bclk_dll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=7.518,clkin2_period=7.518,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO, [...]
-module bclk_dll
-
- (// Clock in ports
-  input         clk133in,
-  // Clock out ports
-  output        clk133,
-  output        clk66,
-  // Status and control signals
-  input         RESET,
-  output        LOCKED
- );
+module bclk_dll (
+                 input clk133in,
 
-  // Input buffering
-  //------------------------------------
-  assign clkin1 = clk133in;
+                 output clk133,
+                 output clk66,
 
+                 input  RESET,
+                 output LOCKED
+                );
 
-  // Clocking primitive
-  //------------------------------------
 
-  // Instantiation of the DCM primitive
-  //    * Unused inputs are tied off
-  //    * Unused outputs are labeled unused
+  //----------------------------------------------------------------
+  // Wires.
+  //----------------------------------------------------------------
+  wire clkin1;
+  wire clk133in_ibufg;
   wire        psdone_unused;
   wire        locked_int;
   wire [7:0]  status_int;
@@ -96,6 +88,15 @@ module bclk_dll
   wire clk0;
   wire clkfx;
 
+
+  // Input buffering
+  //------------------------------------
+  IBUFG clkibufg(.I(clk133in), .O(clk133in_ibufg));
+  BUFG bclk_dll_bufg(.I(clk133in_ibufg), .O(clkin1));
+
+
+  // Clocking primitive
+  //------------------------------------
   DCM_SP
   #(.CLKDV_DIVIDE          (2.000),
     .CLKFX_DIVIDE          (4),
diff --git a/src/rtl/novena_fpga_eim.v b/src/rtl/novena_fpga_eim.v
index 265f942..a37d2ac 100644
--- a/src/rtl/novena_fpga_eim.v
+++ b/src/rtl/novena_fpga_eim.v
@@ -102,10 +102,6 @@ module novena_fpga_eim(
 //  wire i_fbk_out, i_fbk_in;
 //  wire o_fbk_out, o_fbk_in;
 //
-//  IBUFG clkibufg(.I(EIM_BCLK), .O(bclk));
-//
-//  BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in));
-//
 //  bclk_dll bclk_dll_mod(.clk133in(bclk_int_in), .clk133(bclk_dll),
 //			.RESET(reset), .LOCKED(bclk_locked));
 //
@@ -641,10 +637,6 @@ module novena_fpga_eim(
 //   IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
 //   IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
 //
-//   //////////////
-//   // DDR3 interface macro
-//   //////////////
-//
 //   wire c1_clk0, c1_rst0;