[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: Adding ports and associated pins, IO-types etc to drive the LEDs on Cryptech Avalanche Noise Board. Connected LEDs to separate counters for each clock. We can now observe the clocks generated.

[git at cryptech.is]

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 507050f1efafe87be690efe7e8a19f3a535a3879
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Jan 22 16:22:40 2015 +0100

    Adding ports and associated pins, IO-types etc to drive the LEDs on Cryptech Avalanche Noise Board. Connected LEDs to separate counters for each clock. We can now observe the clocks generated.
---
 src/constraints/novena_fpga.ucf | 54 +++++++++++++++++++++++++++++++++--------
 src/rtl/novena_fpga.v           | 50 +++++++++++++++++++++++++++++++++-----
 2 files changed, 88 insertions(+), 16 deletions(-)

diff --git a/src/constraints/novena_fpga.ucf b/src/constraints/novena_fpga.ucf
index 6e1ece8..4255abd 100755
--- a/src/constraints/novena_fpga.ucf
+++ b/src/constraints/novena_fpga.ucf
@@ -34,11 +34,11 @@ CONFIG VCCAUX  = 3.3;
 CONFIG MCB_PERFORMANCE  = EXTENDED;
 
 # ### define setup/hold constraints for EIM
-OFFSET = IN 4125 ps VALID 4750 ps BEFORE "bclk";
+# OFFSET = IN 4125 ps VALID 4750 ps BEFORE "bclk";
 # # this was also supposed to be IN 4125 ps VALID 625 ps BEFORE "bclk", but
 # # the computation gives me -3.5ns slack on hold time, so...add 4750 ps to the hold again.
 # #5200 ps is the true limit
-OFFSET = OUT 5100 ps AFTER "bclk";
+# OFFSET = OUT 5100 ps AFTER "bclk";
 
 # NET "eim_d_t*" TIG;
 # INST "oddr2_eim0" IOB =FORCE;
@@ -67,20 +67,20 @@ OFFSET = OUT 5100 ps AFTER "bclk";
 ############################################################################
 ## Clock defines and constraints.
 ############################################################################
-# NET "clk3_2" TNM_NET = "clk3_2_tnm";
-# TIMESPEC TS_clk = PERIOD "clk3_2_tnm" 3.2 MHz;
+NET "clk50" TNM_NET = "clk50_tnm";
+TIMESPEC TS_clk = PERIOD "clk50_tnm" 50 MHz;
 
 NET "clk25" TNM_NET = "clk25_tnm";
 TIMESPEC TS_clk = PERIOD "clk25_tnm" 25 MHz;
 
-# NET "clk50" TNM_NET = "clk50_tnm";
-# TIMESPEC TS_clk = PERIOD "clk50_tnm" 50 MHz;
+NET "clk3_2" TNM_NET = "clk3_2_tnm";
+TIMESPEC TS_clk = PERIOD "clk3_2_tnm" 3.2 MHz;
 
-NET "bclk133" TNM_NET = "bclk133_tnm";
-TIMESPEC TS_bclk133 = PERIOD "bclk133_tnm" 133 MHz;
+# NET "bclk133" TNM_NET = "bclk133_tnm";
+# TIMESPEC TS_bclk133 = PERIOD "bclk133_tnm" 133 MHz;
 
-NET "bclk66" TNM_NET = "bclk66_tnm";
-TIMESPEC TS_bclk66 = PERIOD "bclk66_tnm" 66 MHz;
+# NET "bclk66" TNM_NET = "bclk66_tnm";
+# TIMESPEC TS_bclk66 = PERIOD "bclk66_tnm" 66 MHz;
 
 
 ############################################################################
@@ -196,6 +196,40 @@ NET "F_LVDS_P15" LOC = U10;
 NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
 NET "F_LVDS_P15" SLEW = SLOW;
 
+# Pins to the header where the LEDs on the Cryptech
+# Avalanche Noise Board (CT_AB) are connected.
+NET "CT_AB_LED[0]" LOC = K6;
+NET "CT_AB_LED[0]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[0]" SLEW = SLOW;
+
+NET "CT_AB_LED[1]" LOC = H4;
+NET "CT_AB_LED[1]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[1]" SLEW = SLOW;
+
+NET "CT_AB_LED[2]" LOC = H3;
+NET "CT_AB_LED[2]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[2]" SLEW = SLOW;
+
+NET "CT_AB_LED[3]" LOC = M1;
+NET "CT_AB_LED[3]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[3]" SLEW = SLOW;
+
+NET "CT_AB_LED[4]" LOC = L7;
+NET "CT_AB_LED[4]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[4]" SLEW = SLOW;
+
+NET "CT_AB_LED[5]" LOC = G1;
+NET "CT_AB_LED[5]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[5]" SLEW = SLOW;
+
+NET "CT_AB_LED[6]" LOC = T2;
+NET "CT_AB_LED[6]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[6]" SLEW = SLOW;
+
+NET "CT_AB_LED[7]" LOC = H7;
+NET "CT_AB_LED[7]" IOSTANDARD = LVCMOS33;
+NET "CT_AB_LED[7]" SLEW = SLOW;
+
 ### ======================================================================
 ### EOF novena_fpga.ucf
 ### ======================================================================
diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index 97ea400..7a5c897 100644
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -44,6 +44,8 @@ module novena_fpga(
 		   input wire           EIM_RW,
 		   input wire           EIM_WAIT,
 
+                   output wire [7 : 0]  CT_AB_LED,
+
 		   output wire          FPGA_LED2,
 
 		   output wire          F_LVDS_P15,
@@ -59,7 +61,11 @@ module novena_fpga(
   //----------------------------------------------------------------
   // Registers.
   //----------------------------------------------------------------
-  reg [23 : 0] counter_reg;
+  reg [23 : 0] counter_clk50_reg;
+  reg [23 : 0] counter_clk25_reg;
+  reg [23 : 0] counter_clk3_2_reg;
+  reg [23 : 0] counter_bclk133_reg;
+  reg [23 : 0] counter_bclk66_reg;
 
 
   //----------------------------------------------------------------
@@ -137,16 +143,48 @@ module novena_fpga(
 
 
   //----------------------------------------------------------------
-  // Heartbeat counter
-  //
-  // Should always run.
+  // Heartbeat counters. One for each clock.
+  // Hearthbeat for clk50 should always run on the FPGA_LED2.
   //----------------------------------------------------------------
+  always @(posedge clk50)
+    begin
+      counter_clk50_reg <= counter_clk50_reg + 1'b1;
+    end
+  assign FPGA_LED2    = counter_clk50_reg[23];
+  assign CT_AB_LED[0] = counter_clk50_reg[23];
+
+
   always @(posedge clk25)
     begin
-      counter_reg <= counter_reg + 1'b1;
+      counter_clk25_reg <= counter_clk25_reg + 1'b1;
+    end
+  assign CT_AB_LED[1] = counter_clk25_reg[23];
+
+
+  always @(posedge clk3_2)
+    begin
+      counter_clk3_2_reg <= counter_clk3_2_reg + 1'b1;
     end
+  assign CT_AB_LED[2] = counter_clk3_2_reg[23];
 
-  assign FPGA_LED2 = counter_reg[23];
+
+  assign CT_AB_LED[3] = 1'b0;
+  assign CT_AB_LED[4] = 1'b0;
+  assign CT_AB_LED[5] = 1'b0;
+
+
+  always @(posedge eim_bclk133)
+    begin
+      counter_bclk133_reg <= counter_bclk133_reg + 1'b1;
+    end
+  assign CT_AB_LED[6] = counter_bclk133_reg[23];
+
+
+  always @(posedge eim_bclk66)
+    begin
+      counter_bclk66_reg <= counter_bclk66_reg + 1'b1;
+    end
+  assign CT_AB_LED[7] = counter_bclk66_reg[23];
 
 endmodule