[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: (1) Adding constraints for 66 MHz EIM clock. (2) Fixed encoding to UNIX, noot dos.

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Thu Jan 22 14:45:03 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 4ff370a5061f8d59e022f5baea748523eacac5a5
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Jan 22 15:44:54 2015 +0100

    (1) Adding constraints for 66 MHz EIM clock. (2) Fixed encoding to UNIX, noot dos.
---
 src/constraints/novena_fpga.ucf | 399 ++++++++++++++++++++--------------------
 1 file changed, 201 insertions(+), 198 deletions(-)

diff --git a/src/constraints/novena_fpga.ucf b/src/constraints/novena_fpga.ucf
index 85e190b..6e1ece8 100755
--- a/src/constraints/novena_fpga.ucf
+++ b/src/constraints/novena_fpga.ucf
@@ -1,198 +1,201 @@
-### ======================================================================
-###
-### novena_fpga.ucf
-## ---------------
-### Constraint file for the Novena FPGA.
-### This design is heavily based on the Novena-SPI-Romulator by Bunnie:
-### https://github.com/bunnie/novena-spi-romulator
-###
-###
-### Authors: Andrew "bunnie" Huang, Joachim Strombergson
-### Copyright (c) 2013, Andrew "bunnie" Huang
-### The copyright holder licenses this file to you under the
-### Apache License, Version 2.0 (the "License"); you may not use this
-### file except in compliance with the License. You may obtain a copy
-### of the License at
-###
-###   http://www.apache.org/licenses/LICENSE-2.0
-###
-### Unless required by applicable law or agreed to in writing,
-### code distributed under the License is distributed on an
-### "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-### KIND, either express or implied.  See the License for the
-### specific language governing permissions and limitations
-### under the License.
-###
-### ======================================================================
-
-###  Autogenerated on 2013-May-10 01:38 by edifToUcf.py
-###  Extracting designator U800 from EDIF netlist novena-dvt.EDF
-
-### extended performance annotation
-CONFIG VCCAUX  = 3.3;
-# Valid values are 2.5 and 3.3
-CONFIG MCB_PERFORMANCE  = EXTENDED;
-
-# ### define setup/hold constraints for EIM
-OFFSET = IN 4125 ps VALID 4750 ps BEFORE "bclk";
-# # this was also supposed to be IN 4125 ps VALID 625 ps BEFORE "bclk", but
-# # the computation gives me -3.5ns slack on hold time, so...add 4750 ps to the hold again.
-# #5200 ps is the true limit
-OFFSET = OUT 5100 ps AFTER "bclk";
-
-# NET "eim_d_t*" TIG;
-# INST "oddr2_eim0" IOB =FORCE;
-# INST "oddr2_eim1" IOB =FORCE;
-# INST "oddr2_eim2" IOB =FORCE;
-# INST "oddr2_eim3" IOB =FORCE;
-# INST "oddr2_eim4" IOB =FORCE;
-# INST "oddr2_eim5" IOB =FORCE;
-# INST "oddr2_eim6" IOB =FORCE;
-# INST "oddr2_eim7" IOB =FORCE;
-# INST "oddr2_eim8" IOB =FORCE;
-# INST "oddr2_eim9" IOB =FORCE;
-# INST "oddr2_eimA" IOB =FORCE;
-# INST "oddr2_eimB" IOB =FORCE;
-# INST "oddr2_eimC" IOB =FORCE;
-# INST "oddr2_eimD" IOB =FORCE;
-# INST "oddr2_eimE" IOB =FORCE;
-# INST "oddr2_eimF" IOB =FORCE;
-
-# NET "reg_wo_40102/state[*]" TIG;
-# NET "reg_wo_40100/state[*]" TIG;
-# NET "reg_ro_41010/state[*]" TIG;
-# don't sweat the R/B signal, we have tons of margin on it
-
-
-############################################################################
-## Clock defines and constraints.
-############################################################################
-# NET "clk3_2" TNM_NET = "clk3_2_tnm";
-# TIMESPEC TS_clk = PERIOD "clk3_2_tnm" 3.2 MHz;
-
-NET "clk25" TNM_NET = "clk25_tnm";
-TIMESPEC TS_clk = PERIOD "clk25_tnm" 25 MHz;
-
-# NET "clk50" TNM_NET = "clk50_tnm";
-# TIMESPEC TS_clk = PERIOD "clk50_tnm" 50 MHz;
-
-NET "bclk" TNM_NET = "bclk_tnm";
-TIMESPEC TS_bclk = PERIOD "bclk_tnm" 133 MHz;
-
-
-############################################################################
-## I/O and pin assignments.
-############################################################################
-NET "APOPTOSIS" LOC = K1;
-NET "APOPTOSIS" IOSTANDARD = LVCMOS33;
-
-
-NET "CLK2_N" LOC = H1;
-NET "CLK2_N" IOSTANDARD = LVDS_33;
-NET "CLK2_N" DIFF_TERM = "TRUE";
-NET "CLK2_P" LOC = H2;
-NET "CLK2_P" IOSTANDARD = LVDS_33;
-NET "CLK2_P" DIFF_TERM = "TRUE";
-
-
-NET "ECSPI3_MISO" LOC = A3;
-NET "ECSPI3_MISO" IOSTANDARD = LVCMOS33;
-
-
-NET "EIM_BCLK" LOC = C9;
-NET "EIM_BCLK" IOSTANDARD = LVCMOS33;
-
-# NET "EIM_CS[0]" LOC = B11;
-# NET "EIM_CS[0]" IOSTANDARD = LVCMOS33;
-# NET "EIM_CS[1]" LOC = A15;
-# NET "EIM_CS[1]" IOSTANDARD = LVCMOS33;
-
-# NET "EIM_DA[0]" LOC = G9;
-# NET "EIM_DA[0]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[0]" SLEW = FAST;
-# NET "EIM_DA[1]" LOC = A10;
-# NET "EIM_DA[1]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[1]" SLEW = FAST;
-# NET "EIM_DA[2]" LOC = F9;
-# NET "EIM_DA[2]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[2]" SLEW = FAST;
-# NET "EIM_DA[3]" LOC = B9;
-# NET "EIM_DA[3]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[3]" SLEW = FAST;
-# NET "EIM_DA[4]" LOC = E13;
-# NET "EIM_DA[4]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[4]" SLEW = FAST;
-# NET "EIM_DA[5]" LOC = F13;
-# NET "EIM_DA[5]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[5]" SLEW = FAST;
-# NET "EIM_DA[6]" LOC = A9;
-# NET "EIM_DA[6]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[6]" SLEW = FAST;
-# NET "EIM_DA[7]" LOC = A8;
-# NET "EIM_DA[7]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[7]" SLEW = FAST;
-# NET "EIM_DA[8]" LOC = B8;
-# NET "EIM_DA[8]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[8]" SLEW = FAST;
-# NET "EIM_DA[9]" LOC = D8;
-# NET "EIM_DA[9]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[9]" SLEW = FAST;
-# NET "EIM_DA[10]" LOC = D11;
-# NET "EIM_DA[10]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[10]" SLEW = FAST;
-# NET "EIM_DA[11]" LOC = C8;
-# NET "EIM_DA[11]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[11]" SLEW = FAST;
-# NET "EIM_DA[12]" LOC = C7;
-# NET "EIM_DA[12]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[12]" SLEW = FAST;
-# NET "EIM_DA[13]" LOC = C11;
-# NET "EIM_DA[13]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[13]" SLEW = FAST;
-# NET "EIM_DA[14]" LOC = C4;
-# NET "EIM_DA[14]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[14]" SLEW = FAST;
-# NET "EIM_DA[15]" LOC = B6;
-# NET "EIM_DA[15]" IOSTANDARD = LVCMOS33;
-# NET "EIM_DA[15]" SLEW = FAST;
-
-# NET "EIM_A[16]" LOC = A11;
-# NET "EIM_A[16]" IOSTANDARD = LVCMOS33;
-# NET "EIM_A[17]" LOC = B12;
-# NET "EIM_A[17]" IOSTANDARD = LVCMOS33;
-# NET "EIM_A[18]" LOC = D14;
-# NET "EIM_A[18]" IOSTANDARD = LVCMOS33;
-
-# NET "EIM_LBA" LOC = B14;
-# NET "EIM_LBA" IOSTANDARD = LVCMOS33;
-# NET "EIM_OE" LOC = C10;
-# NET "EIM_OE" IOSTANDARD = LVCMOS33;
-# NET "EIM_RW" LOC = C14;
-# NET "EIM_RW" IOSTANDARD = LVCMOS33;
-# NET "EIM_WAIT" LOC = A7;
-# NET "EIM_WAIT" IOSTANDARD = LVCMOS33;
-
-
-NET "FPGA_LED2" LOC = A16;
-NET "FPGA_LED2" IOSTANDARD = LVCMOS33;
-
-
-NET "RESETBMCU" LOC = F1;
-NET "RESETBMCU" IOSTANDARD = LVCMOS33;
-
-
-NET "F_LVDS_N7" LOC = V7;
-NET "F_LVDS_N7" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_N7" SLEW = SLOW;
-NET "F_LVDS_P7" LOC = U7;
-NET "F_LVDS_P7" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_P7" SLEW = SLOW;
-
-
-NET "F_LVDS_P15" LOC = U10;
-NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_P15" SLEW = SLOW;
-
-### ======================================================================
-### EOF novena_fpga.ucf
-### ======================================================================
+### ======================================================================
+###
+### novena_fpga.ucf
+## ---------------
+### Constraint file for the Novena FPGA.
+### This design is heavily based on the Novena-SPI-Romulator by Bunnie:
+### https://github.com/bunnie/novena-spi-romulator
+###
+###
+### Authors: Andrew "bunnie" Huang, Joachim Strombergson
+### Copyright (c) 2013, Andrew "bunnie" Huang
+### The copyright holder licenses this file to you under the
+### Apache License, Version 2.0 (the "License"); you may not use this
+### file except in compliance with the License. You may obtain a copy
+### of the License at
+###
+###   http://www.apache.org/licenses/LICENSE-2.0
+###
+### Unless required by applicable law or agreed to in writing,
+### code distributed under the License is distributed on an
+### "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+### KIND, either express or implied.  See the License for the
+### specific language governing permissions and limitations
+### under the License.
+###
+### ======================================================================
+
+###  Autogenerated on 2013-May-10 01:38 by edifToUcf.py
+###  Extracting designator U800 from EDIF netlist novena-dvt.EDF
+
+### extended performance annotation
+CONFIG VCCAUX  = 3.3;
+# Valid values are 2.5 and 3.3
+CONFIG MCB_PERFORMANCE  = EXTENDED;
+
+# ### define setup/hold constraints for EIM
+OFFSET = IN 4125 ps VALID 4750 ps BEFORE "bclk";
+# # this was also supposed to be IN 4125 ps VALID 625 ps BEFORE "bclk", but
+# # the computation gives me -3.5ns slack on hold time, so...add 4750 ps to the hold again.
+# #5200 ps is the true limit
+OFFSET = OUT 5100 ps AFTER "bclk";
+
+# NET "eim_d_t*" TIG;
+# INST "oddr2_eim0" IOB =FORCE;
+# INST "oddr2_eim1" IOB =FORCE;
+# INST "oddr2_eim2" IOB =FORCE;
+# INST "oddr2_eim3" IOB =FORCE;
+# INST "oddr2_eim4" IOB =FORCE;
+# INST "oddr2_eim5" IOB =FORCE;
+# INST "oddr2_eim6" IOB =FORCE;
+# INST "oddr2_eim7" IOB =FORCE;
+# INST "oddr2_eim8" IOB =FORCE;
+# INST "oddr2_eim9" IOB =FORCE;
+# INST "oddr2_eimA" IOB =FORCE;
+# INST "oddr2_eimB" IOB =FORCE;
+# INST "oddr2_eimC" IOB =FORCE;
+# INST "oddr2_eimD" IOB =FORCE;
+# INST "oddr2_eimE" IOB =FORCE;
+# INST "oddr2_eimF" IOB =FORCE;
+
+# NET "reg_wo_40102/state[*]" TIG;
+# NET "reg_wo_40100/state[*]" TIG;
+# NET "reg_ro_41010/state[*]" TIG;
+# don't sweat the R/B signal, we have tons of margin on it
+
+
+############################################################################
+## Clock defines and constraints.
+############################################################################
+# NET "clk3_2" TNM_NET = "clk3_2_tnm";
+# TIMESPEC TS_clk = PERIOD "clk3_2_tnm" 3.2 MHz;
+
+NET "clk25" TNM_NET = "clk25_tnm";
+TIMESPEC TS_clk = PERIOD "clk25_tnm" 25 MHz;
+
+# NET "clk50" TNM_NET = "clk50_tnm";
+# TIMESPEC TS_clk = PERIOD "clk50_tnm" 50 MHz;
+
+NET "bclk133" TNM_NET = "bclk133_tnm";
+TIMESPEC TS_bclk133 = PERIOD "bclk133_tnm" 133 MHz;
+
+NET "bclk66" TNM_NET = "bclk66_tnm";
+TIMESPEC TS_bclk66 = PERIOD "bclk66_tnm" 66 MHz;
+
+
+############################################################################
+## I/O and pin assignments.
+############################################################################
+NET "APOPTOSIS" LOC = K1;
+NET "APOPTOSIS" IOSTANDARD = LVCMOS33;
+
+
+NET "CLK2_N" LOC = H1;
+NET "CLK2_N" IOSTANDARD = LVDS_33;
+NET "CLK2_N" DIFF_TERM = "TRUE";
+NET "CLK2_P" LOC = H2;
+NET "CLK2_P" IOSTANDARD = LVDS_33;
+NET "CLK2_P" DIFF_TERM = "TRUE";
+
+
+NET "ECSPI3_MISO" LOC = A3;
+NET "ECSPI3_MISO" IOSTANDARD = LVCMOS33;
+
+
+NET "EIM_BCLK" LOC = C9;
+NET "EIM_BCLK" IOSTANDARD = LVCMOS33;
+
+# NET "EIM_CS[0]" LOC = B11;
+# NET "EIM_CS[0]" IOSTANDARD = LVCMOS33;
+# NET "EIM_CS[1]" LOC = A15;
+# NET "EIM_CS[1]" IOSTANDARD = LVCMOS33;
+
+# NET "EIM_DA[0]" LOC = G9;
+# NET "EIM_DA[0]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[0]" SLEW = FAST;
+# NET "EIM_DA[1]" LOC = A10;
+# NET "EIM_DA[1]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[1]" SLEW = FAST;
+# NET "EIM_DA[2]" LOC = F9;
+# NET "EIM_DA[2]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[2]" SLEW = FAST;
+# NET "EIM_DA[3]" LOC = B9;
+# NET "EIM_DA[3]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[3]" SLEW = FAST;
+# NET "EIM_DA[4]" LOC = E13;
+# NET "EIM_DA[4]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[4]" SLEW = FAST;
+# NET "EIM_DA[5]" LOC = F13;
+# NET "EIM_DA[5]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[5]" SLEW = FAST;
+# NET "EIM_DA[6]" LOC = A9;
+# NET "EIM_DA[6]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[6]" SLEW = FAST;
+# NET "EIM_DA[7]" LOC = A8;
+# NET "EIM_DA[7]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[7]" SLEW = FAST;
+# NET "EIM_DA[8]" LOC = B8;
+# NET "EIM_DA[8]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[8]" SLEW = FAST;
+# NET "EIM_DA[9]" LOC = D8;
+# NET "EIM_DA[9]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[9]" SLEW = FAST;
+# NET "EIM_DA[10]" LOC = D11;
+# NET "EIM_DA[10]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[10]" SLEW = FAST;
+# NET "EIM_DA[11]" LOC = C8;
+# NET "EIM_DA[11]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[11]" SLEW = FAST;
+# NET "EIM_DA[12]" LOC = C7;
+# NET "EIM_DA[12]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[12]" SLEW = FAST;
+# NET "EIM_DA[13]" LOC = C11;
+# NET "EIM_DA[13]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[13]" SLEW = FAST;
+# NET "EIM_DA[14]" LOC = C4;
+# NET "EIM_DA[14]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[14]" SLEW = FAST;
+# NET "EIM_DA[15]" LOC = B6;
+# NET "EIM_DA[15]" IOSTANDARD = LVCMOS33;
+# NET "EIM_DA[15]" SLEW = FAST;
+
+# NET "EIM_A[16]" LOC = A11;
+# NET "EIM_A[16]" IOSTANDARD = LVCMOS33;
+# NET "EIM_A[17]" LOC = B12;
+# NET "EIM_A[17]" IOSTANDARD = LVCMOS33;
+# NET "EIM_A[18]" LOC = D14;
+# NET "EIM_A[18]" IOSTANDARD = LVCMOS33;
+
+# NET "EIM_LBA" LOC = B14;
+# NET "EIM_LBA" IOSTANDARD = LVCMOS33;
+# NET "EIM_OE" LOC = C10;
+# NET "EIM_OE" IOSTANDARD = LVCMOS33;
+# NET "EIM_RW" LOC = C14;
+# NET "EIM_RW" IOSTANDARD = LVCMOS33;
+# NET "EIM_WAIT" LOC = A7;
+# NET "EIM_WAIT" IOSTANDARD = LVCMOS33;
+
+
+NET "FPGA_LED2" LOC = A16;
+NET "FPGA_LED2" IOSTANDARD = LVCMOS33;
+
+
+NET "RESETBMCU" LOC = F1;
+NET "RESETBMCU" IOSTANDARD = LVCMOS33;
+
+
+NET "F_LVDS_N7" LOC = V7;
+NET "F_LVDS_N7" IOSTANDARD = LVCMOS33;
+NET "F_LVDS_N7" SLEW = SLOW;
+NET "F_LVDS_P7" LOC = U7;
+NET "F_LVDS_P7" IOSTANDARD = LVCMOS33;
+NET "F_LVDS_P7" SLEW = SLOW;
+
+
+NET "F_LVDS_P15" LOC = U10;
+NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
+NET "F_LVDS_P15" SLEW = SLOW;
+
+### ======================================================================
+### EOF novena_fpga.ucf
+### ======================================================================
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