[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: (1) Updating rtl to not have EIM clock with main clock and reset. (2) Changed name on clock and reset module. (3) Updated constraints to new set of main clocks. (4) Testing 25 MHz clock by driving the counter.
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Thu Jan 22 12:33:35 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.
commit b3dad44cb577a4ec34b22a7293ce8d674541fef7
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Thu Jan 22 13:33:27 2015 +0100
(1) Updating rtl to not have EIM clock with main clock and reset. (2) Changed name on clock and reset module. (3) Updated constraints to new set of main clocks. (4) Testing 25 MHz clock by driving the counter.
---
src/constraints/novena_fpga.ucf | 10 ++-
src/rtl/novena_fpga.v | 26 +++-----
src/rtl/novena_fpga_clk_rst.v | 83 +++++++++++++++++++++++
src/rtl/novena_fpga_clocks.v | 143 ----------------------------------------
4 files changed, 101 insertions(+), 161 deletions(-)
diff --git a/src/constraints/novena_fpga.ucf b/src/constraints/novena_fpga.ucf
index 66eb5bd..ceed775 100755
--- a/src/constraints/novena_fpga.ucf
+++ b/src/constraints/novena_fpga.ucf
@@ -67,8 +67,14 @@ CONFIG MCB_PERFORMANCE = EXTENDED;
############################################################################
## Clock defines and constraints.
############################################################################
-NET "clk50" TNM_NET = "clk_tnm";
-TIMESPEC TS_clk = PERIOD "clk_tnm" 50 MHz;
+# NET "clk3_2" TNM_NET = "clk3_2_tnm";
+# TIMESPEC TS_clk = PERIOD "clk3_2_tnm" 3.2 MHz;
+
+NET "clk25" TNM_NET = "clk25_tnm";
+TIMESPEC TS_clk = PERIOD "clk25_tnm" 25 MHz;
+
+# NET "clk50" TNM_NET = "clk50_tnm";
+# TIMESPEC TS_clk = PERIOD "clk50_tnm" 50 MHz;
# NET "bclk" TNM_NET = "bclk_tnm";
# TIMESPEC TS_bclk = PERIOD "bclk_tnm" 133 MHz;
diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index a73bc28..66324fc 100644
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -99,24 +99,18 @@ module novena_fpga(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
- novena_fpga_clocks clk_rst(
- .RESETBMCU(RESETBMCU),
+ novena_fpga_clk_rst clk_rst_inst(
+ .RESETBMCU(RESETBMCU),
- .CLK2_N(CLK2_N),
- .CLK2_P(CLK2_P),
+ .CLK2_N(CLK2_N),
+ .CLK2_P(CLK2_P),
- .EIM_BCLK(EIM_BCLK),
+ .reset(reset),
- .reset(reset),
-
- .clk50(clk50),
- .clk25(clk25),
- .clk3_2(clk3_2),
-
- .eim_bclk(bclk133),
- .eim_bclk_i(bclk133_i),
- .eim_bclk_o(bclk133_o)
- );
+ .clk50(clk50),
+ .clk25(clk25),
+ .clk3_2(clk3_2)
+ );
//----------------------------------------------------------------
@@ -124,7 +118,7 @@ module novena_fpga(
//
// Should always run.
//----------------------------------------------------------------
- always @(posedge clk50) begin
+ always @(posedge clk25) begin
counter_reg <= counter_reg + 1'b1;
end
diff --git a/src/rtl/novena_fpga_clk_rst.v b/src/rtl/novena_fpga_clk_rst.v
new file mode 100644
index 0000000..55acc56
--- /dev/null
+++ b/src/rtl/novena_fpga_clk_rst.v
@@ -0,0 +1,83 @@
+//======================================================================
+//
+// novena_fpga_clk_rst.v
+// ---------------------
+// Novena FPGA clock and reset implementation. This module accepts the
+// differential CLK2 clock generates related 50, 25 and 3.2 MHz clocks.
+// The module also implements the reset functionality.
+//
+// This design is heavily based on the Novena-SPI-Romulator by Bunnie:
+// https://github.com/bunnie/novena-spi-romulator
+//
+//
+// Authors: Andrew "bunnie" Huang, Joachim Strombergson
+// Copyright (c) 2013, Andrew "bunnie" Huang
+// The copyright holder licenses this file to you under the
+// Apache License, Version 2.0 (the "License"); you may not use this
+// file except in compliance with the License. You may obtain a copy
+// of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// code distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+//======================================================================
+
+module novena_fpga_clk_rst(
+ input wire RESETBMCU,
+
+ input wire CLK2_N,
+ input wire CLK2_P,
+
+ output wire reset,
+
+ output wire clk50,
+ output wire clk25,
+ output wire clk3_2
+ );
+
+
+ //----------------------------------------------------------------
+ // Reset macro.
+ //
+ // Syncrhonous, active low reset.
+ //----------------------------------------------------------------
+ sync_reset sync_reset_inst(
+ .glbl_reset(!RESETBMCU),
+ .clk(clk50),
+ .reset(reset)
+ );
+
+
+ //----------------------------------------------------------------
+ // 50 MHz, 25 MHz and 3.2MHz buffered clocks. Always available.
+ //----------------------------------------------------------------
+ wire clk;
+
+ IBUFGDS clkibufgds(
+ .I(CLK2_P),
+ .IB(CLK2_N),
+ .O(clk)
+ );
+
+
+ clk_dll clk_dll_inst(
+ .clk50in(clk),
+ .clk50(clk50),
+ .clk25(clk25),
+ .clk3p2(clk3_2),
+
+ .RESET(!RESETBMCU),
+ .LOCKED()
+ );
+
+endmodule // novena_fpga_clk_rst
+
+//======================================================================
+// EOF novena_fpga_clk_rst.v
+//======================================================================
diff --git a/src/rtl/novena_fpga_clocks.v b/src/rtl/novena_fpga_clocks.v
deleted file mode 100644
index 44e5d78..0000000
--- a/src/rtl/novena_fpga_clocks.v
+++ /dev/null
@@ -1,143 +0,0 @@
-//======================================================================
-//
-// novena_fpga_clocks.v
-// --------------------
-// Novena FPGA clock and reset implementation. This module accepts the
-// differential CLK2 clock and the EIM BCLK and connects them to
-// the clock trees as well as generating related 50 and 100 MHz clocks.
-//
-// This design is heavily based on the Novena-SPI-Romulator by Bunnie:
-// https://github.com/bunnie/novena-spi-romulator
-//
-//
-// Authors: Andrew "bunnie" Huang, Joachim Strombergson
-// Copyright (c) 2013, Andrew "bunnie" Huang
-// The copyright holder licenses this file to you under the
-// Apache License, Version 2.0 (the "License"); you may not use this
-// file except in compliance with the License. You may obtain a copy
-// of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing,
-// code distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations
-// under the License.
-//
-//======================================================================
-
-module novena_fpga_clocks(
- input wire RESETBMCU,
-
- input wire CLK2_N,
- input wire CLK2_P,
-
- input wire EIM_BCLK,
-
- output wire reset,
-
- // 50 MHz DLL clock for user logic.
- output wire clk50,
- output wire clk25,
- output wire clk3_2,
-
- // DLL synched EIM burst clock and
- // assoicated I/O clocks.
- // NOTE: doesn't run until first CPU access
- // to EIM; then free-runs at 133 MHz
- output wire eim_bclk,
- output wire eim_bclk_i,
- output wire eim_bclk_o
- );
-
-
- //----------------------------------------------------------------
- // Reset macro.
- //
- // Active low reset.
- //----------------------------------------------------------------
- sync_reset sync_reset_inst(
- .glbl_reset(!RESETBMCU),
- .clk(clk50),
- .reset(reset)
- );
-
-
- //----------------------------------------------------------------
- // EIM Burst clock including generation of I/O clocks etc.
- //----------------------------------------------------------------
-// wire bclk_dll;
-// wire bclk_div2_dll;
-// wire bclk_div4_dll;
-// wire bclk_locked;
-// wire bclk_early;
-// wire bclk_int_in;
-// wire bclk_io_in;
-// wire bclk_int_in;
-// wire bclk_io_in;
-// wire i_reset, i_locked;
-// wire o_reset, o_locked;
-// wire bclk_i, bclk_o;
-// wire i_fbk_out, i_fbk_in;
-// wire o_fbk_out, o_fbk_in;
-//
-// IBUFG clkibufg(.I(EIM_BCLK), .O(bclk));
-//
-// BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in));
-//
-// bclk_dll bclk_dll_mod(.clk133in(bclk_int_in), .clk133(bclk_dll),
-// .RESET(reset), .LOCKED(bclk_locked));
-//
-//
-// dcm_delay bclk_i_dll(.clk133(bclk_int_in), .clk133out(bclk_i),
-// .CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
-// .RESET(i_reset), .LOCKED(i_locked));
-//
-// dcm_delay bclk_o_dll(.clk133(bclk_int_in), .clk133out(bclk_o),
-// .CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
-// .RESET(o_reset), .LOCKED(o_locked));
-//
-// // lock it to the input path
-// BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
-//
-// assign i_fbk_in = bclk_i;
-//
-// assign eim_bclk = bclk_dll;
-// assign eim_bclk_i = bclk_i;
-// assign eim_bclk_o = bclk_o;
-
- assign eim_bclk = 1'b0;
- assign eim_bclk_i = 1'b0;
- assign eim_bclk_o = 1'b0;
-
-
- //----------------------------------------------------------------
- // 50 MHz, 25 MHz and 3.2MHz buffered clocks. Always available.
- //----------------------------------------------------------------
- wire clk;
- wire dll_locked;
-
- IBUFGDS clkibufgds(
- .I(CLK2_P),
- .IB(CLK2_N),
- .O(clk)
- );
-
-
- clk_dll clk_dll_inst(
- .clk50in(clk),
- .clk50(clk50),
- .clk25(clk25),
- .clk3p2(clk3_2),
-
- .RESET(!RESETBMCU),
- .LOCKED(dll_locked)
- );
-
-endmodule // novena_fpga_clocks
-
-//======================================================================
-// EOF novena_fpga_clocks.v
-//======================================================================
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