[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: Adding dll instance to generate locked 50, 25 and 3.2 MHz clocks.

[git at cryptech.is]

This is an automated email from the git hooks/post-receive script.

joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 7af7164799840eba80a0e30aa542036791a606ca
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed Jan 21 17:58:13 2015 +0100

    Adding dll instance to generate locked 50, 25 and 3.2 MHz clocks.
---
 src/rtl/novena_fpga_clocks.v | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/src/rtl/novena_fpga_clocks.v b/src/rtl/novena_fpga_clocks.v
index 8d71eae..44e5d78 100644
--- a/src/rtl/novena_fpga_clocks.v
+++ b/src/rtl/novena_fpga_clocks.v
@@ -40,6 +40,8 @@ module novena_fpga_clocks(
 
                           // 50 MHz DLL clock for user logic.
                           output wire clk50,
+                          output wire clk25,
+                          output wire clk3_2,
 
                           // DLL synched EIM burst clock and
                           // assoicated I/O clocks.
@@ -56,7 +58,11 @@ module novena_fpga_clocks(
   //
   // Active low reset.
   //----------------------------------------------------------------
-  sync_reset sync_reset_inst(.glbl_reset(!RESETBMCU), .clk(clk), .reset(reset));
+  sync_reset sync_reset_inst(
+                             .glbl_reset(!RESETBMCU),
+                             .clk(clk50),
+                             .reset(reset)
+                            );
 
 
   //----------------------------------------------------------------
@@ -108,12 +114,27 @@ module novena_fpga_clocks(
 
 
   //----------------------------------------------------------------
-  // 50 MHz general clock. Always available.
-  //
-  // Should be DLL locked also.
+  // 50 MHz, 25 MHz and 3.2MHz buffered clocks. Always available.
   //----------------------------------------------------------------
-  // IOBUFs as required by design
-  IBUFGDS clkibufgds(.I(CLK2_P), .IB(CLK2_N), .O(clk50));
+  wire clk;
+  wire dll_locked;
+
+  IBUFGDS clkibufgds(
+                     .I(CLK2_P),
+                     .IB(CLK2_N),
+                     .O(clk)
+                     );
+
+
+  clk_dll clk_dll_inst(
+                       .clk50in(clk),
+                       .clk50(clk50),
+                       .clk25(clk25),
+                       .clk3p2(clk3_2),
+
+                       .RESET(!RESETBMCU),
+                       .LOCKED(dll_locked)
+                      );
 
 endmodule // novena_fpga_clocks