[Cryptech-Commits] [user/js/test/novena_eim_base] 01/01: Commented out the EIM interface. Now what is left should be clock and reset handling for heartbeat.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit a0a39d389ef0da78c225d4fb551b8ad5971595e6
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed Jan 21 13:50:16 2015 +0100

    Commented out the EIM interface. Now what is left should be clock and reset handling for heartbeat.
---
 src/rtl/novena_fpga.v | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index 593a9a1..1f3b9a1 100644
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -35,21 +35,20 @@ module novena_fpga(
 		   input wire          CLK2_N,
 		   input wire          CLK2_P,
 
-		   input wire          EIM_BCLK,
-		   input wire [1  : 0] EIM_CS,
-		   inout wire [15 : 0] EIM_DA,
-		   input wire [18:16]  EIM_A,
-		   input wire          EIM_LBA,
-		   input wire          EIM_OE,
-		   input wire          EIM_RW,
-		   input wire          EIM_WAIT,
+//		   input wire          EIM_BCLK,
+//		   input wire [1  : 0] EIM_CS,
+//		   inout wire [15 : 0] EIM_DA,
+//		   input wire [18:16]  EIM_A,
+//		   input wire          EIM_LBA,
+//		   input wire          EIM_OE,
+//		   input wire          EIM_RW,
+//		   input wire          EIM_WAIT,
+
+		   output wire         FPGA_LED2,
 
 		   output wire         F_LVDS_P15,
 		   output wire         F_LVDS_N7,
 		   output wire         F_LVDS_P7,
-
-		   output wire         FPGA_LED2,
-
 		   output wire         ECSPI3_MISO,
 		   output wire         APOPTOSIS
 	          );