[Cryptech-Commits] [user/js/test/novena_eim_base] 03/04: Removed more SPI macros and code. Moving EIM stuff to the bottom.
git at cryptech.is
git at cryptech.is
Wed Jan 21 12:28:41 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.
commit c6189d3e41a623fc9ddabb51c574869658fc27b4
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Wed Jan 21 13:26:19 2015 +0100
Removed more SPI macros and code. Moving EIM stuff to the bottom.
---
src/rtl/novena_fpga.v | 263 ++++++++++++--------------------------------------
1 file changed, 60 insertions(+), 203 deletions(-)
diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index 57e1a42..ce8dfcd 100755
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -86,7 +86,7 @@ module novena_fpga(
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
-
+o
//----------------------------------------------------------------
// Wires.
@@ -208,21 +208,6 @@ module novena_fpga(
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable
.reg_d( r40002wo[15:0] ) );
- wire [15:0] romulator_ctl;
- wire emulate;
- wire spi_uk_rd_en;
- wire spi_uk_rst;
- wire spi_out_rd_en;
- wire spi_out_rst;
- wire spi_adr_rd_en;
- wire spi_adr_rst;
- assign emulate = romulator_ctl[0]; // 1
- assign spi_uk_rd_en = romulator_ctl[1]; // 2
- assign spi_uk_rst = romulator_ctl[2]; // 4
- assign spi_adr_rd_en = romulator_ctl[3]; // 8
- assign spi_adr_rst = romulator_ctl[4]; // 10
- assign spi_out_rd_en = romulator_ctl[5]; // 20
- assign spi_out_rst = romulator_ctl[6]; // 40
reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r),
@@ -347,127 +332,65 @@ module novena_fpga(
eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
end;
- wire [15:0] spi_eeprom_rbk;
- wire [7:0] spi_uk_cmd;
- wire spi_uk_cmd_updated;
-
- wire spiclk_i;
- wire spiclk;
-
- IBUFG spi_clkibufg( .I(F_LVDS_CK_P0), .O(spiclk_i));
- BUFG spi_clkbufg( .I(spiclk_i), .O(spiclk) );
-
- wire [23:0] spi_adr;
- wire spi_adr_updated;
-
- wire [7:0] spi_byte;
- wire spi_byte_updated;
-
- wire [7:0] spi_obyte;
- wire spi_obyte_updated;
-
- wire [11:0] spi_uk_rd_data_count;
- wire spi_uk_empty;
- wire spi_uk_overflow;
- wire spi_uk_full;
- wire [7:0] spi_uk_dout;
- wire spi_uk_rd_en_pulse;
-
- rising_edge spi_re( .clk(bclk_dll),
- .level(spi_uk_rd_en),
- .pulse(spi_uk_rd_en_pulse)
- );
-
- assign romulator_stat[7:0] = spi_uk_dout[7:0];
- assign romulator_stat[8] = spi_uk_empty;
- assign romulator_stat[9] = spi_uk_full;
- assign romulator_stat[10] = spi_uk_overflow;
- assign romulator_count[11:0] = spi_uk_rd_data_count[11:0];
-
- uk_fifo spi_uk (
- .rst(spi_uk_rst), // input rst
-// .wr_clk(spiclk), // input wr_clk
- .wr_clk(!spiclk), // input wr_clk // invert for monitoring
-
-// .din(spi_uk_cmd), // input [7 : 0] din
-// .wr_en(spi_uk_cmd_updated), // input wr_en
- .din(spi_byte),
- .wr_en(spi_byte_updated),
-
- .rd_clk(bclk_dll), // input rd_clk
- .rd_en(spi_uk_rd_en_pulse), // input rd_en
- .dout(spi_uk_dout), // output [7 : 0] dout
- .full(spi_uk_full), // output full
- .overflow(spi_uk_overflow), // output overflow
- .empty(spi_uk_empty), // output empty
- .rd_data_count(spi_uk_rd_data_count) // output [11 : 0] rd_data_count
- );
-
- wire [11:0] spi_out_rd_data_count;
- wire spi_out_empty;
- wire spi_out_overflow;
- wire spi_out_full;
- wire [7:0] spi_out_dout;
- wire spi_out_rd_en_pulse;
-
- rising_edge spi_out_re( .clk(bclk_dll),
- .level(spi_out_rd_en),
- .pulse(spi_out_rd_en_pulse)
- );
-
- assign romulator_out_stat[7:0] = spi_out_dout[7:0];
- assign romulator_out_stat[8] = spi_out_empty;
- assign romulator_out_stat[9] = spi_out_full;
- assign romulator_out_stat[10] = spi_out_overflow;
- assign romulator_out_count[11:0] = spi_out_rd_data_count[11:0];
-
- uk_fifo spi_out (
- .rst(spi_out_rst), // input rst
- .wr_clk(!spiclk), // input wr_clk
- // invert from negedge sampling of sdout
-
- .din(spi_obyte),
- .wr_en(spi_obyte_updated),
-
- .rd_clk(bclk_dll), // input rd_clk
- .rd_en(spi_out_rd_en_pulse), // input rd_en
- .dout(spi_out_dout), // output [7 : 0] dout
- .full(spi_out_full), // output full
- .overflow(spi_out_overflow), // output overflow
- .empty(spi_out_empty), // output empty
- .rd_data_count(spi_out_rd_data_count) // output [11 : 0] rd_data_count
- );
-
- wire spi_adr_rd_en_pulse;
- wire [23:0] spi_adr_dout;
- wire spi_adr_full;
- wire spi_adr_overflow;
- wire spi_adr_empty;
- wire [13:0] spi_adr_rd_data_count;
- assign romulator_adr_count[13:0] = spi_adr_rd_data_count[13:0];
- assign romulator_adr_stat[8] = spi_adr_empty;
- assign romulator_adr_stat[9] = spi_adr_full;
- assign romulator_adr_stat[10] = spi_adr_overflow;
-
- assign romulator_adr_dout[23:0] = spi_adr_dout[23:0];
-
- rising_edge spi_adr_re( .clk(bclk_dll),
- .level(spi_adr_rd_en),
- .pulse(spi_adr_rd_en_pulse)
- );
- nandadr_fifo spi_adr_fifo (
- .rst(spi_adr_rst), // input rst
- .wr_clk(spiclk), // input wr_clk
- .rd_clk(bclk_dll), // input rd_clk
- .din({6'b0,spi_adr[23:0]}), // input [29 : 0] din
- .wr_en(spi_adr_updated), // input wr_en
- .rd_en(spi_adr_rd_en_pulse), // input rd_en
- .dout(spi_adr_dout[23:0]), // output [29 : 0] dout
- .full(spi_adr_full), // output full
- .overflow(spi_adr_overflow), // output overflow
- .empty(spi_adr_empty), // output empty
- .rd_data_count(spi_adr_rd_data_count) // output [13 : 0] rd_data_count
- );
+
+ //----------------------------------------------------------------
+ // Heartbeat counter
+ //
+ // Should always run.
+ //----------------------------------------------------------------
+ always @(posedge clk50) begin
+ counter <= counter + 1;
+ end
+ assign FPGA_LED2 = counter[23];
+
+
+ //----------------------------------------------------------------
+ // EIM stuff to be moved.
+ //----------------------------------------------------------------
+ reg [15:0] eim_d_t;
+ reg eim_lba_reg;
+ reg eim_oe_reg;
+
+ always @(posedge bclk_i) begin
+ eim_lba_reg <= EIM_LBA;
+ eim_oe_reg <= EIM_OE;
+ end
+
+ always @(posedge bclk_o) begin
+ eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 2] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 3] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 4] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 5] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 6] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 7] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 8] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[ 9] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[10] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[11] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[12] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[13] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[14] = eim_oe_reg | !eim_lba_reg;
+ eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
+ end
+
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
//////////////
// Output pipeline registers -- explicit instantiation as their LOCs are controlled in the UCF.
@@ -540,72 +463,6 @@ module novena_fpga(
.Q( eim_dout[15] ),
.CE( 1'b1 ), .S(1'b0) );
-
- //////////////
- /// "heartbeat" counter
- //////////////
- always @(posedge clk) begin
- counter <= counter + 1;
- end
-
- assign FPGA_LED2 = counter[23];
-
- //////////////
- // IOBUFs as required by design
- //////////////
- IBUFGDS clkibufgds( .I(CLK2_P), .IB(CLK2_N), .O(clk) );
-
- reg [15:0] eim_d_t;
- reg eim_lba_reg;
- reg eim_oe_reg;
-
- always @(posedge bclk_i) begin
- eim_lba_reg <= EIM_LBA;
- eim_oe_reg <= EIM_OE;
- end
-
- always @(posedge bclk_o) begin
- eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 2] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 3] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 4] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 5] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 6] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 7] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 8] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[ 9] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[10] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[11] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[12] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[13] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[14] = eim_oe_reg | !eim_lba_reg;
- eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
- end
-
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
-
- //////////////
- // DDR3 interface macro
- //////////////
-
- wire c1_clk0, c1_rst0;
-
endmodule
//======================================================================
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