[Cryptech-Commits] [user/js/test/novena_eim_base] 01/04: Adding intial version of clock and reset module for the novena base.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 43d57cd16b8aa55b73a9cb134489e7bbaa2bd02e
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed Jan 21 13:19:38 2015 +0100

    Adding intial version of clock and reset module for the novena base.
---
 src/rtl/novena_fpga_clocks.v | 115 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/src/rtl/novena_fpga_clocks.v b/src/rtl/novena_fpga_clocks.v
new file mode 100644
index 0000000..2210476
--- /dev/null
+++ b/src/rtl/novena_fpga_clocks.v
@@ -0,0 +1,115 @@
+//======================================================================
+//
+// novena_fpga_clocks.v
+// --------------------
+// Novena FPGA clock and reset implementation. This module accepts the
+// differential CLK2 clock and the EIM BCLK and connects them to
+// the clock trees as well as generating related 50 and 100 MHz clocks.
+//
+// This design is heavily based on the Novena-SPI-Romulator by Bunnie:
+// https://github.com/bunnie/novena-spi-romulator
+//
+//
+// Authors: Andrew "bunnie" Huang, Joachim Strombergson
+// Copyright (c) 2013, Andrew "bunnie" Huang
+// The copyright holder licenses this file to you under the
+// Apache License, Version 2.0 (the "License"); you may not use this
+// file except in compliance with the License. You may obtain a copy
+// of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// code distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+//======================================================================
+
+module novena_fpga_clocks(
+		          input wire  RESETBMCU,
+
+		          input wire  CLK2_N,
+		          input wire  CLK2_P,
+
+		          input wire  EIM_BCLK,
+
+                          output wire reset,
+
+                          // 50 MHz DLL clock for user logic.
+                          output wire clk50,
+
+                          // DLL synched EIM burst clock and
+                          // assoicated I/O clocks.
+                          // NOTE: doesn't run until first CPU access
+                          // to EIM; then free-runs at 133 MHz
+                          output wire bclk,
+                          output wire bclk_i,
+                          output wire bclk_o
+	                 );
+
+
+  //----------------------------------------------------------------
+  // Reset macro.
+  //
+  // Active low reset.
+  //----------------------------------------------------------------
+  sync_reset master_res_sync(.glbl_reset(!RESETBMCU), .clk(clk), .reset(reset));
+
+
+  //----------------------------------------------------------------
+  // EIM Burst clock including generation of I/O clocks etc.
+  // We need
+  //----------------------------------------------------------------
+  wire bclk_dll;
+  wire bclk_div2_dll;
+  wire bclk_div4_dll;
+  wire bclk_locked;
+  wire bclk_early;
+  wire bclk_int_in;
+  wire bclk_io_in;
+  wire bclk_int_in;
+  wire bclk_io_in;
+  wire i_reset, i_locked;
+  wire o_reset, o_locked;
+  wire bclk_i, bclk_o;
+  wire i_fbk_out, i_fbk_in;
+  wire o_fbk_out, o_fbk_in;
+
+  IBUFG clkibufg(.I(EIM_BCLK), .O(bclk));
+
+  BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in));
+
+  bclk_dll bclk_dll_mod(.clk133in(bclk_int_in), .clk133(bclk_dll),
+			.RESET(reset), .LOCKED(bclk_locked));
+
+
+   dcm_delay bclk_i_dll(.clk133(bclk_int_in), .clk133out(bclk_i),
+			.CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
+			.RESET(i_reset), .LOCKED(i_locked));
+
+   dcm_delay bclk_o_dll(.clk133(bclk_int_in), .clk133out(bclk_o),
+			.CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
+			.RESET(o_reset), .LOCKED(o_locked));
+
+   // lock it to the input path
+   BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
+
+   assign i_fbk_in = bclk_i;
+
+
+  //----------------------------------------------------------------
+  // 50 MHz general clock. Always available.
+  //----------------------------------------------------------------
+  //////////////
+  // IOBUFs as required by design
+  //////////////
+  IBUFGDS clkibufgds(.I(CLK2_P), .IB(CLK2_N), .O(clk50));
+
+endmodule // novena_fpga_eim
+
+//======================================================================
+// EOF novena_fpga_eim.v
+//======================================================================