[Cryptech-Commits] [user/js/test/novena_eim_base] 02/02: Cleaned up the interface to only keep ports we need right now. Kept a few output ports that might be important for the rest of the Novena.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/test/novena_eim_base.

commit 72585b7c167d155552ca4014625abb395a28a751
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed Jan 21 11:22:33 2015 +0100

    Cleaned up the interface to only keep ports we need right now. Kept a few output ports that might be important for the rest of the Novena.
---
 src/rtl/novena_fpga.v | 145 ++++++++++++--------------------------------------
 1 file changed, 35 insertions(+), 110 deletions(-)

diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index f99fe39..f6482b4 100755
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -26,75 +26,28 @@
 //======================================================================
 
 module novena_fpga(
-		   input wire AUD6_TFS,
-		   input wire AUD6_TXC,
-		   input wire AUD6_TXD,
-		   input wire AUD_MCLK,
-		   input wire AUD_MIC_CLK,
-		   input wire AUD_MIC_DAT,
-
-		   input wire BATT_NRST,
-		   input wire BATT_REFLASH_ALRT,
-
-		   input wire CLK2_N,
-		   input wire CLK2_P,
-
-		   input wire DDC_SCL,
-		   input wire DDC_SDA,
-
-		   output wire ECSPI3_MISO,
-		   input wire ECSPI3_MOSI,
-		   input wire ECSPI3_RDY,
-		   input wire ECSPI3_SCLK,
-		   input wire ECSPI3_SS2,
-
-		   input wire EIM_BCLK,
-		   input wire [1:0] EIM_CS,
-		   inout wire [15:0] EIM_DA,
-		   input wire [18:16] EIM_A,
-		   input wire EIM_LBA,
-		   input wire EIM_OE,
-		   input wire EIM_RW,
-		   input wire EIM_WAIT,
-
-
-		   input wire FPGA_LSPI_CLK,
-		   input wire FPGA_LSPI_CS,
-		   input wire FPGA_LSPI_HOLD,
-		   input wire FPGA_LSPI_MISO,
-		   input wire FPGA_LSPI_MOSI,
-		   input wire FPGA_LSPI_WP,
-
-		   input wire I2C3_SCL,
-		   input wire I2C3_SDA,
-
-		   input wire SMB_SCL,
-		   input wire SMB_SDA,
-
-		   input wire UART4_CTS,
-		   input wire UART4_RTS,
-		   input wire UART4_RXD,
-		   input wire UART4_TXD,
-
-		   // input wire UIM_CLK,
-		   // input wire UIM_DATA,
-		   // input wire UIM_PWR,
-		   // input wire UIM_PWRON,
-		   // input wire UIM_RESET,
-
-		   input wire  F_LVDS_CK_P0, // sck
-		   input wire  F_LVDS_CK_N0, // si
-		   input wire  F_DX18, // cs input
-		   output wire F_LVDS_P11,  // so
-		   output wire F_LVDS_P15,  // cs output
-
-		   output wire F_LVDS_N7, // drivers
-		   output wire F_LVDS_P7,
-
-		   input wire RESETBMCU
-
-		   output wire FPGA_LED2,
-		   output wire APOPTOSIS
+		   input wire          RESETBMCU,
+
+		   input wire          CLK2_N,
+		   input wire          CLK2_P,
+
+		   input wire          EIM_BCLK,
+		   input wire [1  : 0] EIM_CS,
+		   inout wire [15 : 0] EIM_DA,
+		   input wire [18:16]  EIM_A,
+		   input wire          EIM_LBA,
+		   input wire          EIM_OE,
+		   input wire          EIM_RW,
+		   input wire          EIM_WAIT,
+
+		   output wire         F_LVDS_P15,
+		   output wire         F_LVDS_N7,
+		   output wire         F_LVDS_P7,
+
+		   output wire         FPGA_LED2,
+
+		   output wire         ECSPI3_MISO,
+		   output wire         APOPTOSIS
 	          );
 
 
@@ -110,7 +63,20 @@ module novena_fpga(
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
+  //
+  // Tie downs etc to be compatible with the rest of the
+  // Novena board.
   //----------------------------------------------------------------
+  // make apoptosis inactive, tigh high to force reboot on config
+  assign APOPTOSIS   = 1'b0;
+
+  // SPI interface outputs. We drive them low for now.
+  assign ECSPI3_MISO = 1'b0;
+  assign F_LVDS_P15  = 1'b0;
+  // drives so when low -- set to 1 for bypass mode
+  assign F_LVDS_N7 = !emulate_r;
+  // drives cs when low
+  assign F_LVDS_P7 = 1'b0;
 
 
   //----------------------------------------------------------------
@@ -140,14 +106,10 @@ module novena_fpga(
       emulate_r <= emulate;
    end
 
-   assign F_LVDS_N7 = !emulate_r; // drives so when low -- set to 1 for bypass mode
-   assign F_LVDS_P7 = 1'b0; // drives cs when low
 
    // P15 is cs output to SPINOR
-   assign F_LVDS_P15 = emulate_r ? 1'b1 : F_DX18;
 //   assign F_LVDS_P15 = F_DX18; // set this for bypass mode
 //   assign F_LVDS_P15 = 1'b1; // set to 1 to disable SPINOR during emulation
-//   assign F_LVDS_P11 = 1'bz;
 
 
    ////////////////////////////////////
@@ -400,37 +362,6 @@ module novena_fpga(
    wire [7:0] 	      spi_obyte;
    wire 	      spi_obyte_updated;
 
-   spi_eeprom spi_eeprom(
-			 .sdout(F_LVDS_P11),
-			 .sdin(F_LVDS_CK_N0),
-			 .scs(F_DX18),
-			 .sclk(spiclk),
-			 .swp(1'b1),
-			 .shold(1'b1),
-
-			 .eim_clk(bclk_i),
-			 .bus_a(bus_addr_r),
-			 .bus_d(din_r),
-			 .we(!cs0_r && !rw_r),
-			 .re(!cs0_r && rw_r),
-			 .reg_d(spi_eeprom_rbk),
-			 .rbk_d(ro_d),
-
-			 .spi_uk_cmd(spi_uk_cmd),  // bitbucket for unknown commands
-			 .spi_uk_cmd_updated(spi_uk_cmd_updated),
-
-			 .spi_byte(spi_byte),
-			 .spi_byte_updated(spi_byte_updated),
-
-			 .spi_obyte(spi_obyte),
-			 .spi_obyte_updated(spi_obyte_updated),
-
-			 .spi_adr(spi_adr),
-			 .spi_adr_updated(spi_adr_updated),
-
-			 .reset(reset)
-			 );
-
    wire [11:0] 	      spi_uk_rd_data_count;
    wire 	      spi_uk_empty;
    wire 	      spi_uk_overflow;
@@ -680,12 +611,6 @@ module novena_fpga(
 			    .LOCKED(ddr3_dll_locked)
 			    );
 
-   //////////////
-   // tie downs (unused signals as of this rev of design)
-   //////////////
-   assign APOPTOSIS = 1'b0; // make apoptosis inactive, tigh high to force reboot on config
-   assign ECSPI3_MISO = 1'b0;
-
 endmodule
 
 //======================================================================