[Cryptech-Commits] [user/paul/core] 01/01: 'toolruns' variant of core reorganization
git at cryptech.is
git at cryptech.is
Thu Feb 26 18:50:45 UTC 2015
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch toolruns
in repository user/paul/core.
commit 01c1bb0d49b631e18273ed35b78db01ff34bb5fe
Author: Paul Selkirk <paul at psgd.org>
Date: Thu Feb 26 13:50:13 2015 -0500
'toolruns' variant of core reorganization
- All verilog top-level files and build goop are now under their
respective communication channel cores (uart, i2c, eim).
- Add missing uart core, with its quartus build files.
- Generic comm_regs module, implemented by each comm channel.
- But passing configs from uart_regs to uart_core doesn't work. :(
---
core_selector/src/rtl/core_selector.v | 6 +-
core_selector/src/rtl/hash_selector.v | 2 +-
diff | 682 ++++++++++++++
eim/src/rtl/eim_regs.v | 128 +++
{novena => eim}/src/sw/Makefile | 0
{novena => eim}/src/sw/hash_tester_eim.c | 22 +
{novena => eim}/src/sw/novena-eim.c | 0
{novena => eim}/src/sw/novena-eim.h | 0
.../toolruns/xilinx/novena}/build/.gitignore | 0
eim/toolruns/xilinx/novena/build/Makefile | 38 +
.../toolruns/xilinx/novena}/build/xilinx.mk | 0
.../toolruns/xilinx/novena}/build/xilinx.opt | 0
.../xilinx/novena/iseconfig}/novena_reorg_eim.xise | 0
.../xilinx/novena}/rtl/ipcore/_xmsgs/cg.xmsgs | 0
.../novena}/rtl/ipcore/_xmsgs/pn_parser.xmsgs | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.asy | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.gise | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.ncf | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.sym | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.ucf | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.v | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.veo | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.xco | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.xdc | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm.xise | 0
.../rtl/ipcore/clkmgr_dcm}/clk_wiz_v3_6_readme.txt | 0
.../ipcore/clkmgr_dcm/doc}/clk_wiz_v3_6_readme.txt | 0
.../ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html | 0
.../rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf | Bin
.../clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf | 0
.../clkmgr_dcm/example_design/clkmgr_dcm_exdes.v | 0
.../clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc | 0
.../rtl/ipcore/clkmgr_dcm/implement/implement.bat | 0
.../rtl/ipcore/clkmgr_dcm/implement/implement.sh | 0
.../ipcore/clkmgr_dcm/implement/planAhead_ise.bat | 0
.../ipcore/clkmgr_dcm/implement/planAhead_ise.sh | 0
.../ipcore/clkmgr_dcm/implement/planAhead_ise.tcl | 0
.../ipcore/clkmgr_dcm/implement/planAhead_rdn.bat | 0
.../ipcore/clkmgr_dcm/implement/planAhead_rdn.sh | 0
.../ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl | 0
.../rtl/ipcore/clkmgr_dcm/implement/xst.prj | 0
.../rtl/ipcore/clkmgr_dcm/implement/xst.scr | 0
.../ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v | 0
.../clkmgr_dcm/simulation/functional/simcmds.tcl | 0
.../simulation/functional/simulate_isim.bat | 0
.../simulation/functional/simulate_isim.sh | 0
.../simulation/functional/simulate_mti.bat | 0
.../simulation/functional/simulate_mti.do | 0
.../simulation/functional/simulate_mti.sh | 0
.../simulation/functional/simulate_ncsim.sh | 0
.../simulation/functional/simulate_vcs.sh | 0
.../simulation/functional/ucli_commands.key | 0
.../simulation/functional/vcs_session.tcl | 0
.../clkmgr_dcm/simulation/functional/wave.do | 0
.../clkmgr_dcm/simulation/functional/wave.sv | 0
.../clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v | 0
.../clkmgr_dcm/simulation/timing/sdf_cmd_file | 0
.../clkmgr_dcm/simulation/timing/simcmds.tcl | 0
.../clkmgr_dcm/simulation/timing/simulate_isim.sh | 0
.../clkmgr_dcm/simulation/timing/simulate_mti.bat | 0
.../clkmgr_dcm/simulation/timing/simulate_mti.do | 0
.../clkmgr_dcm/simulation/timing/simulate_mti.sh | 0
.../clkmgr_dcm/simulation/timing/simulate_ncsim.sh | 0
.../clkmgr_dcm/simulation/timing/simulate_vcs.sh | 0
.../clkmgr_dcm/simulation/timing/ucli_commands.key | 0
.../clkmgr_dcm/simulation/timing/vcs_session.tcl | 0
.../ipcore/clkmgr_dcm/simulation/timing/wave.do | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm_flist.txt | 0
.../xilinx/novena}/rtl/ipcore/clkmgr_dcm_xmdf.tcl | 0
.../toolruns/xilinx/novena}/rtl/ipcore/coregen.cgp | 0
.../novena}/rtl/ipcore/create_clkmgr_dcm.tcl | 0
.../xilinx/novena}/rtl/ipcore/edit_clkmgr_dcm.tcl | 0
.../toolruns/xilinx/novena}/rtl/novena_clkmgr.v | 0
.../toolruns/xilinx/novena}/rtl/novena_eim.v | 0
.../toolruns/xilinx/novena}/ucf/novena_eim.ucf | 0
i2c/src/rtl/i2c.v | 217 -----
i2c/src/rtl/i2c_regs.v | 130 +++
i2c/src/sw/Makefile | 7 +
{novena => i2c}/src/sw/hash_tester_i2c.c | 21 +
.../toolruns/xilinx/novena}/build/.gitignore | 0
i2c/toolruns/xilinx/novena/build/Makefile | 32 +
.../toolruns/xilinx/novena}/build/xilinx.mk | 0
.../toolruns/xilinx/novena}/build/xilinx.opt | 0
.../xilinx/novena/iseconfig/_xmsgs/pn_parser.xmsgs | 24 +
.../xilinx/novena/iseconfig/_xmsgs/xst.xmsgs | 105 +++
.../iseconfig/novena_baseline_top.xreport | 215 +++++
.../iseconfig/novena_reorg_i2c.projectmgr | 77 ++
.../novena/iseconfig/novena_baseline_top.cmd_log | 1 +
.../novena/iseconfig/novena_baseline_top.lso | 1 +
.../novena/iseconfig/novena_baseline_top.prj | 20 +
.../novena/iseconfig/novena_baseline_top.syr | 989 +++++++++++++++++++++
.../novena/iseconfig/novena_baseline_top.xst | 40 +-
.../iseconfig/novena_baseline_top_summary.html | 80 ++
.../xilinx/novena/iseconfig/novena_reorg_i2c.gise | 84 ++
.../xilinx/novena/iseconfig}/novena_reorg_i2c.xise | 73 +-
.../xilinx/novena/iseconfig/webtalk_pn.xml | 42 +
.../xilinx/novena/iseconfig/xst/work/work.sdbl | Bin 0 -> 385657 bytes
.../xilinx/novena/iseconfig/xst/work/work.sdbx | Bin 0 -> 530 bytes
.../toolruns/xilinx/novena}/rtl/novena_i2c.v | 0
.../toolruns/xilinx/novena}/ucf/novena_i2c.ucf | 0
novena/build/Makefile.eim | 39 -
novena/build/Makefile.i2c | 36 -
novena/src/rtl/novena_regs.v | 126 ---
uart/LICENSE | 24 +
uart/README.md | 14 +
uart/src/rtl/uart_core.v | 581 ++++++++++++
uart/src/rtl/uart_regs.v | 155 ++++
uart/src/sw/seriedebug.py | 113 +++
uart/src/tb/tb_uart.v | 394 ++++++++
uart/toolruns/Makefile | 70 ++
.../quartus/terasic_c5g/coretest_hashes.qpf | 31 +
.../terasic_c5g/db/prev_cmp_coretest_hashes.qmsg | 40 +
.../quartus/terasic_c5g/db/terasic_top.(0).cnf.cdb | Bin 0 -> 3424 bytes
.../quartus/terasic_c5g/db/terasic_top.(0).cnf.hdb | Bin 0 -> 1960 bytes
.../quartus/terasic_c5g/db/terasic_top.(1).cnf.cdb | Bin 0 -> 5812 bytes
.../quartus/terasic_c5g/db/terasic_top.(1).cnf.hdb | Bin 0 -> 2209 bytes
.../terasic_c5g/db/terasic_top.(10).cnf.cdb | Bin 0 -> 34456 bytes
.../terasic_c5g/db/terasic_top.(10).cnf.hdb | Bin 0 -> 11849 bytes
.../terasic_c5g/db/terasic_top.(11).cnf.cdb | Bin 0 -> 146915 bytes
.../terasic_c5g/db/terasic_top.(11).cnf.hdb | Bin 0 -> 32942 bytes
.../terasic_c5g/db/terasic_top.(12).cnf.cdb | Bin 0 -> 69132 bytes
.../terasic_c5g/db/terasic_top.(12).cnf.hdb | Bin 0 -> 27253 bytes
.../terasic_c5g/db/terasic_top.(13).cnf.cdb | Bin 0 -> 13508 bytes
.../terasic_c5g/db/terasic_top.(13).cnf.hdb | Bin 0 -> 1292 bytes
.../terasic_c5g/db/terasic_top.(14).cnf.cdb | Bin 0 -> 7036 bytes
.../terasic_c5g/db/terasic_top.(14).cnf.hdb | Bin 0 -> 3029 bytes
.../terasic_c5g/db/terasic_top.(15).cnf.cdb | Bin 0 -> 58575 bytes
.../terasic_c5g/db/terasic_top.(15).cnf.hdb | Bin 0 -> 21633 bytes
.../terasic_c5g/db/terasic_top.(16).cnf.cdb | Bin 0 -> 16119 bytes
.../terasic_c5g/db/terasic_top.(16).cnf.hdb | Bin 0 -> 2935 bytes
.../terasic_c5g/db/terasic_top.(17).cnf.cdb | Bin 0 -> 16072 bytes
.../terasic_c5g/db/terasic_top.(17).cnf.hdb | Bin 0 -> 2940 bytes
.../quartus/terasic_c5g/db/terasic_top.(2).cnf.cdb | Bin 0 -> 6292 bytes
.../quartus/terasic_c5g/db/terasic_top.(2).cnf.hdb | Bin 0 -> 2532 bytes
.../quartus/terasic_c5g/db/terasic_top.(3).cnf.cdb | Bin 0 -> 14196 bytes
.../quartus/terasic_c5g/db/terasic_top.(3).cnf.hdb | Bin 0 -> 1800 bytes
.../quartus/terasic_c5g/db/terasic_top.(4).cnf.cdb | Bin 0 -> 72097 bytes
.../quartus/terasic_c5g/db/terasic_top.(4).cnf.hdb | Bin 0 -> 16849 bytes
.../quartus/terasic_c5g/db/terasic_top.(5).cnf.cdb | Bin 0 -> 30776 bytes
.../quartus/terasic_c5g/db/terasic_top.(5).cnf.hdb | Bin 0 -> 8448 bytes
.../quartus/terasic_c5g/db/terasic_top.(6).cnf.cdb | Bin 0 -> 32294 bytes
.../quartus/terasic_c5g/db/terasic_top.(6).cnf.hdb | Bin 0 -> 11509 bytes
.../quartus/terasic_c5g/db/terasic_top.(7).cnf.cdb | Bin 0 -> 74508 bytes
.../quartus/terasic_c5g/db/terasic_top.(7).cnf.hdb | Bin 0 -> 18117 bytes
.../quartus/terasic_c5g/db/terasic_top.(8).cnf.cdb | Bin 0 -> 37458 bytes
.../quartus/terasic_c5g/db/terasic_top.(8).cnf.hdb | Bin 0 -> 13423 bytes
.../quartus/terasic_c5g/db/terasic_top.(9).cnf.cdb | Bin 0 -> 1843 bytes
.../quartus/terasic_c5g/db/terasic_top.(9).cnf.hdb | Bin 0 -> 841 bytes
.../quartus/terasic_c5g/db/terasic_top.cbx.xml | 5 +
.../quartus/terasic_c5g/db/terasic_top.cmp.rdb | Bin 0 -> 4213 bytes
.../quartus/terasic_c5g/db/terasic_top.db_info | 3 +
.../quartus/terasic_c5g/db/terasic_top.hif | Bin 0 -> 2089 bytes
.../db/terasic_top.logic_util_heuristic.dat | 0
.../quartus/terasic_c5g/db/terasic_top.map.qmsg | 63 ++
.../quartus/terasic_c5g/db/terasic_top.map.rdb | Bin 0 -> 1143 bytes
.../quartus/terasic_c5g/db/terasic_top.map_bb.hdb | Bin 0 -> 11425 bytes
.../terasic_c5g/db/terasic_top.pti_db_list.ddb | Bin 0 -> 237 bytes
...ic_top.rom0_sha256_k_constants_e63d9e28.hdl.mif | 75 ++
.../db/terasic_top.sld_design_entry.sci | Bin 0 -> 270 bytes
.../terasic_c5g/db/terasic_top.smart_action.txt | 1 +
.../terasic_c5g/db/terasic_top.tis_db_list.ddb | Bin 0 -> 237 bytes
.../terasic_c5g/output_files/terasic_top.flow.rpt | 114 +++
.../terasic_c5g/output_files/terasic_top.map.rpt | 242 +++++
.../terasic_c5g/output_files/terasic_top.map.smsg | 12 +
.../output_files/terasic_top.map.summary | 12 +
uart/toolruns/quartus/terasic_c5g/terasic_top.qsf | 100 +++
uart/toolruns/quartus/terasic_c5g/terasic_top.qws | Bin 0 -> 613 bytes
.../toolruns/quartus/terasic_c5g/terasic_top.v | 174 ++--
168 files changed, 4864 insertions(+), 596 deletions(-)
diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
index 4200b15..ba1d724 100644
--- a/core_selector/src/rtl/core_selector.v
+++ b/core_selector/src/rtl/core_selector.v
@@ -106,7 +106,7 @@ module core_selector
// EIM address space and select which core to send EIM read and
// write operations to.
//----------------------------------------------------------------
- hash_selector segment_hashes
+ hash_selector hashes
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -131,7 +131,7 @@ module core_selector
// EIM address space and select which RNG to send EIM read and
// write operations to. So far there are no RNG cores.
//----------------------------------------------------------------
- rng_selector segment_rngs
+ rng_selector rngs
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -156,7 +156,7 @@ module core_selector
// EIM address space and select which CIPHER to send EIM read and
// write operations to. So far there are no CIPHER cores.
//----------------------------------------------------------------
- cipher_selector segment_ciphers
+ cipher_selector ciphers
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v
index 4698078..067d040 100644
--- a/core_selector/src/rtl/hash_selector.v
+++ b/core_selector/src/rtl/hash_selector.v
@@ -149,7 +149,7 @@ XXX move to `define in wrapper core??
//----------------------------------------------------------------
wire [31: 0] read_data_global;
wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
- novena_regs novena_regs_inst
+ comm_regs comm_regs
(
.clk(sys_clk),
.rst(sys_rst),
diff --git a/diff b/diff
new file mode 100644
index 0000000..1fb2266
--- /dev/null
+++ b/diff
@@ -0,0 +1,682 @@
+diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
+index 4200b15..ba1d724 100644
+--- a/core_selector/src/rtl/core_selector.v
++++ b/core_selector/src/rtl/core_selector.v
+@@ -106,7 +106,7 @@ module core_selector
+ // EIM address space and select which core to send EIM read and
+ // write operations to.
+ //----------------------------------------------------------------
+- hash_selector segment_hashes
++ hash_selector hashes
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+@@ -131,7 +131,7 @@ module core_selector
+ // EIM address space and select which RNG to send EIM read and
+ // write operations to. So far there are no RNG cores.
+ //----------------------------------------------------------------
+- rng_selector segment_rngs
++ rng_selector rngs
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+@@ -156,7 +156,7 @@ module core_selector
+ // EIM address space and select which CIPHER to send EIM read and
+ // write operations to. So far there are no CIPHER cores.
+ //----------------------------------------------------------------
+- cipher_selector segment_ciphers
++ cipher_selector ciphers
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v
+index 4698078..067d040 100644
+--- a/core_selector/src/rtl/hash_selector.v
++++ b/core_selector/src/rtl/hash_selector.v
+@@ -149,7 +149,7 @@ XXX move to `define in wrapper core??
+ //----------------------------------------------------------------
+ wire [31: 0] read_data_global;
+ wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
+- novena_regs novena_regs_inst
++ comm_regs comm_regs
+ (
+ .clk(sys_clk),
+ .rst(sys_rst),
+diff --git a/eim/src/sw/hash_tester_eim.c b/eim/src/sw/hash_tester_eim.c
+index a0ab0f1..06253ea 100644
+--- a/eim/src/sw/hash_tester_eim.c
++++ b/eim/src/sw/hash_tester_eim.c
+@@ -418,6 +418,7 @@ int tc_wait_valid(off_t offset)
+
+ int TC0()
+ {
++#if 0
+ uint8_t board_type[4] = { 'P', 'V', 'T', '1'}; /* "PVT1" */
+ uint8_t bitstream_ver[4] = { 0x00, 0x01, 0x00, 0x0B }; /* v0.1.0b */
+ uint8_t t[4];
+@@ -451,6 +452,9 @@ int TC0()
+ tc_expected(SEGMENT_OFFSET_CIPHERS + (0 << 2), seg_ciphers_reg_first, 4) ||
+ tc_expected(SEGMENT_OFFSET_CIPHERS + (1 << 2), seg_ciphers_reg_second, 4) ||
+ tc_expected(SEGMENT_OFFSET_CIPHERS + (2 << 2), seg_ciphers_reg_third, 4);
++#else
++ return 0;
++#endif
+ }
+
+ /* ---------------- SHA-1 test cases ---------------- */
+diff --git a/eim/toolruns/xilinx/novena/build/Makefile b/eim/toolruns/xilinx/novena/build/Makefile
+index 6544fdd..d86ca15 100644
+--- a/eim/toolruns/xilinx/novena/build/Makefile
++++ b/eim/toolruns/xilinx/novena/build/Makefile
+@@ -5,35 +5,34 @@ part = xc6slx45csg324-3
+ top_module = novena_baseline_top
+ isedir = /opt/Xilinx/14.7/ISE_DS
+ xil_env = . $(isedir)/settings64.sh
+-ucf = ../src/ucf/novena_eim.ucf
++ucf = ../ucf/novena_eim.ucf
+
+ vfiles = \
+- ../src/rtl/novena_eim.v \
+- ../src/rtl/novena_clkmgr.v \
+- ../src/rtl/ipcore/clkmgr_dcm.v \
+- ../src/rtl/novena_regs.v \
+- ../../eim/src/rtl/eim.v \
+- ../../eim/src/rtl/eim_arbiter.v \
+- ../../eim/src/rtl/eim_arbiter_cdc.v \
+- ../../eim/src/rtl/cdc_bus_pulse.v \
+- ../../eim/src/rtl/eim_da_phy.v \
+- ../../eim/src/rtl/eim_indicator.v \
+- ../../core_selector/src/rtl/core_selector.v \
+- ../../core_selector/src/rtl/hash_selector.v \
+- ../../core_selector/src/rtl/rng_selector.v \
+- ../../core_selector/src/rtl/cipher_selector.v \
+- ../../sha1/src/rtl/sha1.v \
+- ../../sha1/src/rtl/sha1_core.v \
+- ../../sha1/src/rtl/sha1_w_mem.v \
+- ../../sha256/src/rtl/sha256.v \
+- ../../sha256/src/rtl/sha256_core.v \
+- ../../sha256/src/rtl/sha256_k_constants.v \
+- ../../sha256/src/rtl/sha256_w_mem.v \
+- ../../sha256/src/rtl/wb_sha256.v \
+- ../../sha512/src/rtl/sha512.v \
+- ../../sha512/src/rtl/sha512_core.v \
+- ../../sha512/src/rtl/sha512_h_constants.v \
+- ../../sha512/src/rtl/sha512_k_constants.v \
+- ../../sha512/src/rtl/sha512_w_mem.v
++ ../rtl/novena_eim.v \
++ ../rtl/novena_clkmgr.v \
++ ../rtl/ipcore/clkmgr_dcm.v \
++ ../../../../src/rtl/cdc_bus_pulse.v \
++ ../../../../src/rtl/eim_arbiter_cdc.v \
++ ../../../../src/rtl/eim_arbiter.v \
++ ../../../../src/rtl/eim_da_phy.v \
++ ../../../../src/rtl/eim_indicator.v \
++ ../../../../src/rtl/eim_regs.v \
++ ../../../../src/rtl/eim.v \
++ ../../../../../core_selector/src/rtl/cipher_selector.v \
++ ../../../../../core_selector/src/rtl/core_selector.v \
++ ../../../../../core_selector/src/rtl/hash_selector.v \
++ ../../../../../core_selector/src/rtl/rng_selector.v \
++ ../../../../../sha1/src/rtl/sha1_core.v \
++ ../../../../../sha1/src/rtl/sha1.v \
++ ../../../../../sha1/src/rtl/sha1_w_mem.v \
++ ../../../../../sha256/src/rtl/sha256_core.v \
++ ../../../../../sha256/src/rtl/sha256_k_constants.v \
++ ../../../../../sha256/src/rtl/sha256.v \
++ ../../../../../sha256/src/rtl/sha256_w_mem.v \
++ ../../../../../sha512/src/rtl/sha512_core.v \
++ ../../../../../sha512/src/rtl/sha512_h_constants.v \
++ ../../../../../sha512/src/rtl/sha512_k_constants.v \
++ ../../../../../sha512/src/rtl/sha512.v \
++ ../../../../../sha512/src/rtl/sha512_w_mem.v
+
+ include xilinx.mk
+diff --git a/i2c/src/rtl/i2c_core.v b/i2c/src/rtl/i2c_core.v
+index 798c105..3e821fa 100644
+--- a/i2c/src/rtl/i2c_core.v
++++ b/i2c/src/rtl/i2c_core.v
+@@ -577,4 +577,9 @@ module i2c_core (
+ SDA_sync <= SDA_s;
+ end // always @ (posedge clk or posedge reset)
+
++ /* This dummy register can be used by users to check that they can actually
++ * write something.
++ */
++ reg [31: 0] reg_dummy;
++
+ endmodule // i2c_slave
+diff --git a/i2c/src/rtl/i2c_regs.v b/i2c/src/rtl/i2c_regs.v
+index 4a3bc5d..898887c 100644
+--- a/i2c/src/rtl/i2c_regs.v
++++ b/i2c/src/rtl/i2c_regs.v
+@@ -37,179 +37,92 @@
+ //
+ //======================================================================
+
+-module i2c(
+- input wire clk,
+- input wire reset_n,
+-
+- // External interface.
+- input wire SCL,
+- input wire SDA,
+- output wire SDA_pd,
+- output wire [6:0] i2c_device_addr,
+-
+- // Internal receive interface.
+- output wire rxd_syn,
+- output [7 : 0] rxd_data,
+- input wire rxd_ack,
+-
+- // Internal transmit interface.
+- input wire txd_syn,
+- input wire [7 : 0] txd_data,
+- output wire txd_ack,
+-
+- // API interface.
+- input wire cs,
+- input wire we,
+- input wire [7 : 0] address,
+- input wire [31 : 0] write_data,
+- output wire [31 : 0] read_data,
+- output wire error,
+-
+- // Debug output.
+- output wire [7 : 0] debug
+- );
+-
+-
+- //----------------------------------------------------------------
+- // Internal constant and parameter definitions.
+- //----------------------------------------------------------------
+- // API addresses.
+- parameter ADDR_CORE_NAME0 = 8'h00;
+- parameter ADDR_CORE_NAME1 = 8'h01;
+- parameter ADDR_CORE_TYPE = 8'h02;
+- parameter ADDR_CORE_VERSION = 8'h03;
+-
+- // Core ID constants.
+- parameter CORE_NAME0 = 32'h69326320; // "i2c "
+- parameter CORE_NAME1 = 32'h20202020; // " "
+- parameter CORE_TYPE = 32'h20202031; // " 1"
+- parameter CORE_VERSION = 32'h302e3031; // "0.01"
+-
+- //----------------------------------------------------------------
+- // Wires.
+- //----------------------------------------------------------------
+-
+- wire core_SCL;
+- wire core_SDA;
+- wire core_SDA_pd;
+-
+- wire core_rxd_syn;
+- wire [7 : 0] core_rxd_data;
+- wire core_rxd_ack;
+-
+- wire core_txd_syn;
+- wire [7 : 0] core_txd_data;
+- wire core_txd_ack;
+-
+- reg [31 : 0] tmp_read_data;
+- reg tmp_error;
+-
+-
+- //----------------------------------------------------------------
+- // Concurrent connectivity for ports etc.
+- //----------------------------------------------------------------
+- assign core_SCL = SCL;
+- assign core_SDA = SDA;
+- assign SDA_pd = core_SDA_pd;
+-
+- assign rxd_syn = core_rxd_syn;
+- assign rxd_data = core_rxd_data;
+- assign core_rxd_ack = rxd_ack;
+-
+- assign core_txd_syn = txd_syn;
+- assign core_txd_data = txd_data;
+- assign txd_ack = core_txd_ack;
+-
+- assign read_data = tmp_read_data;
+- assign error = tmp_error;
+-
+- assign debug = core_rxd_data;
+-
+-
+- //----------------------------------------------------------------
+- // core
+- //
+- // Instantiation of the i2c core.
+- //----------------------------------------------------------------
+- i2c_core core(
+- .clk(clk),
+- .reset(reset_n),
+-
+- // External data interface
+- .SCL(core_SCL),
+- .SDA(core_SDA),
+- .SDA_pd(core_SDA_pd),
+- .i2c_device_addr(i2c_device_addr),
+-
+- // Internal receive interface.
+- .rxd_syn(core_rxd_syn),
+- .rxd_data(core_rxd_data),
+- .rxd_ack(core_rxd_ack),
+-
+- // Internal transmit interface.
+- .txd_syn(core_txd_syn),
+- .txd_data(core_txd_data),
+- .txd_ack(core_txd_ack)
+- );
+-
+-
+- //----------------------------------------------------------------
+- // api
+- //
+- // The core API that allows an internal host to control the
+- // core functionality.
+- //----------------------------------------------------------------
+- always @*
+- begin: api
+- // Default assignments.
+- tmp_read_data = 32'h00000000;
+- tmp_error = 0;
+-
+- if (cs)
+- begin
+- if (we)
+- begin
+- // Write operations.
+- case (address)
+- default:
+- begin
+- tmp_error = 1;
+- end
+- endcase // case (address)
+- end
+- else
+- begin
+- // Read operations.
+- case (address)
+- ADDR_CORE_NAME0:
+- begin
+- tmp_read_data = CORE_NAME0;
+- end
+-
+- ADDR_CORE_NAME1:
+- begin
+- tmp_read_data = CORE_NAME1;
+- end
+-
+- ADDR_CORE_TYPE:
+- begin
+- tmp_read_data = CORE_TYPE;
+- end
+-
+- ADDR_CORE_VERSION:
+- begin
+- tmp_read_data = CORE_VERSION;
+- end
+-
+- default:
+- begin
+- tmp_error = 1;
+- end
+- endcase // case (address)
+- end
++module comm_regs
++ (
++ input wire clk,
++ input wire rst,
++
++ input wire cs,
++ input wire we,
++
++ input wire [ 7 : 0] address,
++ input wire [31 : 0] write_data,
++ output wire [31 : 0] read_data
++ );
++
++
++ //----------------------------------------------------------------
++ // Internal constant and parameter definitions.
++ //----------------------------------------------------------------
++ // API addresses.
++ localparam ADDR_CORE_NAME0 = 8'h00;
++ localparam ADDR_CORE_NAME1 = 8'h01;
++ localparam ADDR_CORE_VERSION = 8'h02;
++ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
++
++ // Core ID constants.
++ localparam CORE_NAME0 = 32'h69326320; // "i2c "
++ localparam CORE_NAME1 = 32'h20202020; // " "
++ localparam CORE_VERSION = 32'h302e3031; // "0.01"
++
++
++ //----------------------------------------------------------------
++ // Wires.
++ //----------------------------------------------------------------
++ reg [31: 0] tmp_read_data;
++
++ /* This dummy register can be used by users to check that they can actually
++ * write something.
++ */
++ reg [31: 0] reg_dummy;
++
++ //----------------------------------------------------------------
++ // Concurrent connectivity for ports etc.
++ //----------------------------------------------------------------
++ assign read_data = tmp_read_data;
++
++
++ //----------------------------------------------------------------
++ // Access Handler
++ //----------------------------------------------------------------
++ always @(posedge clk)
++ //
++ if (rst) begin
++ reg_dummy <= {32{1'b0}};
++ end
++ else if (cs) begin
++ //
++ if (we) begin
++ //
++ // WRITE handler
++ //
++ case (address)
++ ADDR_DUMMY_REG:
++ reg_dummy <= write_data;
++ endcase
++ //
++ end else begin
++ //
++ // READ handler
++ //
++ case (address)
++ ADDR_CORE_NAME0:
++ tmp_read_data <= CORE_NAME0;
++ ADDR_CORE_NAME1:
++ tmp_read_data <= CORE_NAME1;
++ ADDR_CORE_VERSION:
++ tmp_read_data <= CORE_VERSION;
++ ADDR_DUMMY_REG:
++ tmp_read_data <= reg_dummy;
++ //
++ default:
++ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
++ endcase
++ //
+ end
+- end
+-
++ //
++ end
++
+ endmodule // i2c
+
+ //======================================================================
+diff --git a/i2c/src/sw/Makefile b/i2c/src/sw/Makefile
+index 8580a1a..8cf2b34 100755
+--- a/i2c/src/sw/Makefile
++++ b/i2c/src/sw/Makefile
+@@ -1,17 +1,7 @@
+-all: hash_tester_eim hash_tester_i2c
+-
+-.c.o:
+- gcc -c -Wall -o $@ $<
+-
+-hash_tester_eim: hash_tester_eim.o novena-eim.o
+- gcc -o $@ $^
+-
+-hash_tester_eim.o: hash_tester_eim.c novena-eim.h
+-
+-novena-eim.o: novena-eim.c novena-eim.h
++all: hash_tester_i2c
+
+ hash_tester_i2c: hash_tester_i2c.c
+ gcc -o $@ $^
+
+ clean:
+- rm -f *.o hash_tester_eim hash_tester_i2c
++ rm -f hash_tester_i2c
+diff --git a/i2c/src/sw/hash_tester_i2c.c b/i2c/src/sw/hash_tester_i2c.c
+index 70b98c2..e7c0eae 100644
+--- a/i2c/src/sw/hash_tester_i2c.c
++++ b/i2c/src/sw/hash_tester_i2c.c
+@@ -455,6 +455,7 @@ int tc_wait_valid(uint8_t addr0)
+
+ int TC0()
+ {
++#if 0
+ uint32_t board_type = 0x50565431; /* "PVT1" */
+ uint32_t bitstream_ver = 0x0001000B; /* v0.1.0b */
+ uint32_t t;
+@@ -471,6 +472,26 @@ int TC0()
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_BOARD_TYPE, board_type) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_BITSTREAM_VER, bitstream_ver) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
++#else
++ uint32_t name0 = 0x69326320; // "i2c "
++ uint32_t name1 = 0x20202020; // " "
++ uint32_t version = 0x302e3031; // "0.01"
++ uint32_t t;
++
++ printf("TC0: Reading name, type and version words from I2C core.\n");
++
++ /* write current time into dummy register, then try to read it back
++ * to make sure that we can actually write something into EIM
++ */
++ t = time(NULL);
++ tc_write(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
++
++ return
++ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME0, name0) ||
++ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME1, name1) ||
++ tc_read(GLOBAL_ADDR_PREFIX, ADDR_VERSION, version) ||
++ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
++#endif
+ }
+
+ /* ---------------- SHA-1 test cases ---------------- */
+diff --git a/i2c/toolruns/xilinx/novena/build/Makefile b/i2c/toolruns/xilinx/novena/build/Makefile
+index 267e33b..09980e2 100644
+--- a/i2c/toolruns/xilinx/novena/build/Makefile
++++ b/i2c/toolruns/xilinx/novena/build/Makefile
+@@ -5,32 +5,28 @@ part = xc6slx45csg324-3
+ top_module = novena_baseline_top
+ isedir = /opt/Xilinx/14.7/ISE_DS
+ xil_env = . $(isedir)/settings64.sh
+-ucf = ../src/ucf/novena_i2c.ucf
++ucf = ../ucf/novena_i2c.ucf
+
+ vfiles = \
+- ../src/rtl/novena_i2c.v \
+- ../src/rtl/novena_clkmgr.v \
+- ../src/rtl/ipcore/clkmgr_dcm.v \
+- ../src/rtl/novena_regs.v \
+- ../../i2c/src/rtl/i2c.v \
+- ../../i2c/src/rtl/i2c_core.v \
+- ../../coretest/src/rtl/coretest.v \
+- ../../core_selector/src/rtl/core_selector.v \
+- ../../core_selector/src/rtl/hash_selector.v \
+- ../../core_selector/src/rtl/rng_selector.v \
+- ../../core_selector/src/rtl/cipher_selector.v \
+- ../../sha1/src/rtl/sha1.v \
+- ../../sha1/src/rtl/sha1_core.v \
+- ../../sha1/src/rtl/sha1_w_mem.v \
+- ../../sha256/src/rtl/sha256.v \
+- ../../sha256/src/rtl/sha256_core.v \
+- ../../sha256/src/rtl/sha256_k_constants.v \
+- ../../sha256/src/rtl/sha256_w_mem.v \
+- ../../sha256/src/rtl/wb_sha256.v \
+- ../../sha512/src/rtl/sha512.v \
+- ../../sha512/src/rtl/sha512_core.v \
+- ../../sha512/src/rtl/sha512_h_constants.v \
+- ../../sha512/src/rtl/sha512_k_constants.v \
+- ../../sha512/src/rtl/sha512_w_mem.v
++ ../rtl/novena_i2c.v \
++ ../../../../src/rtl/i2c_core.v \
++ ../../../../src/rtl/i2c_regs.v \
++ ../../../../../coretest/src/rtl/coretest.v \
++ ../../../../../core_selector/src/rtl/cipher_selector.v \
++ ../../../../../core_selector/src/rtl/core_selector.v \
++ ../../../../../core_selector/src/rtl/hash_selector.v \
++ ../../../../../core_selector/src/rtl/rng_selector.v \
++ ../../../../../sha1/src/rtl/sha1_core.v \
++ ../../../../../sha1/src/rtl/sha1.v \
++ ../../../../../sha1/src/rtl/sha1_w_mem.v \
++ ../../../../../sha256/src/rtl/sha256_core.v \
++ ../../../../../sha256/src/rtl/sha256_k_constants.v \
++ ../../../../../sha256/src/rtl/sha256.v \
++ ../../../../../sha256/src/rtl/sha256_w_mem.v \
++ ../../../../../sha512/src/rtl/sha512_core.v \
++ ../../../../../sha512/src/rtl/sha512_h_constants.v \
++ ../../../../../sha512/src/rtl/sha512_k_constants.v \
++ ../../../../../sha512/src/rtl/sha512.v \
++ ../../../../../sha512/src/rtl/sha512_w_mem.v
+
+ include xilinx.mk
+diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
+index e7666bb..6e3cd35 100644
+--- a/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
++++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
+@@ -15,88 +15,88 @@
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+- <file xil_pn:name="../../src/rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+- <file xil_pn:name="../../src/ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
++ <file xil_pn:name="../ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+- <file xil_pn:name="../../../core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+- <file xil_pn:name="../../../core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ </file>
+- <file xil_pn:name="../../../core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ </file>
+- <file xil_pn:name="../../../core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+- <file xil_pn:name="../../../coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+- <file xil_pn:name="../../../i2c/src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+- <file xil_pn:name="../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+- <file xil_pn:name="../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+- <file xil_pn:name="../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+- <file xil_pn:name="../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ </file>
+- <file xil_pn:name="../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+- <file xil_pn:name="../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+- <file xil_pn:name="../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+- <file xil_pn:name="../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ </file>
+- <file xil_pn:name="../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+- <file xil_pn:name="../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+- <file xil_pn:name="../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+- <file xil_pn:name="../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
++ <file xil_pn:name="../../../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+- <file xil_pn:name="../../src/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
+- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
++ <file xil_pn:name="../../../../src/rtl/i2c_regs.v" xil_pn:type="FILE_VERILOG">
++ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
++ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ </files>
+
+@@ -161,6 +161,7 @@
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
++ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+@@ -214,7 +215,7 @@
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_baseline_top" xil_pn:valueState="non-default"/>
+- <property xil_pn:name="Implementation Top File" xil_pn:value="../../src/rtl/novena_i2c.v" xil_pn:valueState="non-default"/>
++ <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/novena_i2c.v" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_baseline_top" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/eim/src/rtl/eim_regs.v b/eim/src/rtl/eim_regs.v
new file mode 100644
index 0000000..70a9735
--- /dev/null
+++ b/eim/src/rtl/eim_regs.v
@@ -0,0 +1,128 @@
+//======================================================================
+//
+// eim.v
+// ------
+// Top level wrapper for the eim core.
+//
+// A simple EIM interface.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module comm_regs
+ (
+ input wire clk,
+ input wire rst,
+
+ input wire cs,
+ input wire we,
+
+ input wire [ 7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // API addresses.
+ localparam ADDR_CORE_NAME0 = 8'h00;
+ localparam ADDR_CORE_NAME1 = 8'h01;
+ localparam ADDR_CORE_VERSION = 8'h02;
+ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
+
+ // Core ID constants.
+ localparam CORE_NAME0 = 32'h65696d20; // "eim "
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3031; // "0.01"
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31: 0] tmp_read_data;
+
+ // dummy register to check that you can actually write something
+ reg [31: 0] reg_dummy;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+
+ //----------------------------------------------------------------
+ // Access Handler
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ //
+ if (rst)
+ reg_dummy <= {32{1'b0}};
+ else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_DUMMY_REG:
+ reg_dummy <= write_data;
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data <= CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data <= CORE_NAME1;
+ ADDR_CORE_VERSION:
+ tmp_read_data <= CORE_VERSION;
+ ADDR_DUMMY_REG:
+ tmp_read_data <= reg_dummy;
+ //
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
+endmodule // eim
+
+//======================================================================
+// EOF eim.v
+//======================================================================
diff --git a/novena/src/sw/Makefile b/eim/src/sw/Makefile
similarity index 100%
rename from novena/src/sw/Makefile
rename to eim/src/sw/Makefile
diff --git a/novena/src/sw/hash_tester_eim.c b/eim/src/sw/hash_tester_eim.c
similarity index 97%
rename from novena/src/sw/hash_tester_eim.c
rename to eim/src/sw/hash_tester_eim.c
index a0ab0f1..ba95379 100644
--- a/novena/src/sw/hash_tester_eim.c
+++ b/eim/src/sw/hash_tester_eim.c
@@ -418,6 +418,7 @@ int tc_wait_valid(off_t offset)
int TC0()
{
+#if 0
uint8_t board_type[4] = { 'P', 'V', 'T', '1'}; /* "PVT1" */
uint8_t bitstream_ver[4] = { 0x00, 0x01, 0x00, 0x0B }; /* v0.1.0b */
uint8_t t[4];
@@ -451,6 +452,27 @@ int TC0()
tc_expected(SEGMENT_OFFSET_CIPHERS + (0 << 2), seg_ciphers_reg_first, 4) ||
tc_expected(SEGMENT_OFFSET_CIPHERS + (1 << 2), seg_ciphers_reg_second, 4) ||
tc_expected(SEGMENT_OFFSET_CIPHERS + (2 << 2), seg_ciphers_reg_third, 4);
+#else
+ uint32_t name0 = 0x65696d20; // "eim "
+ uint32_t name1 = 0x20202020; // " "
+ uint32_t version = 0x302e3031; // "0.01"
+ uint32_t t;
+
+ if (!quiet)
+ printf("TC0: Reading name and version words from EIM core.\n");
+
+ /* write current time into dummy register, then try to read it back
+ * to make sure that we can actually write something into EIM
+ */
+ t = time(NULL);
+ tc_write(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
+
+ return
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME0, name0) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME1, name1) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_VERSION, version) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
+#endif
}
/* ---------------- SHA-1 test cases ---------------- */
diff --git a/novena/src/sw/novena-eim.c b/eim/src/sw/novena-eim.c
similarity index 100%
rename from novena/src/sw/novena-eim.c
rename to eim/src/sw/novena-eim.c
diff --git a/novena/src/sw/novena-eim.h b/eim/src/sw/novena-eim.h
similarity index 100%
rename from novena/src/sw/novena-eim.h
rename to eim/src/sw/novena-eim.h
diff --git a/novena/build/.gitignore b/eim/toolruns/xilinx/novena/build/.gitignore
similarity index 100%
copy from novena/build/.gitignore
copy to eim/toolruns/xilinx/novena/build/.gitignore
diff --git a/eim/toolruns/xilinx/novena/build/Makefile b/eim/toolruns/xilinx/novena/build/Makefile
new file mode 100644
index 0000000..d86ca15
--- /dev/null
+++ b/eim/toolruns/xilinx/novena/build/Makefile
@@ -0,0 +1,38 @@
+project = novena_reorg_eim
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_baseline_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings64.sh
+ucf = ../ucf/novena_eim.ucf
+
+vfiles = \
+ ../rtl/novena_eim.v \
+ ../rtl/novena_clkmgr.v \
+ ../rtl/ipcore/clkmgr_dcm.v \
+ ../../../../src/rtl/cdc_bus_pulse.v \
+ ../../../../src/rtl/eim_arbiter_cdc.v \
+ ../../../../src/rtl/eim_arbiter.v \
+ ../../../../src/rtl/eim_da_phy.v \
+ ../../../../src/rtl/eim_indicator.v \
+ ../../../../src/rtl/eim_regs.v \
+ ../../../../src/rtl/eim.v \
+ ../../../../../core_selector/src/rtl/cipher_selector.v \
+ ../../../../../core_selector/src/rtl/core_selector.v \
+ ../../../../../core_selector/src/rtl/hash_selector.v \
+ ../../../../../core_selector/src/rtl/rng_selector.v \
+ ../../../../../sha1/src/rtl/sha1_core.v \
+ ../../../../../sha1/src/rtl/sha1.v \
+ ../../../../../sha1/src/rtl/sha1_w_mem.v \
+ ../../../../../sha256/src/rtl/sha256_core.v \
+ ../../../../../sha256/src/rtl/sha256_k_constants.v \
+ ../../../../../sha256/src/rtl/sha256.v \
+ ../../../../../sha256/src/rtl/sha256_w_mem.v \
+ ../../../../../sha512/src/rtl/sha512_core.v \
+ ../../../../../sha512/src/rtl/sha512_h_constants.v \
+ ../../../../../sha512/src/rtl/sha512_k_constants.v \
+ ../../../../../sha512/src/rtl/sha512.v \
+ ../../../../../sha512/src/rtl/sha512_w_mem.v
+
+include xilinx.mk
diff --git a/novena/build/xilinx.mk b/eim/toolruns/xilinx/novena/build/xilinx.mk
similarity index 100%
copy from novena/build/xilinx.mk
copy to eim/toolruns/xilinx/novena/build/xilinx.mk
diff --git a/novena/build/xilinx.opt b/eim/toolruns/xilinx/novena/build/xilinx.opt
similarity index 100%
copy from novena/build/xilinx.opt
copy to eim/toolruns/xilinx/novena/build/xilinx.opt
diff --git a/novena/iseconfig/novena_reorg_eim/novena_reorg_eim.xise b/eim/toolruns/xilinx/novena/iseconfig/novena_reorg_eim.xise
similarity index 100%
rename from novena/iseconfig/novena_reorg_eim/novena_reorg_eim.xise
rename to eim/toolruns/xilinx/novena/iseconfig/novena_reorg_eim.xise
diff --git a/novena/src/rtl/ipcore/_xmsgs/cg.xmsgs b/eim/toolruns/xilinx/novena/rtl/ipcore/_xmsgs/cg.xmsgs
similarity index 100%
rename from novena/src/rtl/ipcore/_xmsgs/cg.xmsgs
rename to eim/toolruns/xilinx/novena/rtl/ipcore/_xmsgs/cg.xmsgs
diff --git a/novena/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs b/eim/toolruns/xilinx/novena/rtl/ipcore/_xmsgs/pn_parser.xmsgs
similarity index 100%
rename from novena/src/rtl/ipcore/_xmsgs/pn_parser.xmsgs
rename to eim/toolruns/xilinx/novena/rtl/ipcore/_xmsgs/pn_parser.xmsgs
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.asy b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.asy
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.asy
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.asy
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.gise b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.gise
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.gise
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.gise
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.ncf b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.ncf
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.ncf
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.ncf
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.sym b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.sym
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.sym
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.sym
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.ucf b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.ucf
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.ucf
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.ucf
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.v b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.v
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.v
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.v
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.veo b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.veo
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.veo
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.veo
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.xco b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xco
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.xco
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xco
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.xdc b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xdc
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.xdc
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xdc
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm.xise b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xise
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm.xise
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm.xise
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/implement.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/implement.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/implement.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/implement.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/implement.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/implement.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/implement.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/implement.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/xst.prj b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/xst.prj
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/xst.prj
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/xst.prj
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/implement/xst.scr b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/xst.scr
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/implement/xst.scr
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/implement/xst.scr
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm_flist.txt b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm_flist.txt
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm_flist.txt
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm_flist.txt
diff --git a/novena/src/rtl/ipcore/clkmgr_dcm_xmdf.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm_xmdf.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/clkmgr_dcm_xmdf.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/clkmgr_dcm_xmdf.tcl
diff --git a/novena/src/rtl/ipcore/coregen.cgp b/eim/toolruns/xilinx/novena/rtl/ipcore/coregen.cgp
similarity index 100%
rename from novena/src/rtl/ipcore/coregen.cgp
rename to eim/toolruns/xilinx/novena/rtl/ipcore/coregen.cgp
diff --git a/novena/src/rtl/ipcore/create_clkmgr_dcm.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/create_clkmgr_dcm.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/create_clkmgr_dcm.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/create_clkmgr_dcm.tcl
diff --git a/novena/src/rtl/ipcore/edit_clkmgr_dcm.tcl b/eim/toolruns/xilinx/novena/rtl/ipcore/edit_clkmgr_dcm.tcl
similarity index 100%
rename from novena/src/rtl/ipcore/edit_clkmgr_dcm.tcl
rename to eim/toolruns/xilinx/novena/rtl/ipcore/edit_clkmgr_dcm.tcl
diff --git a/novena/src/rtl/novena_clkmgr.v b/eim/toolruns/xilinx/novena/rtl/novena_clkmgr.v
similarity index 100%
rename from novena/src/rtl/novena_clkmgr.v
rename to eim/toolruns/xilinx/novena/rtl/novena_clkmgr.v
diff --git a/novena/src/rtl/novena_eim.v b/eim/toolruns/xilinx/novena/rtl/novena_eim.v
similarity index 100%
rename from novena/src/rtl/novena_eim.v
rename to eim/toolruns/xilinx/novena/rtl/novena_eim.v
diff --git a/novena/src/ucf/novena_eim.ucf b/eim/toolruns/xilinx/novena/ucf/novena_eim.ucf
similarity index 100%
rename from novena/src/ucf/novena_eim.ucf
rename to eim/toolruns/xilinx/novena/ucf/novena_eim.ucf
diff --git a/i2c/src/rtl/i2c.v b/i2c/src/rtl/i2c.v
deleted file mode 100644
index 4a3bc5d..0000000
--- a/i2c/src/rtl/i2c.v
+++ /dev/null
@@ -1,217 +0,0 @@
-//======================================================================
-//
-// i2c.v
-// ------
-// Top level wrapper for the i2c core.
-//
-// A simple I2C interface.
-//
-//
-// Author: Joachim Strombergson
-// Copyright (c) 2014, SUNET
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module i2c(
- input wire clk,
- input wire reset_n,
-
- // External interface.
- input wire SCL,
- input wire SDA,
- output wire SDA_pd,
- output wire [6:0] i2c_device_addr,
-
- // Internal receive interface.
- output wire rxd_syn,
- output [7 : 0] rxd_data,
- input wire rxd_ack,
-
- // Internal transmit interface.
- input wire txd_syn,
- input wire [7 : 0] txd_data,
- output wire txd_ack,
-
- // API interface.
- input wire cs,
- input wire we,
- input wire [7 : 0] address,
- input wire [31 : 0] write_data,
- output wire [31 : 0] read_data,
- output wire error,
-
- // Debug output.
- output wire [7 : 0] debug
- );
-
-
- //----------------------------------------------------------------
- // Internal constant and parameter definitions.
- //----------------------------------------------------------------
- // API addresses.
- parameter ADDR_CORE_NAME0 = 8'h00;
- parameter ADDR_CORE_NAME1 = 8'h01;
- parameter ADDR_CORE_TYPE = 8'h02;
- parameter ADDR_CORE_VERSION = 8'h03;
-
- // Core ID constants.
- parameter CORE_NAME0 = 32'h69326320; // "i2c "
- parameter CORE_NAME1 = 32'h20202020; // " "
- parameter CORE_TYPE = 32'h20202031; // " 1"
- parameter CORE_VERSION = 32'h302e3031; // "0.01"
-
- //----------------------------------------------------------------
- // Wires.
- //----------------------------------------------------------------
-
- wire core_SCL;
- wire core_SDA;
- wire core_SDA_pd;
-
- wire core_rxd_syn;
- wire [7 : 0] core_rxd_data;
- wire core_rxd_ack;
-
- wire core_txd_syn;
- wire [7 : 0] core_txd_data;
- wire core_txd_ack;
-
- reg [31 : 0] tmp_read_data;
- reg tmp_error;
-
-
- //----------------------------------------------------------------
- // Concurrent connectivity for ports etc.
- //----------------------------------------------------------------
- assign core_SCL = SCL;
- assign core_SDA = SDA;
- assign SDA_pd = core_SDA_pd;
-
- assign rxd_syn = core_rxd_syn;
- assign rxd_data = core_rxd_data;
- assign core_rxd_ack = rxd_ack;
-
- assign core_txd_syn = txd_syn;
- assign core_txd_data = txd_data;
- assign txd_ack = core_txd_ack;
-
- assign read_data = tmp_read_data;
- assign error = tmp_error;
-
- assign debug = core_rxd_data;
-
-
- //----------------------------------------------------------------
- // core
- //
- // Instantiation of the i2c core.
- //----------------------------------------------------------------
- i2c_core core(
- .clk(clk),
- .reset(reset_n),
-
- // External data interface
- .SCL(core_SCL),
- .SDA(core_SDA),
- .SDA_pd(core_SDA_pd),
- .i2c_device_addr(i2c_device_addr),
-
- // Internal receive interface.
- .rxd_syn(core_rxd_syn),
- .rxd_data(core_rxd_data),
- .rxd_ack(core_rxd_ack),
-
- // Internal transmit interface.
- .txd_syn(core_txd_syn),
- .txd_data(core_txd_data),
- .txd_ack(core_txd_ack)
- );
-
-
- //----------------------------------------------------------------
- // api
- //
- // The core API that allows an internal host to control the
- // core functionality.
- //----------------------------------------------------------------
- always @*
- begin: api
- // Default assignments.
- tmp_read_data = 32'h00000000;
- tmp_error = 0;
-
- if (cs)
- begin
- if (we)
- begin
- // Write operations.
- case (address)
- default:
- begin
- tmp_error = 1;
- end
- endcase // case (address)
- end
- else
- begin
- // Read operations.
- case (address)
- ADDR_CORE_NAME0:
- begin
- tmp_read_data = CORE_NAME0;
- end
-
- ADDR_CORE_NAME1:
- begin
- tmp_read_data = CORE_NAME1;
- end
-
- ADDR_CORE_TYPE:
- begin
- tmp_read_data = CORE_TYPE;
- end
-
- ADDR_CORE_VERSION:
- begin
- tmp_read_data = CORE_VERSION;
- end
-
- default:
- begin
- tmp_error = 1;
- end
- endcase // case (address)
- end
- end
- end
-
-endmodule // i2c
-
-//======================================================================
-// EOF i2c.v
-//======================================================================
diff --git a/i2c/src/rtl/i2c_regs.v b/i2c/src/rtl/i2c_regs.v
new file mode 100644
index 0000000..898887c
--- /dev/null
+++ b/i2c/src/rtl/i2c_regs.v
@@ -0,0 +1,130 @@
+//======================================================================
+//
+// i2c.v
+// ------
+// Top level wrapper for the i2c core.
+//
+// A simple I2C interface.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module comm_regs
+ (
+ input wire clk,
+ input wire rst,
+
+ input wire cs,
+ input wire we,
+
+ input wire [ 7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // API addresses.
+ localparam ADDR_CORE_NAME0 = 8'h00;
+ localparam ADDR_CORE_NAME1 = 8'h01;
+ localparam ADDR_CORE_VERSION = 8'h02;
+ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
+
+ // Core ID constants.
+ localparam CORE_NAME0 = 32'h69326320; // "i2c "
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_VERSION = 32'h302e3031; // "0.01"
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ reg [31: 0] tmp_read_data;
+
+ /* This dummy register can be used by users to check that they can actually
+ * write something.
+ */
+ reg [31: 0] reg_dummy;
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+
+ //----------------------------------------------------------------
+ // Access Handler
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ //
+ if (rst) begin
+ reg_dummy <= {32{1'b0}};
+ end
+ else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_DUMMY_REG:
+ reg_dummy <= write_data;
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data <= CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data <= CORE_NAME1;
+ ADDR_CORE_VERSION:
+ tmp_read_data <= CORE_VERSION;
+ ADDR_DUMMY_REG:
+ tmp_read_data <= reg_dummy;
+ //
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
+endmodule // i2c
+
+//======================================================================
+// EOF i2c.v
+//======================================================================
diff --git a/i2c/src/sw/Makefile b/i2c/src/sw/Makefile
new file mode 100755
index 0000000..8cf2b34
--- /dev/null
+++ b/i2c/src/sw/Makefile
@@ -0,0 +1,7 @@
+all: hash_tester_i2c
+
+hash_tester_i2c: hash_tester_i2c.c
+ gcc -o $@ $^
+
+clean:
+ rm -f hash_tester_i2c
diff --git a/novena/src/sw/hash_tester_i2c.c b/i2c/src/sw/hash_tester_i2c.c
similarity index 97%
rename from novena/src/sw/hash_tester_i2c.c
rename to i2c/src/sw/hash_tester_i2c.c
index 70b98c2..104544c 100644
--- a/novena/src/sw/hash_tester_i2c.c
+++ b/i2c/src/sw/hash_tester_i2c.c
@@ -455,6 +455,7 @@ int tc_wait_valid(uint8_t addr0)
int TC0()
{
+#if 0
uint32_t board_type = 0x50565431; /* "PVT1" */
uint32_t bitstream_ver = 0x0001000B; /* v0.1.0b */
uint32_t t;
@@ -471,6 +472,26 @@ int TC0()
tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_BOARD_TYPE, board_type) ||
tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_BITSTREAM_VER, bitstream_ver) ||
tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
+#else
+ uint32_t name0 = 0x69326320; // "i2c "
+ uint32_t name1 = 0x20202020; // " "
+ uint32_t version = 0x302e3031; // "0.01"
+ uint32_t t;
+
+ printf("TC0: Reading name and version words from I2C core.\n");
+
+ /* write current time into dummy register, then try to read it back
+ * to make sure that we can actually write something into EIM
+ */
+ t = time(NULL);
+ tc_write(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
+
+ return
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME0, name0) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_NAME1, name1) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_VERSION, version) ||
+ tc_read(GLOBAL_ADDR_PREFIX, ADDR_GLOBAL_DUMMY_REG, t);
+#endif
}
/* ---------------- SHA-1 test cases ---------------- */
diff --git a/novena/build/.gitignore b/i2c/toolruns/xilinx/novena/build/.gitignore
similarity index 100%
rename from novena/build/.gitignore
rename to i2c/toolruns/xilinx/novena/build/.gitignore
diff --git a/i2c/toolruns/xilinx/novena/build/Makefile b/i2c/toolruns/xilinx/novena/build/Makefile
new file mode 100644
index 0000000..09980e2
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/build/Makefile
@@ -0,0 +1,32 @@
+project = novena_reorg_i2c
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_baseline_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings64.sh
+ucf = ../ucf/novena_i2c.ucf
+
+vfiles = \
+ ../rtl/novena_i2c.v \
+ ../../../../src/rtl/i2c_core.v \
+ ../../../../src/rtl/i2c_regs.v \
+ ../../../../../coretest/src/rtl/coretest.v \
+ ../../../../../core_selector/src/rtl/cipher_selector.v \
+ ../../../../../core_selector/src/rtl/core_selector.v \
+ ../../../../../core_selector/src/rtl/hash_selector.v \
+ ../../../../../core_selector/src/rtl/rng_selector.v \
+ ../../../../../sha1/src/rtl/sha1_core.v \
+ ../../../../../sha1/src/rtl/sha1.v \
+ ../../../../../sha1/src/rtl/sha1_w_mem.v \
+ ../../../../../sha256/src/rtl/sha256_core.v \
+ ../../../../../sha256/src/rtl/sha256_k_constants.v \
+ ../../../../../sha256/src/rtl/sha256.v \
+ ../../../../../sha256/src/rtl/sha256_w_mem.v \
+ ../../../../../sha512/src/rtl/sha512_core.v \
+ ../../../../../sha512/src/rtl/sha512_h_constants.v \
+ ../../../../../sha512/src/rtl/sha512_k_constants.v \
+ ../../../../../sha512/src/rtl/sha512.v \
+ ../../../../../sha512/src/rtl/sha512_w_mem.v
+
+include xilinx.mk
diff --git a/novena/build/xilinx.mk b/i2c/toolruns/xilinx/novena/build/xilinx.mk
similarity index 100%
rename from novena/build/xilinx.mk
rename to i2c/toolruns/xilinx/novena/build/xilinx.mk
diff --git a/novena/build/xilinx.opt b/i2c/toolruns/xilinx/novena/build/xilinx.opt
similarity index 100%
copy from novena/build/xilinx.opt
copy to i2c/toolruns/xilinx/novena/build/xilinx.opt
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/pn_parser.xmsgs b/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..cb56952
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_core.v" into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_regs.v" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/xst.xmsgs b/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..517a56c
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/xst.xmsgs
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="1016" delta="new" >"/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 145: Port <arg fmt="%s" index="1">core_error</arg> is not connected to this instance
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="1127" delta="new" >"/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 159: Assignment to <arg fmt="%s" index="1">coretest_reset_n</arg> ignored, since the identifier is never used
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="552" delta="new" >"/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 145: Input port <arg fmt="%s" index="1">core_error</arg> is not connected on this instance
+</msg>
+
+<msg type="warning" file="Xst" num="2898" delta="new" >Port '<arg fmt="%s" index="1">core_error</arg>', unconnected in block instance '<arg fmt="%s" index="2">coretest</arg>', is tied to GND.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">reset_mcu_b_pin</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >"<arg fmt="%s" index="1">/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v</arg>" line <arg fmt="%s" index="2">145</arg>: Output port <<arg fmt="%s" index="3">core_reset_n</arg>> of the instance <<arg fmt="%s" index="4">coretest</arg>> is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<15></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<14></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<13></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<12></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<11></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<10></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<9></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<8></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<7></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<6></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<5></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<4></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<3></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<2></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<1></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">I2C_nstate<0></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SCL_nstate<3></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SCL_nstate<2></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SCL_nstate<1></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SCL_nstate<0></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SDA_nstate<3></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SDA_nstate<2></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SDA_nstate<1></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal <<arg fmt="%s" index="2">SDA_nstate<0></arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">write_data<31:1></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="internal" file="Xst" num="0" delta="new" srcfile="../interf/cmain.c" srcline="3423" srcrcs="1.29" >
+Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
+</msg>
+
+</messages>
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_baseline_top.xreport b/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_baseline_top.xreport
new file mode 100644
index 0000000..759e221
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_baseline_top.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+ <DateModified>2015-02-25T14:04:01</DateModified>
+ <ModuleName>novena_baseline_top</ModuleName>
+ <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+ <SavedFilePath>/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_baseline_top.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig</ImplementationReportsDirectory>
+ <DateInitialized>2015-02-25T14:04:01</DateInitialized>
+ <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+ <viewgroup label="Design Overview" >
+ <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="novena_baseline_top_summary.html" label="Summary" >
+ <toc-item title="Design Overview" target="Design Overview" />
+ <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+ <toc-item title="Performance Summary" target="Performance Summary" />
+ <toc-item title="Failing Constraints" target="Failing Constraints" />
+ <toc-item title="Detailed Reports" target="Detailed Reports" />
+ </view>
+ <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="novena_baseline_top_envsettings.html" label="System Settings" />
+ <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="novena_baseline_top_map.xrpt" label="IOB Properties" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="novena_baseline_top_map.xrpt" label="Control Set Information" />
+ <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="novena_baseline_top_map.xrpt" label="Module Level Utilization" />
+ <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="novena_baseline_top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+ <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="novena_baseline_top_par.xrpt" label="Pinout Report" />
+ <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="novena_baseline_top_par.xrpt" label="Clock Report" />
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="novena_baseline_top.twx" label="Static Timing" />
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="novena_baseline_top_html/fit/report.htm" label="CPLD Fitter Report" />
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="novena_baseline_top_html/tim/report.htm" label="CPLD Timing Report" />
+ </viewgroup>
+ <viewgroup label="XPS Errors and Warnings" >
+ <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+ <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+ <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+ </viewgroup>
+ <viewgroup label="XPS Reports" >
+ <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+ <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+ <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+ <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="novena_baseline_top.log" label="System Log File" />
+ </viewgroup>
+ <viewgroup label="Errors and Warnings" >
+ <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+ <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+ <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+ <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+ <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+ <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+ <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+ <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+ <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+ <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+ <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+ </viewgroup>
+ <viewgroup label="Detailed Reports" >
+ <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="novena_baseline_top.syr" label="Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+ <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
+ <toc-item title="HDL Compilation" target=" HDL Compilation " />
+ <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
+ <toc-item title="HDL Analysis" target=" HDL Analysis " />
+ <toc-item title="HDL Parsing" target=" HDL Parsing " />
+ <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
+ <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
+ <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+ <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
+ <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+ <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
+ <toc-item title="Partition Report" target=" Partition Report " />
+ <toc-item title="Final Report" target=" Final Report " />
+ <toc-item title="Design Summary" target=" Design Summary " />
+ <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+ <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+ <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+ <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+ <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+ <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+ <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+ <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+ <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+ </view>
+ <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.srr" label="Synplify Report" />
+ <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.prec_log" label="Precision Report" />
+ <view inputState="Synthesized" program="ngdbuild" type="Report" file="novena_baseline_top.bld" label="Translation Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Command Line" target="Command Line:" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+ </view>
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="novena_baseline_top_map.mrp" label="Map Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+ <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+ <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+ <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+ <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+ <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+ <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+ <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+ <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+ <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+ <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+ <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+ <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="novena_baseline_top.par" label="Place and Route Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+ <toc-item title="Router Information" target="Starting Router" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Clock Report" target="Generating Clock Report" />
+ <toc-item title="Timing Results" target="Timing Score:" />
+ <toc-item title="Final Summary" target="Peak Memory Usage:" />
+ </view>
+ <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="novena_baseline_top.twr" label="Post-PAR Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.rpt" label="CPLD Fitter Report (Text)" >
+ <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+ <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
+ <toc-item title="Pin Resources" target="** Pin Resources **" />
+ <toc-item title="Global Resources" target="** Global Control Resources **" />
+ </view>
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.tim" label="CPLD Timing Report (Text)" >
+ <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+ <toc-item title="Performance Summary" target="Performance Summary:" />
+ </view>
+ <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="novena_baseline_top.pwr" label="Power Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Power summary" target="Power summary" />
+ <toc-item title="Thermal summary" target="Thermal summary" />
+ </view>
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="novena_baseline_top.bgn" label="Bitgen Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+ <toc-item title="Final Summary" target="DRC detected" />
+ </view>
+ </viewgroup>
+ <viewgroup label="Secondary Reports" >
+ <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+ <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/novena_baseline_top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/novena_baseline_top_translate.nlf" label="Post-Translate Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="novena_baseline_top_map.map" label="Map Log File" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Design Information" target="Design Information" />
+ <toc-item title="Design Summary" target="Design Summary" />
+ </view>
+ <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+ <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_preroute.twr" label="Post-Map Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/novena_baseline_top_map.nlf" label="Post-Map Simulation Model Report" />
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_map.psr" label="Physical Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="novena_baseline_top_pad.txt" label="Pad Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="novena_baseline_top.unroutes" label="Unroutes Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.grf" label="Guide Results Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.dly" label="Asynchronous Delay Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.clk_rgn" label="Clock Region Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.tsi" label="Post-Place and Route Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+ <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/novena_baseline_top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_sta.nlf" label="Primetime Netlist Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.ibs" label="IBIS Model" >
+ <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+ <toc-item title="Component" target="Component " />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.lck" label="Back-annotate Pin Report" >
+ <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+ <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.lpc" label="Locked Pin Constraints" >
+ <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+ <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+ </view>
+ <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/novena_baseline_top_timesim.nlf" label="Post-Fit Simulation Model Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+ </viewgroup>
+ </body>
+</report-views>
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_reorg_i2c.projectmgr b/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_reorg_i2c.projectmgr
new file mode 100644
index 0000000..e4ae2a0
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/iseconfig/novena_reorg_i2c.projectmgr
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
+<Project version="2" owner="projectmgr" name="novena_reorg_i2c" >
+ <!--This is an ISE project configuration file.-->
+ <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes>
+ <ClosedNodesVersion>2</ClosedNodesVersion>
+ <ClosedNode>/novena_baseline_top |home|pselkirk|cryptech|user|paul|core|i2c|toolruns|xilinx|novena|rtl|novena_i2c.v/cores - core_selector/segment_hashes - hash_selector/sha1_inst - sha1</ClosedNode>
+ <ClosedNode>/novena_baseline_top |home|pselkirk|cryptech|user|paul|core|i2c|toolruns|xilinx|novena|rtl|novena_i2c.v/cores - core_selector/segment_hashes - hash_selector/sha256_inst - sha256</ClosedNode>
+ <ClosedNode>/novena_baseline_top |home|pselkirk|cryptech|user|paul|core|i2c|toolruns|xilinx|novena|rtl|novena_i2c.v/cores - core_selector/segment_hashes - hash_selector/sha512_inst - sha512</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>novena_baseline_top (/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c7000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c70000000100000003000000000000000100000003</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>novena_baseline_top (/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" ></ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <ItemView guiview="File" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000002a0000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac0000000100000000000000d600000001000000000000008400000001000000000000009a0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>cipher_selector.v</CurrentItem>
+ </ItemView>
+ <ItemView guiview="Library" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>work</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>work</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>Configure Target Device</ClosedNode>
+ <ClosedNode>Design Utilities</ClosedNode>
+ <ClosedNode>Implement Design</ClosedNode>
+ <ClosedNode>Synthesize - XST</ClosedNode>
+ <ClosedNode>User Constraints</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Generate Programming File</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Generate Programming File</CurrentItem>
+ </ItemView>
+ <SourceProcessView>000000ff00000000000000020000014c0000011d01000000060100000002</SourceProcessView>
+ <CurrentView>Implementation</CurrentView>
+</Project>
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.cmd_log b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.cmd_log
new file mode 100644
index 0000000..54bbe09
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.cmd_log
@@ -0,0 +1 @@
+xst -intstyle ise -ifn "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.xst" -ofn "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.syr"
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.lso b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.lso
new file mode 100644
index 0000000..b8f99f5
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.lso
@@ -0,0 +1 @@
+work
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.prj b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.prj
new file mode 100644
index 0000000..6b89de0
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.prj
@@ -0,0 +1,20 @@
+verilog work "../../../../../sha512/src/rtl/sha512_w_mem.v"
+verilog work "../../../../../sha512/src/rtl/sha512_k_constants.v"
+verilog work "../../../../../sha512/src/rtl/sha512_h_constants.v"
+verilog work "../../../../../sha256/src/rtl/sha256_w_mem.v"
+verilog work "../../../../../sha256/src/rtl/sha256_k_constants.v"
+verilog work "../../../../../sha1/src/rtl/sha1_w_mem.v"
+verilog work "../../../../../sha512/src/rtl/sha512_core.v"
+verilog work "../../../../../sha256/src/rtl/sha256_core.v"
+verilog work "../../../../../sha1/src/rtl/sha1_core.v"
+verilog work "../../../../../sha512/src/rtl/sha512.v"
+verilog work "../../../../../sha256/src/rtl/sha256.v"
+verilog work "../../../../../sha1/src/rtl/sha1.v"
+verilog work "../../../../src/rtl/i2c_regs.v"
+verilog work "../../../../../core_selector/src/rtl/rng_selector.v"
+verilog work "../../../../../core_selector/src/rtl/hash_selector.v"
+verilog work "../../../../../core_selector/src/rtl/cipher_selector.v"
+verilog work "../../../../src/rtl/i2c_core.v"
+verilog work "../../../../../core_selector/src/rtl/core_selector.v"
+verilog work "../../../../../coretest/src/rtl/coretest.v"
+verilog work "../rtl/novena_i2c.v"
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.syr b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.syr
new file mode 100644
index 0000000..458e56c
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.syr
@@ -0,0 +1,989 @@
+Release 14.7 - xst P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
+-->
+Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.06 secs
+
+-->
+Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.06 secs
+
+-->
+Reading design: novena_baseline_top.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Parsing
+ 3) HDL Elaboration
+ 4) HDL Synthesis
+ 4.1) HDL Synthesis Report
+ 5) Advanced HDL Synthesis
+ 5.1) Advanced HDL Synthesis Report
+ 6) Low Level Synthesis
+ 7) Partition Report
+ 8) Design Summary
+ 8.1) Primitive and Black Box Usage
+ 8.2) Device utilization summary
+ 8.3) Partition Resource Summary
+ 8.4) Timing Report
+ 8.4.1) Clock Information
+ 8.4.2) Asynchronous Control Signals Information
+ 8.4.3) Timing Summary
+ 8.4.4) Timing Details
+ 8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+* Synthesis Options Summary *
+=========================================================================
+---- Source Parameters
+Input File Name : "novena_baseline_top.prj"
+Ignore Synthesis Constraint File : NO
+
+---- Target Parameters
+Output File Name : "novena_baseline_top"
+Output Format : NGC
+Target Device : xc6slx45-3-csg324
+
+---- Source Options
+Top Module Name : novena_baseline_top
+Automatic FSM Extraction : YES
+FSM Encoding Algorithm : Auto
+Safe Implementation : No
+FSM Style : LUT
+RAM Extraction : Yes
+RAM Style : Auto
+ROM Extraction : Yes
+Shift Register Extraction : YES
+ROM Style : Auto
+Resource Sharing : YES
+Asynchronous To Synchronous : NO
+Shift Register Minimum Size : 2
+Use DSP Block : Auto
+Automatic Register Balancing : No
+
+---- Target Options
+LUT Combining : Auto
+Reduce Control Sets : Auto
+Add IO Buffers : YES
+Global Maximum Fanout : 100000
+Add Generic Clock Buffer(BUFG) : 16
+Register Duplication : YES
+Optimize Instantiated Primitives : NO
+Use Clock Enable : Auto
+Use Synchronous Set : Auto
+Use Synchronous Reset : Auto
+Pack IO Registers into IOBs : Auto
+Equivalent register Removal : YES
+
+---- General Options
+Optimization Goal : Speed
+Optimization Effort : 1
+Power Reduction : NO
+Keep Hierarchy : No
+Netlist Hierarchy : As_Optimized
+RTL Output : Yes
+Global Optimization : AllClockNets
+Read Cores : YES
+Write Timing Constraints : NO
+Cross Clock Analysis : NO
+Hierarchy Separator : /
+Bus Delimiter : <>
+Case Specifier : Maintain
+Slice Utilization Ratio : 100
+BRAM Utilization Ratio : 100
+DSP48 Utilization Ratio : 100
+Auto BRAM Packing : NO
+Slice Utilization Ratio Delta : 5
+
+=========================================================================
+
+
+=========================================================================
+* HDL Parsing *
+=========================================================================
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v" into library work
+Parsing module <sha512_w_mem>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v" into library work
+Parsing module <sha512_k_constants>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v" into library work
+Parsing module <sha512_h_constants>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v" into library work
+Parsing module <sha256_w_mem>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v" into library work
+Parsing module <sha256_k_constants>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v" into library work
+Parsing module <sha1_w_mem>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" into library work
+Parsing module <sha512_core>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" into library work
+Parsing module <sha256_core>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" into library work
+Parsing module <sha1_core>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" into library work
+Parsing module <sha512>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" into library work
+Parsing module <sha256>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" into library work
+Parsing module <sha1>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_regs.v" into library work
+Parsing module <comm_regs>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v" into library work
+Parsing module <rng_selector>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" into library work
+Parsing module <hash_selector>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v" into library work
+Parsing module <cipher_selector>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_core.v" into library work
+Parsing module <i2c_core>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" into library work
+Parsing module <core_selector>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" into library work
+Parsing module <coretest>.
+Analyzing Verilog file "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" into library work
+Parsing module <novena_baseline_top>.
+
+=========================================================================
+* HDL Elaboration *
+=========================================================================
+WARNING:HDLCompiler:1016 - "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 145: Port core_error is not connected to this instance
+
+Elaborating module <novena_baseline_top>.
+
+Elaborating module <IBUFGDS>.
+
+Elaborating module <IOBUF(DRIVE=8,SLEW="SLOW")>.
+
+Elaborating module <i2c_core>.
+
+Elaborating module <coretest>.
+WARNING:HDLCompiler:1127 - "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 159: Assignment to coretest_reset_n ignored, since the identifier is never used
+
+Elaborating module <core_selector>.
+
+Elaborating module <hash_selector>.
+
+Elaborating module <comm_regs>.
+
+Elaborating module <sha1>.
+
+Elaborating module <sha1_core>.
+
+Elaborating module <sha1_w_mem>.
+
+Elaborating module <sha256>.
+
+Elaborating module <sha256_core>.
+
+Elaborating module <sha256_k_constants>.
+
+Elaborating module <sha256_w_mem>.
+
+Elaborating module <sha512>.
+
+Elaborating module <sha512_core>.
+
+Elaborating module <sha512_k_constants>.
+
+Elaborating module <sha512_h_constants>.
+
+Elaborating module <sha512_w_mem>.
+
+Elaborating module <rng_selector>.
+
+Elaborating module <cipher_selector>.
+WARNING:HDLCompiler:552 - "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" Line 145: Input port core_error is not connected on this instance
+
+=========================================================================
+* HDL Synthesis *
+=========================================================================
+
+Synthesizing Unit <novena_baseline_top>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v".
+ I2C_DEVICE_ADDR = 7'b0001111
+WARNING:Xst:2898 - Port 'core_error', unconnected in block instance 'coretest', is tied to GND.
+WARNING:Xst:647 - Input <reset_mcu_b_pin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+INFO:Xst:3210 - "/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v" line 145: Output port <core_reset_n> of the instance <coretest> is unconnected or connected to loadless signal.
+ Summary:
+ no macro.
+Unit <novena_baseline_top> synthesized.
+
+Synthesizing Unit <i2c_core>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_core.v".
+ TRF_CYCLES = 5'b00100
+ I2C_START = 16'b0000000000000001
+ I2C_RESTART = 16'b0000000000000010
+ I2C_DADDR = 16'b0000000000000100
+ I2C_ACK_DADDR = 16'b0000000000001000
+ I2C_WR_DATA = 16'b0000000000010000
+ I2C_ACK_WR = 16'b0000000000100000
+ I2C_END_WR = 16'b0000000001000000
+ I2C_RD_DATA = 16'b0000000010000000
+ I2C_ACK_RD = 16'b0000000100000000
+ I2C_END_RD = 16'b0000001000000000
+ I2C_END_RD2 = 16'b0000010000000000
+ I2C_WAITSTOP = 16'b0000100000000000
+ I2C_RXD_SYN = 16'b0001000000000000
+ I2C_RXD_ACK = 16'b0010000000000000
+ I2C_TXD_SYN = 16'b0100000000000000
+ I2C_TXD_ACK = 16'b1000000000000000
+ I2C_nSTATES = 16
+ SCL_HIGH = 4'b0001
+ SCL_FALL = 4'b0010
+ SCL_LOW = 4'b0100
+ SCL_RISE = 4'b1000
+ SCL_nSTATES = 4
+ SDA_HIGH = 4'b0001
+ SDA_FALL = 4'b0010
+ SDA_LOW = 4'b0100
+ SDA_RISE = 4'b1000
+ SDA_nSTATES = 4
+ Found 4-bit register for signal <I2C_bitcnt>.
+ Found 8-bit register for signal <I2C_daddr>.
+ Found 8-bit register for signal <I2C_wdata>.
+ Found 1-bit register for signal <SDA_pd>.
+ Found 8-bit register for signal <I2C_rdata>.
+ Found 1-bit register for signal <rxd_syn_reg>.
+ Found 1-bit register for signal <txd_ack_reg>.
+ Found 4-bit register for signal <SCL_cstate>.
+ Found 5-bit register for signal <SCL_rfcnt>.
+ Found 4-bit register for signal <SDA_cstate>.
+ Found 5-bit register for signal <SDA_rfcnt>.
+ Found 1-bit register for signal <SCL_s>.
+ Found 1-bit register for signal <SCL_sync>.
+ Found 1-bit register for signal <SDA_s>.
+ Found 1-bit register for signal <SDA_sync>.
+ Found 16-bit register for signal <I2C_cstate>.
+ Found 4-bit adder for signal <I2C_bitcnt[3]_GND_4_o_add_98_OUT> created at line 261.
+ Found 5-bit adder for signal <SCL_rfcnt[4]_GND_4_o_add_174_OUT> created at line 465.
+ Found 5-bit adder for signal <SDA_rfcnt[4]_GND_4_o_add_212_OUT> created at line 548.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <I2C_nstate<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SCL_nstate<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SCL_nstate<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SCL_nstate<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SCL_nstate<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SDA_nstate<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SDA_nstate<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SDA_nstate<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+WARNING:Xst:737 - Found 1-bit latch for signal <SDA_nstate<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+ Found 4-bit comparator greater for signal <GND_4_o_I2C_bitcnt[3]_LessThan_11_o> created at line 169
+ Found 5-bit comparator greater for signal <GND_4_o_SCL_rfcnt[4]_LessThan_153_o> created at line 442
+ Found 5-bit comparator greater for signal <GND_4_o_SDA_rfcnt[4]_LessThan_191_o> created at line 525
+ Summary:
+ inferred 3 Adder/Subtractor(s).
+ inferred 69 D-type flip-flop(s).
+ inferred 24 Latch(s).
+ inferred 3 Comparator(s).
+ inferred 16 Multiplexer(s).
+Unit <i2c_core> synthesized.
+
+Synthesizing Unit <coretest>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v".
+ BUFFER_MAX = 4'b1111
+ SOC = 8'b01010101
+ EOC = 8'b10101010
+ RESET_CMD = 8'b00000001
+ READ_CMD = 8'b00010000
+ WRITE_CMD = 8'b00010001
+ SOR = 8'b10101010
+ EOR = 8'b01010101
+ UNKNOWN = 8'b11111110
+ ERROR = 8'b11111101
+ READ_OK = 8'b01111111
+ WRITE_OK = 8'b01111110
+ RESET_OK = 8'b01111101
+ RX_IDLE = 3'b000
+ RX_ACK = 3'b001
+ RX_NSYN = 3'b010
+ TX_IDLE = 3'b000
+ TX_SYN = 3'b001
+ TX_NOACK = 3'b010
+ TX_NEXT = 3'b011
+ TX_SENT = 3'b100
+ TX_DONE = 3'b101
+ TEST_IDLE = 8'b00000000
+ TEST_GET_CMD = 8'b00010000
+ TEST_PARSE_CMD = 8'b00010001
+ TEST_GET_ADDR0 = 8'b00100000
+ TEST_GET_ADDR1 = 8'b00100001
+ TEST_GET_DATA0 = 8'b00100100
+ TEST_GET_DATA1 = 8'b00100101
+ TEST_GET_DATA2 = 8'b00100110
+ TEST_GET_DATA3 = 8'b00100111
+ TEST_GET_EOC = 8'b00101000
+ TEST_RST_START = 8'b00110000
+ TEST_RST_WAIT = 8'b00110001
+ TEST_RST_END = 8'b00110010
+ TEST_RD_START = 8'b01010000
+ TEST_RD_WAIT = 8'b01010001
+ TEST_RD_WAIT2 = 8'b01010010
+ TEST_RD_END = 8'b01010011
+ TEST_WR_START = 8'b01100000
+ TEST_WR_WAIT = 8'b01100001
+ TEST_WR_END = 8'b01100010
+ TEST_CMD_UNKNOWN = 8'b10000000
+ TEST_CMD_ERROR = 8'b10000001
+ TEST_SEND_RESPONSE = 8'b11000000
+ Found 72-bit register for signal <n0280[71:0]>.
+ Found 1-bit register for signal <rx_syn_reg>.
+ Found 1-bit register for signal <rx_ack_reg>.
+ Found 1-bit register for signal <tx_ack_reg>.
+ Found 1-bit register for signal <tx_syn_reg>.
+ Found 4-bit register for signal <rx_buffer_rd_ptr_reg>.
+ Found 4-bit register for signal <rx_buffer_wr_ptr_reg>.
+ Found 4-bit register for signal <rx_buffer_ctr_reg>.
+ Found 4-bit register for signal <tx_buffer_ptr_reg>.
+ Found 4-bit register for signal <tx_msg_len_reg>.
+ Found 1-bit register for signal <send_response_reg>.
+ Found 1-bit register for signal <response_sent_reg>.
+ Found 8-bit register for signal <cmd_reg>.
+ Found 8-bit register for signal <core_addr_byte0_reg>.
+ Found 8-bit register for signal <core_addr_byte1_reg>.
+ Found 8-bit register for signal <core_wr_data_byte0_reg>.
+ Found 8-bit register for signal <core_wr_data_byte1_reg>.
+ Found 8-bit register for signal <core_wr_data_byte2_reg>.
+ Found 8-bit register for signal <core_wr_data_byte3_reg>.
+ Found 1-bit register for signal <core_reset_n>.
+ Found 1-bit register for signal <core_cs_reg>.
+ Found 1-bit register for signal <core_we_reg>.
+ Found 1-bit register for signal <core_error_reg>.
+ Found 32-bit register for signal <core_read_data_reg>.
+ Found 3-bit register for signal <rx_engine_reg>.
+ Found 3-bit register for signal <tx_engine_reg>.
+ Found 8-bit register for signal <test_engine_reg>.
+ Found 128-bit register for signal <n0277[127:0]>.
+ Found finite state machine <FSM_1> for signal <rx_engine_reg>.
+ -----------------------------------------------------------------------
+ | States | 3 |
+ | Transitions | 8 |
+ | Inputs | 3 |
+ | Outputs | 5 |
+ | Clock | clk (rising_edge) |
+ | Encoding | auto |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Found 4-bit subtractor for signal <rx_buffer_ctr_reg[3]_GND_29_o_sub_109_OUT> created at line 632.
+ Found 4-bit adder for signal <rx_buffer_rd_ptr_reg[3]_GND_29_o_add_103_OUT> created at line 585.
+ Found 4-bit adder for signal <rx_buffer_wr_ptr_reg[3]_GND_29_o_add_105_OUT> created at line 606.
+ Found 4-bit adder for signal <rx_buffer_ctr_reg[3]_GND_29_o_add_107_OUT> created at line 627.
+ Found 4-bit adder for signal <tx_buffer_ptr_reg[3]_GND_29_o_add_113_OUT> created at line 662.
+ Found 4x1-bit Read Only RAM for signal <response_sent_we>
+ Found 8x2-bit Read Only RAM for signal <_n0495>
+ Found 8-bit 9-to-1 multiplexer for signal <tx_data> created at line 254.
+ Found 8-bit 16-to-1 multiplexer for signal <rx_byte> created at line 482.
+ Found 3-bit 7-to-1 multiplexer for signal <tx_engine_new> created at line 751.
+ Found 1-bit 4-to-1 multiplexer for signal <rx_engine_we> created at line 218.
+ Found 4-bit comparator equal for signal <tx_buffer_ptr_reg[3]_tx_msg_len_reg[3]_equal_131_o> created at line 785
+ HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <tx_engine_reg> would allow inference of a finite state machine and as consequence better performance and smaller area.
+ Summary:
+ inferred 2 RAM(s).
+ inferred 4 Adder/Subtractor(s).
+ inferred 329 D-type flip-flop(s).
+ inferred 1 Comparator(s).
+ inferred 53 Multiplexer(s).
+ inferred 1 Finite State Machine(s).
+Unit <coretest> synthesized.
+
+Synthesizing Unit <core_selector>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v".
+ Found 32-bit 4-to-1 multiplexer for signal <_n0033> created at line 88.
+ Summary:
+ inferred 2 Multiplexer(s).
+Unit <core_selector> synthesized.
+
+Synthesizing Unit <hash_selector>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v".
+ Found 32-bit 4-to-1 multiplexer for signal <_n0066> created at line 232.
+ Summary:
+ inferred 2 Multiplexer(s).
+Unit <hash_selector> synthesized.
+
+Synthesizing Unit <comm_regs>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/i2c/src/rtl/i2c_regs.v".
+WARNING:Xst:647 - Input <write_data<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+ Found 32-bit register for signal <tmp_read_data>.
+ Summary:
+ inferred 32 D-type flip-flop(s).
+Unit <comm_regs> synthesized.
+
+Synthesizing Unit <sha1>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v".
+ ADDR_NAME0 = 8'b00000000
+ ADDR_NAME1 = 8'b00000001
+ ADDR_VERSION = 8'b00000010
+ ADDR_CTRL = 8'b00001000
+ CTRL_INIT_BIT = 0
+ CTRL_NEXT_BIT = 1
+ ADDR_STATUS = 8'b00001001
+ STATUS_READY_BIT = 0
+ STATUS_VALID_BIT = 1
+ ADDR_BLOCK = 8'b00010000
+ ADDR_DIGEST = 8'b00100000
+ CORE_NAME0 = 32'b01110011011010000110000100110001
+ CORE_NAME1 = 32'b00100000001000000010000000100000
+ CORE_VERSION = 32'b00110000001011100011010100110000
+ BLOCK_BITS = 512
+ DIGEST_BITS = 160
+ BLOCK_WORDS = 16
+ DIGEST_WORDS = 5
+ Found 1-bit register for signal <init_reg>.
+ Found 1-bit register for signal <next_reg>.
+ Found 512-bit register for signal <block_reg>.
+ Found 32-bit register for signal <tmp_read_data_reg>.
+ Found 160-bit register for signal <digest_reg>.
+ Found 5-bit subtractor for signal <GND_33_o_GND_33_o_sub_14_OUT<4:0>> created at line 161.
+ Found 512-bit shifter logical left for signal <n1092> created at line 179
+ Found 160-bit shifter logical left for signal <n1094> created at line 182
+ Found 8-bit comparator lessequal for signal <n0012> created at line 159
+ Found 8-bit comparator greater for signal <address[7]_GND_33_o_LessThan_13_o> created at line 160
+ Found 8-bit comparator greater for signal <address[7]_GND_33_o_LessThan_536_o> created at line 181
+ Summary:
+ inferred 1 Adder/Subtractor(s).
+ inferred 706 D-type flip-flop(s).
+ inferred 3 Comparator(s).
+ inferred 516 Multiplexer(s).
+ inferred 2 Combinational logic shifter(s).
+Unit <sha1> synthesized.
+
+Synthesizing Unit <sha1_core>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v".
+ H0_0 = 32'b01100111010001010010001100000001
+ H0_1 = 32'b11101111110011011010101110001001
+ H0_2 = 32'b10011000101110101101110011111110
+ H0_3 = 32'b00010000001100100101010001110110
+ H0_4 = 32'b11000011110100101110000111110000
+ SHA1_ROUNDS = 79
+ CTRL_IDLE = 0
+ CTRL_ROUNDS = 1
+ CTRL_DIGEST = 2
+ CTRL_DONE = 3
+ Found 32-bit register for signal <b_reg>.
+ Found 32-bit register for signal <c_reg>.
+ Found 32-bit register for signal <d_reg>.
+ Found 32-bit register for signal <e_reg>.
+ Found 32-bit register for signal <H0_reg>.
+ Found 32-bit register for signal <H1_reg>.
+ Found 32-bit register for signal <H2_reg>.
+ Found 32-bit register for signal <H3_reg>.
+ Found 32-bit register for signal <H4_reg>.
+ Found 32-bit register for signal <a_reg>.
+ Found 7-bit register for signal <round_ctr_reg>.
+ Found 2-bit register for signal <sha1_ctrl_reg>.
+ Found 1-bit register for signal <digest_valid_reg>.
+ Found finite state machine <FSM_3> for signal <sha1_ctrl_reg>.
+ -----------------------------------------------------------------------
+ | States | 4 |
+ | Transitions | 11 |
+ | Inputs | 4 |
+ | Outputs | 6 |
+ | Clock | clk (rising_edge) |
+ | Reset | reset_n (negative) |
+ | Reset type | asynchronous |
+ | Reset State | 00 |
+ | Encoding | auto |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_30_OUT> created at line 240.
+ Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_31_OUT> created at line 241.
+ Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_32_OUT> created at line 242.
+ Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_33_OUT> created at line 243.
+ Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_34_OUT> created at line 244.
+ Found 32-bit adder for signal <n0235> created at line 320.
+ Found 32-bit adder for signal <n0238> created at line 320.
+ Found 32-bit adder for signal <n0241> created at line 320.
+ Found 32-bit adder for signal <a_reg[26]_w[31]_add_80_OUT> created at line 320.
+ Found 7-bit adder for signal <round_ctr_reg[6]_GND_34_o_add_90_OUT> created at line 351.
+ Found 1-bit 3-to-1 multiplexer for signal <sha1_ctrl_we> created at line 378.
+ Found 7-bit comparator lessequal for signal <n0055> created at line 298
+ Found 7-bit comparator lessequal for signal <n0061> created at line 303
+ Found 7-bit comparator lessequal for signal <n0063> created at line 303
+ Found 7-bit comparator lessequal for signal <n0066> created at line 308
+ Found 7-bit comparator lessequal for signal <n0068> created at line 308
+ Found 7-bit comparator lessequal for signal <n0076> created at line 313
+ Summary:
+ inferred 10 Adder/Subtractor(s).
+ inferred 328 D-type flip-flop(s).
+ inferred 6 Comparator(s).
+ inferred 34 Multiplexer(s).
+ inferred 1 Finite State Machine(s).
+Unit <sha1_core> synthesized.
+
+Synthesizing Unit <sha1_w_mem>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v".
+ SHA1_ROUNDS = 79
+ CTRL_IDLE = 1'b0
+ CTRL_UPDATE = 1'b1
+ Found 7-bit register for signal <w_ctr_reg>.
+ Found 512-bit register for signal <n0058[511:0]>.
+ Found 1-bit register for signal <sha1_w_mem_ctrl_reg>.
+ Found 7-bit adder for signal <w_ctr_reg[6]_GND_35_o_add_49_OUT> created at line 295.
+ Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_6_OUT> created at line 184.
+ Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_35_o_LessThan_6_o> created at line 182
+ Found 7-bit comparator greater for signal <GND_35_o_w_ctr_reg[6]_LessThan_12_o> created at line 253
+ Summary:
+ inferred 1 Adder/Subtractor(s).
+ inferred 520 D-type flip-flop(s).
+ inferred 2 Comparator(s).
+ inferred 40 Multiplexer(s).
+Unit <sha1_w_mem> synthesized.
+
+Synthesizing Unit <sha256>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v".
+ ADDR_NAME0 = 8'b00000000
+ ADDR_NAME1 = 8'b00000001
+ ADDR_VERSION = 8'b00000010
+ ADDR_CTRL = 8'b00001000
+ CTRL_INIT_BIT = 0
+ CTRL_NEXT_BIT = 1
+ ADDR_STATUS = 8'b00001001
+ STATUS_READY_BIT = 0
+ STATUS_VALID_BIT = 1
+ ADDR_BLOCK = 8'b00010000
+ ADDR_DIGEST = 8'b00100000
+ CORE_NAME0 = 32'b01110011011010000110000100110010
+ CORE_NAME1 = 32'b00101101001100100011010100110110
+ CORE_VERSION = 32'b00110000001011100011100000110000
+ BLOCK_BITS = 512
+ DIGEST_BITS = 256
+ BLOCK_WORDS = 16
+ DIGEST_WORDS = 8
+ Found 1-bit register for signal <init_reg>.
+ Found 1-bit register for signal <next_reg>.
+ Found 512-bit register for signal <block_reg>.
+ Found 32-bit register for signal <tmp_read_data_reg>.
+ Found 256-bit register for signal <digest_reg>.
+ Found 5-bit subtractor for signal <GND_36_o_GND_36_o_sub_14_OUT<4:0>> created at line 161.
+ Found 512-bit shifter logical left for signal <n1092> created at line 179
+ Found 256-bit shifter logical left for signal <n1094> created at line 182
+ Found 8-bit comparator lessequal for signal <n0012> created at line 159
+ Found 8-bit comparator greater for signal <address[7]_GND_36_o_LessThan_13_o> created at line 160
+ Found 8-bit comparator greater for signal <address[7]_GND_36_o_LessThan_536_o> created at line 181
+ Summary:
+ inferred 1 Adder/Subtractor(s).
+ inferred 802 D-type flip-flop(s).
+ inferred 3 Comparator(s).
+ inferred 516 Multiplexer(s).
+ inferred 2 Combinational logic shifter(s).
+Unit <sha256> synthesized.
+
+Synthesizing Unit <sha256_core>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v".
+ H0_0 = 32'b01101010000010011110011001100111
+ H0_1 = 32'b10111011011001111010111010000101
+ H0_2 = 32'b00111100011011101111001101110010
+ H0_3 = 32'b10100101010011111111010100111010
+ H0_4 = 32'b01010001000011100101001001111111
+ H0_5 = 32'b10011011000001010110100010001100
+ H0_6 = 32'b00011111100000111101100110101011
+ H0_7 = 32'b01011011111000001100110100011001
+ SHA256_ROUNDS = 63
+ CTRL_IDLE = 0
+ CTRL_ROUNDS = 1
+ CTRL_DONE = 2
+ Found 32-bit register for signal <b_reg>.
+ Found 32-bit register for signal <c_reg>.
+ Found 32-bit register for signal <d_reg>.
+ Found 32-bit register for signal <e_reg>.
+ Found 32-bit register for signal <f_reg>.
+ Found 32-bit register for signal <g_reg>.
+ Found 32-bit register for signal <h_reg>.
+ Found 32-bit register for signal <H0_reg>.
+ Found 32-bit register for signal <H1_reg>.
+ Found 32-bit register for signal <H2_reg>.
+ Found 32-bit register for signal <H3_reg>.
+ Found 32-bit register for signal <H4_reg>.
+ Found 32-bit register for signal <H5_reg>.
+ Found 32-bit register for signal <H6_reg>.
+ Found 32-bit register for signal <H7_reg>.
+ Found 32-bit register for signal <a_reg>.
+ Found 6-bit register for signal <t_ctr_reg>.
+ Found 2-bit register for signal <sha256_ctrl_reg>.
+ Found 1-bit register for signal <digest_valid_reg>.
+ Found finite state machine <FSM_4> for signal <sha256_ctrl_reg>.
+ -----------------------------------------------------------------------
+ | States | 3 |
+ | Transitions | 9 |
+ | Inputs | 4 |
+ | Outputs | 5 |
+ | Clock | clk (rising_edge) |
+ | Reset | reset_n (negative) |
+ | Reset type | asynchronous |
+ | Reset State | 00 |
+ | Encoding | auto |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_45_OUT> created at line 290.
+ Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_46_OUT> created at line 291.
+ Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_47_OUT> created at line 292.
+ Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_48_OUT> created at line 293.
+ Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_49_OUT> created at line 294.
+ Found 32-bit adder for signal <H5_reg[31]_f_reg[31]_add_50_OUT> created at line 295.
+ Found 32-bit adder for signal <H6_reg[31]_g_reg[31]_add_51_OUT> created at line 296.
+ Found 32-bit adder for signal <H7_reg[31]_h_reg[31]_add_52_OUT> created at line 297.
+ Found 32-bit adder for signal <n0294> created at line 319.
+ Found 32-bit adder for signal <n0297> created at line 319.
+ Found 32-bit adder for signal <n0300> created at line 319.
+ Found 32-bit adder for signal <t1> created at line 319.
+ Found 32-bit adder for signal <t2> created at line 339.
+ Found 32-bit adder for signal <t1[31]_t2[31]_add_95_OUT> created at line 391.
+ Found 32-bit adder for signal <d_reg[31]_t1[31]_add_96_OUT> created at line 395.
+ Found 6-bit adder for signal <t_ctr_reg[5]_GND_37_o_add_105_OUT> created at line 423.
+ Found 1-bit 4-to-1 multiplexer for signal <sha256_ctrl_we> created at line 458.
+ Summary:
+ inferred 16 Adder/Subtractor(s).
+ inferred 519 D-type flip-flop(s).
+ inferred 39 Multiplexer(s).
+ inferred 1 Finite State Machine(s).
+Unit <sha256_core> synthesized.
+
+Synthesizing Unit <sha256_k_constants>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v".
+ Found 64x32-bit Read Only RAM for signal <tmp_K>
+ Summary:
+ inferred 1 RAM(s).
+Unit <sha256_k_constants> synthesized.
+
+Synthesizing Unit <sha256_w_mem>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v".
+ CTRL_IDLE = 0
+ CTRL_UPDATE = 1
+ Found 6-bit register for signal <w_ctr_reg>.
+ Found 2-bit register for signal <sha256_w_mem_ctrl_reg>.
+ Found 512-bit register for signal <n0067[511:0]>.
+ Found finite state machine <FSM_5> for signal <sha256_w_mem_ctrl_reg>.
+ -----------------------------------------------------------------------
+ | States | 2 |
+ | Transitions | 5 |
+ | Inputs | 2 |
+ | Outputs | 2 |
+ | Clock | clk (rising_edge) |
+ | Reset | reset_n (negative) |
+ | Reset type | asynchronous |
+ | Reset State | 00 |
+ | Encoding | auto |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Found 32-bit adder for signal <n0132> created at line 233.
+ Found 32-bit adder for signal <n0135> created at line 233.
+ Found 32-bit adder for signal <w_new> created at line 233.
+ Found 6-bit adder for signal <w_ctr_reg[5]_GND_39_o_add_54_OUT> created at line 296.
+ Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_8_OUT> created at line 178.
+ Found 6-bit comparator greater for signal <w_ctr_reg[5]_GND_39_o_LessThan_8_o> created at line 176
+ Found 6-bit comparator greater for signal <GND_39_o_w_ctr_reg[5]_LessThan_18_o> created at line 255
+ Summary:
+ inferred 4 Adder/Subtractor(s).
+ inferred 518 D-type flip-flop(s).
+ inferred 2 Comparator(s).
+ inferred 39 Multiplexer(s).
+ inferred 1 Finite State Machine(s).
+Unit <sha256_w_mem> synthesized.
+
+Synthesizing Unit <sha512>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v".
+ ADDR_NAME0 = 8'b00000000
+ ADDR_NAME1 = 8'b00000001
+ ADDR_VERSION = 8'b00000010
+ ADDR_CTRL = 8'b00001000
+ CTRL_INIT_BIT = 0
+ CTRL_NEXT_BIT = 1
+ CTRL_MODE_LOW_BIT = 2
+ CTRL_MODE_HIGH_BIT = 3
+ CTRL_WORK_FACTOR_BIT = 7
+ ADDR_STATUS = 8'b00001001
+ STATUS_READY_BIT = 0
+ STATUS_VALID_BIT = 1
+ ADDR_WORK_FACTOR_NUM = 8'b00001010
+ ADDR_BLOCK = 8'b00010000
+ ADDR_DIGEST = 8'b01000000
+ CORE_NAME0 = 32'b01110011011010000110000100110010
+ CORE_NAME1 = 32'b00101101001101010011000100110010
+ CORE_VERSION = 32'b00110000001011100011100000110000
+ MODE_SHA_512_224 = 2'b00
+ MODE_SHA_512_256 = 2'b01
+ MODE_SHA_384 = 2'b10
+ MODE_SHA_512 = 2'b11
+ DEFAULT_WORK_FACTOR_NUM = 32'b00000000000011110000000000000000
+ BLOCK_BITS = 1024
+ DIGEST_BITS = 512
+ BLOCK_WORDS = 32
+ DIGEST_WORDS = 16
+ Found 1-bit register for signal <init_reg>.
+ Found 1-bit register for signal <next_reg>.
+ Found 2-bit register for signal <mode_reg>.
+ Found 1-bit register for signal <work_factor_reg>.
+ Found 32-bit register for signal <work_factor_num_reg>.
+ Found 1024-bit register for signal <block_reg>.
+ Found 32-bit register for signal <tmp_read_data_reg>.
+ Found 512-bit register for signal <digest_reg>.
+ Found 6-bit subtractor for signal <GND_40_o_GND_40_o_sub_16_OUT<5:0>> created at line 190.
+ Found 1024-bit shifter logical left for signal <n2144> created at line 214
+ Found 512-bit shifter logical left for signal <n2146> created at line 217
+ Found 8-bit comparator lessequal for signal <n0015> created at line 188
+ Found 8-bit comparator greater for signal <address[7]_GND_40_o_LessThan_15_o> created at line 189
+ Found 8-bit comparator lessequal for signal <n1074> created at line 215
+ Found 8-bit comparator greater for signal <address[7]_GND_40_o_LessThan_1060_o> created at line 216
+ Summary:
+ inferred 1 Adder/Subtractor(s).
+ inferred 1605 D-type flip-flop(s).
+ inferred 4 Comparator(s).
+ inferred 1034 Multiplexer(s).
+ inferred 2 Combinational logic shifter(s).
+Unit <sha512> synthesized.
+
+Synthesizing Unit <sha512_core>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v".
+ SHA512_ROUNDS = 79
+ CTRL_IDLE = 0
+ CTRL_ROUNDS = 1
+ CTRL_DONE = 2
+ Found 64-bit register for signal <b_reg>.
+ Found 64-bit register for signal <c_reg>.
+ Found 64-bit register for signal <d_reg>.
+ Found 64-bit register for signal <e_reg>.
+ Found 64-bit register for signal <f_reg>.
+ Found 64-bit register for signal <g_reg>.
+ Found 64-bit register for signal <h_reg>.
+ Found 64-bit register for signal <H0_reg>.
+ Found 64-bit register for signal <H1_reg>.
+ Found 64-bit register for signal <H2_reg>.
+ Found 64-bit register for signal <H3_reg>.
+ Found 64-bit register for signal <H4_reg>.
+ Found 64-bit register for signal <H5_reg>.
+ Found 64-bit register for signal <H6_reg>.
+ Found 64-bit register for signal <H7_reg>.
+ Found 64-bit register for signal <a_reg>.
+ Found 32-bit register for signal <work_factor_ctr_reg>.
+ Found 7-bit register for signal <t_ctr_reg>.
+ Found 2-bit register for signal <sha512_ctrl_reg>.
+ Found 1-bit register for signal <digest_valid_reg>.
+ Found finite state machine <FSM_6> for signal <sha512_ctrl_reg>.
+ -----------------------------------------------------------------------
+ | States | 3 |
+ | Transitions | 11 |
+ | Inputs | 6 |
+ | Outputs | 4 |
+ | Clock | clk (rising_edge) |
+ | Reset | reset_n (negative) |
+ | Reset type | asynchronous |
+ | Reset State | 00 |
+ | Encoding | auto |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Found 64-bit adder for signal <H0_reg[63]_a_reg[63]_add_47_OUT> created at line 321.
+ Found 64-bit adder for signal <H1_reg[63]_b_reg[63]_add_48_OUT> created at line 322.
+ Found 64-bit adder for signal <H2_reg[63]_c_reg[63]_add_49_OUT> created at line 323.
+ Found 64-bit adder for signal <H3_reg[63]_d_reg[63]_add_50_OUT> created at line 324.
+ Found 64-bit adder for signal <H4_reg[63]_e_reg[63]_add_51_OUT> created at line 325.
+ Found 64-bit adder for signal <H5_reg[63]_f_reg[63]_add_52_OUT> created at line 326.
+ Found 64-bit adder for signal <H6_reg[63]_g_reg[63]_add_53_OUT> created at line 327.
+ Found 64-bit adder for signal <H7_reg[63]_h_reg[63]_add_54_OUT> created at line 328.
+ Found 64-bit adder for signal <n0324> created at line 350.
+ Found 64-bit adder for signal <n0327> created at line 350.
+ Found 64-bit adder for signal <n0330> created at line 350.
+ Found 64-bit adder for signal <t1> created at line 350.
+ Found 64-bit adder for signal <t2> created at line 370.
+ Found 64-bit adder for signal <t1[63]_t2[63]_add_97_OUT> created at line 422.
+ Found 64-bit adder for signal <d_reg[63]_t1[63]_add_98_OUT> created at line 426.
+ Found 7-bit adder for signal <t_ctr_reg[6]_GND_41_o_add_107_OUT> created at line 454.
+ Found 32-bit adder for signal <work_factor_ctr_reg[31]_GND_41_o_add_110_OUT> created at line 484.
+ Found 1-bit 4-to-1 multiplexer for signal <w_init> created at line 522.
+ Found 1-bit 4-to-1 multiplexer for signal <sha512_ctrl_we> created at line 522.
+ Found 1-bit 4-to-1 multiplexer for signal <digest_valid_we> created at line 522.
+ Found 32-bit comparator equal for signal <work_factor_ctr_done> created at line 471
+ Summary:
+ inferred 17 Adder/Subtractor(s).
+ inferred 1064 D-type flip-flop(s).
+ inferred 1 Comparator(s).
+ inferred 55 Multiplexer(s).
+ inferred 1 Finite State Machine(s).
+Unit <sha512_core> synthesized.
+
+Synthesizing Unit <sha512_k_constants>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v".
+ Found 128x64-bit Read Only RAM for signal <tmp_K>
+ Summary:
+ inferred 1 RAM(s).
+Unit <sha512_k_constants> synthesized.
+
+Synthesizing Unit <sha512_h_constants>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v".
+ Found 4x512-bit Read Only RAM for signal <_n0037>
+ Summary:
+ inferred 1 RAM(s).
+Unit <sha512_h_constants> synthesized.
+
+Synthesizing Unit <sha512_w_mem>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v".
+ CTRL_IDLE = 1'b0
+ CTRL_UPDATE = 1'b1
+ Found 7-bit register for signal <w_ctr_reg>.
+ Found 1024-bit register for signal <n0061[1023:0]>.
+ Found 1-bit register for signal <sha512_w_mem_ctrl_reg>.
+ Found 64-bit adder for signal <n0120> created at line 234.
+ Found 64-bit adder for signal <n0123> created at line 234.
+ Found 64-bit adder for signal <w_new> created at line 234.
+ Found 7-bit adder for signal <w_ctr_reg[6]_GND_44_o_add_52_OUT> created at line 297.
+ Found 64-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][63]_wide_mux_6_OUT> created at line 179.
+ Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_44_o_LessThan_6_o> created at line 177
+ Found 7-bit comparator greater for signal <GND_44_o_w_ctr_reg[6]_LessThan_16_o> created at line 256
+ Summary:
+ inferred 4 Adder/Subtractor(s).
+ inferred 1032 D-type flip-flop(s).
+ inferred 2 Comparator(s).
+ inferred 40 Multiplexer(s).
+Unit <sha512_w_mem> synthesized.
+
+Synthesizing Unit <rng_selector>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v".
+ Found 32-bit register for signal <reg_dummy_second>.
+ Found 32-bit register for signal <reg_dummy_third>.
+ Found 32-bit register for signal <tmp_read_data>.
+ Found 32-bit register for signal <reg_dummy_first>.
+ Found 32-bit 4-to-1 multiplexer for signal <_n0058> created at line 95.
+ Summary:
+ inferred 128 D-type flip-flop(s).
+ inferred 1 Multiplexer(s).
+Unit <rng_selector> synthesized.
+
+Synthesizing Unit <cipher_selector>.
+ Related source file is "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v".
+ Found 32-bit register for signal <reg_dummy_second>.
+ Found 32-bit register for signal <reg_dummy_third>.
+ Found 32-bit register for signal <tmp_read_data>.
+ Found 32-bit register for signal <reg_dummy_first>.
+ Found 32-bit 4-to-1 multiplexer for signal <_n0058> created at line 100.
+ Summary:
+ inferred 128 D-type flip-flop(s).
+ inferred 1 Multiplexer(s).
+Unit <cipher_selector> synthesized.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# RAMs : 5
+ 128x64-bit single-port Read Only RAM : 1
+ 4x1-bit single-port Read Only RAM : 1
+ 4x512-bit single-port Read Only RAM : 1
+ 64x32-bit single-port Read Only RAM : 1
+ 8x2-bit single-port Read Only RAM : 1
+# Adders/Subtractors : 62
+ 32-bit adder : 28
+ 4-bit adder : 4
+ 4-bit addsub : 1
+ 5-bit adder : 2
+ 5-bit subtractor : 2
+ 6-bit adder : 2
+ 6-bit subtractor : 1
+ 64-bit adder : 18
+ 7-bit adder : 4
+# Registers : 127
+ 1-bit register : 29
+ 1024-bit register : 2
+ 128-bit register : 1
+ 16-bit register : 1
+ 160-bit register : 1
+ 2-bit register : 1
+ 256-bit register : 1
+ 3-bit register : 1
+ 32-bit register : 41
+ 4-bit register : 8
+ 5-bit register : 2
+ 512-bit register : 5
+ 6-bit register : 2
+ 64-bit register : 16
+ 7-bit register : 4
+ 72-bit register : 1
+ 8-bit register : 11
+# Latches : 24
+ 1-bit latch : 24
+# Comparators : 27
+ 32-bit comparator equal : 1
+ 4-bit comparator equal : 1
+ 4-bit comparator greater : 1
+ 5-bit comparator greater : 2
+ 6-bit comparator greater : 2
+ 7-bit comparator greater : 4
+ 7-bit comparator lessequal : 6
+ 8-bit comparator greater : 6
+ 8-bit comparator lessequal : 4
+# Multiplexers : 2388
+ 1-bit 2-to-1 multiplexer : 73
+ 1-bit 3-to-1 multiplexer : 1
+ 1-bit 4-to-1 multiplexer : 5
+ 10-bit 2-to-1 multiplexer : 3
+ 11-bit 2-to-1 multiplexer : 3
+ 12-bit 2-to-1 multiplexer : 3
+ 13-bit 2-to-1 multiplexer : 3
+ 14-bit 2-to-1 multiplexer : 3
+ 15-bit 2-to-1 multiplexer : 3
+ 16-bit 2-to-1 multiplexer : 7
+ 17-bit 2-to-1 multiplexer : 3
+ 18-bit 2-to-1 multiplexer : 3
+ 19-bit 2-to-1 multiplexer : 3
+ 2-bit 2-to-1 multiplexer : 5
+ 20-bit 2-to-1 multiplexer : 3
+ 21-bit 2-to-1 multiplexer : 3
+ 22-bit 2-to-1 multiplexer : 3
+ 23-bit 2-to-1 multiplexer : 3
+ 24-bit 2-to-1 multiplexer : 3
+ 25-bit 2-to-1 multiplexer : 3
+ 26-bit 2-to-1 multiplexer : 3
+ 27-bit 2-to-1 multiplexer : 3
+ 28-bit 2-to-1 multiplexer : 3
+ 29-bit 2-to-1 multiplexer : 3
+ 3-bit 2-to-1 multiplexer : 3
+ 3-bit 7-to-1 multiplexer : 1
+ 30-bit 2-to-1 multiplexer : 3
+ 31-bit 2-to-1 multiplexer : 3
+ 32-bit 16-to-1 multiplexer : 2
+ 32-bit 2-to-1 multiplexer : 2092
+ 32-bit 4-to-1 multiplexer : 4
+ 4-bit 2-to-1 multiplexer : 4
+ 5-bit 2-to-1 multiplexer : 7
+ 6-bit 2-to-1 multiplexer : 5
+ 64-bit 16-to-1 multiplexer : 1
+ 64-bit 2-to-1 multiplexer : 73
+ 7-bit 2-to-1 multiplexer : 7
+ 8-bit 16-to-1 multiplexer : 1
+ 8-bit 2-to-1 multiplexer : 30
+ 8-bit 9-to-1 multiplexer : 1
+ 9-bit 2-to-1 multiplexer : 3
+# Logic shifters : 6
+ 1024-bit shifter logical left : 1
+ 160-bit shifter logical left : 1
+ 256-bit shifter logical left : 1
+ 512-bit shifter logical left : 3
+# FSMs : 5
+# Xors : 28
+ 32-bit xor2 : 16
+ 32-bit xor4 : 1
+ 64-bit xor2 : 11
+
+=========================================================================
+INTERNAL_ERROR:Xst:cmain.c:3423:1.29 -
+
+ Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
+
+
diff --git a/novena/build/xilinx.opt b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.xst
similarity index 56%
rename from novena/build/xilinx.opt
rename to i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.xst
index 7fe9d8b..98b1be9 100644
--- a/novena/build/xilinx.opt
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.xst
@@ -1,42 +1,52 @@
--ifmt mixed
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn novena_baseline_top.prj
+-ofn novena_baseline_top
-ofmt NGC
--opt_mode speed
+-p xc6slx45-3-csg324
+-top novena_baseline_top
+-opt_mode Speed
-opt_level 1
+-power NO
-iuc NO
--keep_hierarchy no
--netlist_hierarchy as_optimized
--rtlview no
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
-glob_opt AllClockNets
--read_cores yes
+-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
--case maintain
+-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-#-dsp_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
--fsm_extract YES
--fsm_encoding Auto
--fsm_style lut
+-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
--rom_style Auto
-shreg_extract YES
+-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-#-use_dsp48 auto
+-shreg_min_size 2
+-use_dsp48 Auto
-iobuf YES
--max_fanout 500
+-max_fanout 100000
+-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
--iob auto
+-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top_summary.html b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top_summary.html
new file mode 100644
index 0000000..7b24833
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top_summary.html
@@ -0,0 +1,80 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>novena_baseline_top Project Status (02/25/2015 - 14:05:02)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>novena_reorg_i2c.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>novena_baseline_top</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Synthesized (Failed)</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx45-3csg324</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>
+No Errors</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/*.xmsgs?&DataKey=Warning'>30 Warnings (30 new)</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+ </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD> </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD> </TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD> </TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+ <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/novena_baseline_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Feb 25 14:05:01 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/_xmsgs/xst.xmsgs?&DataKey=Warning'>30 Warnings (30 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/pselkirk/cryptech/user/paul/core/i2 [...]
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+</TABLE>
+ <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 02/26/2015 - 12:17:46</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.gise b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.gise
new file mode 100644
index 0000000..a53b927
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.gise
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="novena_reorg_i2c.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="novena_baseline_top.cmd_log"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="novena_baseline_top.lso"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="novena_baseline_top.prj"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="novena_baseline_top.syr"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="novena_baseline_top.xst"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="novena_baseline_top_summary.html"/>
+ <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7735180201410500496" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="185030266866616449" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5130061521047960270" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891083" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-970702571731719349" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891102" xil_pn:in_ck="1194234190703846944" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8263288593880124464" xil_pn:start_ts="1424891083">
+ <status xil_pn:value="FailedRun"/>
+ <status xil_pn:value="WarningsGenerated"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <outfile xil_pn:name="novena_baseline_top.lso"/>
+ <outfile xil_pn:name="novena_baseline_top.prj"/>
+ <outfile xil_pn:name="novena_baseline_top.syr"/>
+ <outfile xil_pn:name="novena_baseline_top.xst"/>
+ <outfile xil_pn:name="webtalk_pn.xml"/>
+ <outfile xil_pn:name="xst"/>
+ </transform>
+ <transform xil_pn:end_ts="1424891102" xil_pn:in_ck="285930566408177000" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7504093920189949661" xil_pn:start_ts="1424891102">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
+
+</generated_project>
diff --git a/novena/iseconfig/novena_reorg_i2c/novena_reorg_i2c.xise b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
similarity index 95%
rename from novena/iseconfig/novena_reorg_i2c/novena_reorg_i2c.xise
rename to i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
index e7666bb..6e3cd35 100644
--- a/novena/iseconfig/novena_reorg_i2c/novena_reorg_i2c.xise
+++ b/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise
@@ -15,88 +15,88 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
- <file xil_pn:name="../../src/rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
- <file xil_pn:name="../../src/ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
+ <file xil_pn:name="../ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
- <file xil_pn:name="../../../core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
- <file xil_pn:name="../../../core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
- <file xil_pn:name="../../../core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
- <file xil_pn:name="../../../core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
- <file xil_pn:name="../../../coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
- <file xil_pn:name="../../../i2c/src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
- <file xil_pn:name="../../src/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <file xil_pn:name="../../../../src/rtl/i2c_regs.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
</files>
@@ -161,6 +161,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -214,7 +215,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_baseline_top" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="../../src/rtl/novena_i2c.v" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/novena_i2c.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_baseline_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/webtalk_pn.xml b/i2c/toolruns/xilinx/novena/iseconfig/webtalk_pn.xml
new file mode 100644
index 0000000..f778675
--- /dev/null
+++ b/i2c/toolruns/xilinx/novena/iseconfig/webtalk_pn.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pn" timeStamp="Wed Feb 25 14:04:43 2015">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="884D55DDED613BF5E3BBF7BC051A0A88" type="project"/>
+<property name="ProjectIteration" value="0" type="project"/>
+<property name="ProjectFile" value="/home/pselkirk/cryptech/user/paul/core/i2c/toolruns/xilinx/novena/iseconfig/novena_reorg_i2c.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2015-02-18T13:38:00" type="project"/>
+</section>
+<section name="Project Statistics" visible="true">
+<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
+<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
+<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
+<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
+<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
+<property name="PROP_SynthTopFile" value="changed" type="process"/>
+<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
+<property name="PROP_UseSmartGuide" value="false" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2015-02-18T13:38:00" type="design"/>
+<property name="PROP_intWbtProjectID" value="884D55DDED613BF5E3BBF7BC051A0A88" type="design"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
+<property name="PROP_AutoTop" value="true" type="design"/>
+<property name="PROP_DevFamily" value="Spartan6" type="design"/>
+<property name="PROP_DevDevice" value="xc6slx45" type="design"/>
+<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
+<property name="PROP_DevPackage" value="csg324" type="design"/>
+<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
+<property name="PROP_DevSpeed" value="-3" type="design"/>
+<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
+<property name="FILE_UCF" value="1" type="source"/>
+<property name="FILE_VERILOG" value="20" type="source"/>
+</section>
+</application>
+</document>
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbl b/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbl
new file mode 100644
index 0000000..1456a43
Binary files /dev/null and b/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbl differ
diff --git a/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbx b/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbx
new file mode 100644
index 0000000..9dcaa4b
Binary files /dev/null and b/i2c/toolruns/xilinx/novena/iseconfig/xst/work/work.sdbx differ
diff --git a/novena/src/rtl/novena_i2c.v b/i2c/toolruns/xilinx/novena/rtl/novena_i2c.v
similarity index 100%
copy from novena/src/rtl/novena_i2c.v
copy to i2c/toolruns/xilinx/novena/rtl/novena_i2c.v
diff --git a/novena/src/ucf/novena_i2c.ucf b/i2c/toolruns/xilinx/novena/ucf/novena_i2c.ucf
similarity index 100%
rename from novena/src/ucf/novena_i2c.ucf
rename to i2c/toolruns/xilinx/novena/ucf/novena_i2c.ucf
diff --git a/novena/build/Makefile.eim b/novena/build/Makefile.eim
deleted file mode 100644
index 6544fdd..0000000
--- a/novena/build/Makefile.eim
+++ /dev/null
@@ -1,39 +0,0 @@
-project = novena_reorg_eim
-vendor = xilinx
-family = spartan6
-part = xc6slx45csg324-3
-top_module = novena_baseline_top
-isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings64.sh
-ucf = ../src/ucf/novena_eim.ucf
-
-vfiles = \
- ../src/rtl/novena_eim.v \
- ../src/rtl/novena_clkmgr.v \
- ../src/rtl/ipcore/clkmgr_dcm.v \
- ../src/rtl/novena_regs.v \
- ../../eim/src/rtl/eim.v \
- ../../eim/src/rtl/eim_arbiter.v \
- ../../eim/src/rtl/eim_arbiter_cdc.v \
- ../../eim/src/rtl/cdc_bus_pulse.v \
- ../../eim/src/rtl/eim_da_phy.v \
- ../../eim/src/rtl/eim_indicator.v \
- ../../core_selector/src/rtl/core_selector.v \
- ../../core_selector/src/rtl/hash_selector.v \
- ../../core_selector/src/rtl/rng_selector.v \
- ../../core_selector/src/rtl/cipher_selector.v \
- ../../sha1/src/rtl/sha1.v \
- ../../sha1/src/rtl/sha1_core.v \
- ../../sha1/src/rtl/sha1_w_mem.v \
- ../../sha256/src/rtl/sha256.v \
- ../../sha256/src/rtl/sha256_core.v \
- ../../sha256/src/rtl/sha256_k_constants.v \
- ../../sha256/src/rtl/sha256_w_mem.v \
- ../../sha256/src/rtl/wb_sha256.v \
- ../../sha512/src/rtl/sha512.v \
- ../../sha512/src/rtl/sha512_core.v \
- ../../sha512/src/rtl/sha512_h_constants.v \
- ../../sha512/src/rtl/sha512_k_constants.v \
- ../../sha512/src/rtl/sha512_w_mem.v
-
-include xilinx.mk
diff --git a/novena/build/Makefile.i2c b/novena/build/Makefile.i2c
deleted file mode 100644
index 267e33b..0000000
--- a/novena/build/Makefile.i2c
+++ /dev/null
@@ -1,36 +0,0 @@
-project = novena_reorg_i2c
-vendor = xilinx
-family = spartan6
-part = xc6slx45csg324-3
-top_module = novena_baseline_top
-isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings64.sh
-ucf = ../src/ucf/novena_i2c.ucf
-
-vfiles = \
- ../src/rtl/novena_i2c.v \
- ../src/rtl/novena_clkmgr.v \
- ../src/rtl/ipcore/clkmgr_dcm.v \
- ../src/rtl/novena_regs.v \
- ../../i2c/src/rtl/i2c.v \
- ../../i2c/src/rtl/i2c_core.v \
- ../../coretest/src/rtl/coretest.v \
- ../../core_selector/src/rtl/core_selector.v \
- ../../core_selector/src/rtl/hash_selector.v \
- ../../core_selector/src/rtl/rng_selector.v \
- ../../core_selector/src/rtl/cipher_selector.v \
- ../../sha1/src/rtl/sha1.v \
- ../../sha1/src/rtl/sha1_core.v \
- ../../sha1/src/rtl/sha1_w_mem.v \
- ../../sha256/src/rtl/sha256.v \
- ../../sha256/src/rtl/sha256_core.v \
- ../../sha256/src/rtl/sha256_k_constants.v \
- ../../sha256/src/rtl/sha256_w_mem.v \
- ../../sha256/src/rtl/wb_sha256.v \
- ../../sha512/src/rtl/sha512.v \
- ../../sha512/src/rtl/sha512_core.v \
- ../../sha512/src/rtl/sha512_h_constants.v \
- ../../sha512/src/rtl/sha512_k_constants.v \
- ../../sha512/src/rtl/sha512_w_mem.v
-
-include xilinx.mk
diff --git a/novena/src/rtl/novena_regs.v b/novena/src/rtl/novena_regs.v
deleted file mode 100644
index 7341092..0000000
--- a/novena/src/rtl/novena_regs.v
+++ /dev/null
@@ -1,126 +0,0 @@
-//======================================================================
-//
-// novena_regs.v
-// -------------
-// Global registers for the Cryptech Novena FPGA framework.
-//
-//
-// Author: Pavel Shatov
-// Copyright (c) 2015, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-`timescale 1ns / 1ps
-
-module novena_regs
- (
- input wire clk,
- input wire rst,
-
- input wire cs,
- input wire we,
-
- input wire [ 7 : 0] address,
- input wire [31 : 0] write_data,
- output wire [31 : 0] read_data
- );
-
-
- //----------------------------------------------------------------
- // Board-Level Registers
- //----------------------------------------------------------------
- localparam ADDR_BOARD_TYPE = 8'h00; // board id
- localparam ADDR_FIRMWARE_VER = 8'h01; // bitstream version
- localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
-
-
- //----------------------------------------------------------------
- // Constants
- //----------------------------------------------------------------
- localparam NOVENA_BOARD_TYPE = 32'h50565431; // PVT1
- localparam NOVENA_DESIGN_VER = 32'h00_01_00_0b; // v0.1.0b
-
-
- //
- // Output Register
- //
- reg [31: 0] tmp_read_data;
- assign read_data = tmp_read_data;
-
-
- /* This dummy register can be used by users to check that they can actually
- * write something.
- */
-
- reg [31: 0] reg_dummy;
-
-
- //
- // Access Handler
- //
- always @(posedge clk)
- //
- if (rst)
- reg_dummy <= {32{1'b0}};
- else if (cs) begin
- //
- if (we) begin
- //
- // WRITE handler
- //
- case (address)
- ADDR_DUMMY_REG:
- reg_dummy <= write_data;
- endcase
- //
- end else begin
- //
- // READ handler
- //
- case (address)
- ADDR_BOARD_TYPE:
- tmp_read_data <= NOVENA_BOARD_TYPE;
- ADDR_FIRMWARE_VER:
- tmp_read_data <= NOVENA_DESIGN_VER;
- ADDR_DUMMY_REG:
- tmp_read_data <= reg_dummy;
- //
- default:
- tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- endcase
- //
- end
- //
- end
-
-endmodule
-
-//======================================================================
-// EOF novena_regs.v
-//======================================================================
diff --git a/uart/LICENSE b/uart/LICENSE
new file mode 100644
index 0000000..0fb159c
--- /dev/null
+++ b/uart/LICENSE
@@ -0,0 +1,24 @@
+Author: Joachim Strömbergson
+Copyright (c) 2014, SUNET
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/uart/README.md b/uart/README.md
new file mode 100644
index 0000000..513ccf0
--- /dev/null
+++ b/uart/README.md
@@ -0,0 +1,14 @@
+uart
+====
+
+A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.
+
+This UART used to be in coretest, but has been moved out as a separate
+project.
+
+The current implementation supports the ability to set the bit rate as
+well as number of data- and stop bits by writing to control addresses
+via the control interface.
+
+
+
diff --git a/uart/src/rtl/uart_core.v b/uart/src/rtl/uart_core.v
new file mode 100644
index 0000000..e2f2108
--- /dev/null
+++ b/uart/src/rtl/uart_core.v
@@ -0,0 +1,581 @@
+//======================================================================
+//
+// uart_core.v
+// -----------
+// A simple universal asynchronous receiver/transmitter (UART)
+// interface. The interface contains 16 byte wide transmit and
+// receivea buffers and can handle start and stop bits. But in
+// general is rather simple. The primary purpose is as host
+// interface for the coretest design. The core also has a
+// loopback mode to allow testing of a serial link.
+//
+// Note that the UART has a separate API interface to allow
+// a control core to change settings such as speed. But the core
+// has default values to allow it to start operating directly
+// after reset. No config should be needed.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module uart_core(
+ input wire clk,
+ input wire reset_n,
+
+ // External data interface
+ input wire rxd,
+ output wire txd,
+
+ // Internal receive interface.
+ output wire rxd_syn,
+ output [7 : 0] rxd_data,
+ input wire rxd_ack,
+
+ // Internal transmit interface.
+ input wire txd_syn,
+ input wire [7 : 0] txd_data,
+ output wire txd_ack
+ );
+
+
+ //----------------------------------------------------------------
+ // Configuration parameters
+ //----------------------------------------------------------------
+ wire [15 : 0] bit_rate = terasic_top.cores.hashes.comm_regs.bit_rate;
+ wire [3 : 0] data_bits = terasic_top.cores.hashes.comm_regs.data_bits;
+ wire [1 : 0] stop_bits = terasic_top.cores.hashes.comm_regs.stop_bits;
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter ERX_IDLE = 0;
+ parameter ERX_START = 1;
+ parameter ERX_BITS = 2;
+ parameter ERX_STOP = 3;
+ parameter ERX_SYN = 4;
+
+ parameter ETX_IDLE = 0;
+ parameter ETX_ACK = 1;
+ parameter ETX_START = 2;
+ parameter ETX_BITS = 3;
+ parameter ETX_STOP = 4;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg rxd_reg;
+
+ reg [7 : 0] rxd_byte_reg;
+ reg rxd_byte_we;
+
+ reg [4 : 0] rxd_bit_ctr_reg;
+ reg [4 : 0] rxd_bit_ctr_new;
+ reg rxd_bit_ctr_we;
+ reg rxd_bit_ctr_rst;
+ reg rxd_bit_ctr_inc;
+
+ reg [15 : 0] rxd_bitrate_ctr_reg;
+ reg [15 : 0] rxd_bitrate_ctr_new;
+ reg rxd_bitrate_ctr_we;
+ reg rxd_bitrate_ctr_rst;
+ reg rxd_bitrate_ctr_inc;
+
+ reg rxd_syn_reg;
+ reg rxd_syn_new;
+ reg rxd_syn_we;
+
+ reg [2 : 0] erx_ctrl_reg;
+ reg [2 : 0] erx_ctrl_new;
+ reg erx_ctrl_we;
+
+ reg txd_reg;
+ reg txd_new;
+ reg txd_we;
+
+ reg [7 : 0] txd_byte_reg;
+ reg [7 : 0] txd_byte_new;
+ reg txd_byte_we;
+
+ reg [4 : 0] txd_bit_ctr_reg;
+ reg [4 : 0] txd_bit_ctr_new;
+ reg txd_bit_ctr_we;
+ reg txd_bit_ctr_rst;
+ reg txd_bit_ctr_inc;
+
+ reg [15 : 0] txd_bitrate_ctr_reg;
+ reg [15 : 0] txd_bitrate_ctr_new;
+ reg txd_bitrate_ctr_we;
+ reg txd_bitrate_ctr_rst;
+ reg txd_bitrate_ctr_inc;
+
+ reg txd_ack_reg;
+ reg txd_ack_new;
+ reg txd_ack_we;
+
+ reg [2 : 0] etx_ctrl_reg;
+ reg [2 : 0] etx_ctrl_new;
+ reg etx_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire [15 : 0] half_bit_rate;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign txd = txd_reg;
+ assign rxd_syn = rxd_syn_reg;
+ assign rxd_data = rxd_byte_reg;
+ assign txd_ack = txd_ack_reg;
+
+ assign half_bit_rate = {1'b0, bit_rate[15 : 1]};
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //
+ // Update functionality for all registers in the core.
+ // All registers are positive edge triggered with
+ // asynchronous active low reset.
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin: reg_update
+ if (!reset_n)
+ begin
+ rxd_reg <= 0;
+ rxd_byte_reg <= 8'h00;
+ rxd_bit_ctr_reg <= 4'h0;
+ rxd_bitrate_ctr_reg <= 16'h0000;
+ rxd_syn_reg <= 0;
+ erx_ctrl_reg <= ERX_IDLE;
+
+ txd_reg <= 1;
+ txd_byte_reg <= 8'h00;
+ txd_bit_ctr_reg <= 4'h0;
+ txd_bitrate_ctr_reg <= 16'h0000;
+ txd_ack_reg <= 0;
+ etx_ctrl_reg <= ETX_IDLE;
+ end
+ else
+ begin
+ // We sample the rx input port every cycle.
+ rxd_reg <= rxd;
+
+ // We shift the rxd bit into msb.
+ if (rxd_byte_we)
+ begin
+ rxd_byte_reg <= {rxd_reg, rxd_byte_reg[7 : 1]};
+ end
+
+ if (rxd_bit_ctr_we)
+ begin
+ rxd_bit_ctr_reg <= rxd_bit_ctr_new;
+ end
+
+ if (rxd_bitrate_ctr_we)
+ begin
+ rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
+ end
+
+ if (rxd_syn_we)
+ begin
+ rxd_syn_reg <= rxd_syn_new;
+ end
+
+ if (erx_ctrl_we)
+ begin
+ erx_ctrl_reg <= erx_ctrl_new;
+ end
+
+ if (txd_we)
+ begin
+ txd_reg <= txd_new;
+ end
+
+ if (txd_byte_we)
+ begin
+ txd_byte_reg <= txd_byte_new;
+ end
+
+ if (txd_bit_ctr_we)
+ begin
+ txd_bit_ctr_reg <= txd_bit_ctr_new;
+ end
+
+ if (txd_bitrate_ctr_we)
+ begin
+ txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
+ end
+
+ if (txd_ack_we)
+ begin
+ txd_ack_reg <= txd_ack_new;
+ end
+
+ if (etx_ctrl_we)
+ begin
+ etx_ctrl_reg <= etx_ctrl_new;
+ end
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // rxd_bit_ctr
+ //
+ // Bit counter for receiving data on the external
+ // serial interface.
+ //----------------------------------------------------------------
+ always @*
+ begin: rxd_bit_ctr
+ rxd_bit_ctr_new = 4'h0;
+ rxd_bit_ctr_we = 0;
+
+ if (rxd_bit_ctr_rst)
+ begin
+ rxd_bit_ctr_new = 4'h0;
+ rxd_bit_ctr_we = 1;
+ end
+
+ else if (rxd_bit_ctr_inc)
+ begin
+ rxd_bit_ctr_new = rxd_bit_ctr_reg + 4'b0001;
+ rxd_bit_ctr_we = 1;
+ end
+ end // rxd_bit_ctr
+
+
+ //----------------------------------------------------------------
+ // rxd_bitrate_ctr
+ //
+ // Bitrate counter for receiving data on the external
+ // serial interface.
+ //----------------------------------------------------------------
+ always @*
+ begin: rxd_bitrate_ctr
+ rxd_bitrate_ctr_new = 16'h0000;
+ rxd_bitrate_ctr_we = 0;
+
+ if (rxd_bitrate_ctr_rst)
+ begin
+ rxd_bitrate_ctr_new = 16'h0000;
+ rxd_bitrate_ctr_we = 1;
+ end
+
+ else if (rxd_bitrate_ctr_inc)
+ begin
+ rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 16'h0001;
+ rxd_bitrate_ctr_we = 1;
+ end
+ end // rxd_bitrate_ctr
+
+
+
+ //----------------------------------------------------------------
+ // txd_bit_ctr
+ //
+ // Bit counter for transmitting data on the external
+ // serial interface.
+ //----------------------------------------------------------------
+ always @*
+ begin: txd_bit_ctr
+ txd_bit_ctr_new = 4'h0;
+ txd_bit_ctr_we = 0;
+
+ if (txd_bit_ctr_rst)
+ begin
+ txd_bit_ctr_new = 4'h0;
+ txd_bit_ctr_we = 1;
+ end
+
+ else if (txd_bit_ctr_inc)
+ begin
+ txd_bit_ctr_new = txd_bit_ctr_reg + 4'b0001;
+ txd_bit_ctr_we = 1;
+ end
+ end // txd_bit_ctr
+
+
+ //----------------------------------------------------------------
+ // txd_bitrate_ctr
+ //
+ // Bitrate counter for transmitting data on the external
+ // serial interface.
+ //----------------------------------------------------------------
+ always @*
+ begin: txd_bitrate_ctr
+ txd_bitrate_ctr_new = 16'h0000;
+ txd_bitrate_ctr_we = 0;
+
+ if (txd_bitrate_ctr_rst)
+ begin
+ txd_bitrate_ctr_new = 16'h0000;
+ txd_bitrate_ctr_we = 1;
+ end
+
+ else if (txd_bitrate_ctr_inc)
+ begin
+ txd_bitrate_ctr_new = txd_bitrate_ctr_reg + 16'h0001;
+ txd_bitrate_ctr_we = 1;
+ end
+ end // txd_bitrate_ctr
+
+
+ //----------------------------------------------------------------
+ // external_rx_engine
+ //
+ // Logic that implements the receive engine towards
+ // the external interface. Detects incoming data, collects it,
+ // if required checks parity and store correct data into
+ // the rx buffer.
+ //----------------------------------------------------------------
+ always @*
+ begin: external_rx_engine
+ rxd_bit_ctr_rst = 0;
+ rxd_bit_ctr_inc = 0;
+ rxd_bitrate_ctr_rst = 0;
+ rxd_bitrate_ctr_inc = 0;
+ rxd_byte_we = 0;
+ rxd_syn_new = 0;
+ rxd_syn_we = 0;
+ erx_ctrl_new = ERX_IDLE;
+ erx_ctrl_we = 0;
+
+ case (erx_ctrl_reg)
+ ERX_IDLE:
+ begin
+ if (!rxd_reg)
+ begin
+ // Possible start bit detected.
+ rxd_bitrate_ctr_rst = 1;
+ erx_ctrl_new = ERX_START;
+ erx_ctrl_we = 1;
+ end
+ end
+
+
+ ERX_START:
+ begin
+ rxd_bitrate_ctr_inc = 1;
+ if (rxd_reg)
+ begin
+ // Just a glitch.
+ erx_ctrl_new = ERX_IDLE;
+ erx_ctrl_we = 1;
+ end
+ else
+ begin
+ if (rxd_bitrate_ctr_reg == half_bit_rate)
+ begin
+ // start bit assumed. We start sampling data.
+ rxd_bit_ctr_rst = 1;
+ rxd_bitrate_ctr_rst = 1;
+ erx_ctrl_new = ERX_BITS;
+ erx_ctrl_we = 1;
+ end
+ end
+ end
+
+
+ ERX_BITS:
+ begin
+ if (rxd_bitrate_ctr_reg < bit_rate)
+ begin
+ rxd_bitrate_ctr_inc = 1;
+ end
+ else
+ begin
+ rxd_byte_we = 1;
+ rxd_bit_ctr_inc = 1;
+ rxd_bitrate_ctr_rst = 1;
+ if (rxd_bit_ctr_reg == data_bits - 1)
+ begin
+ erx_ctrl_new = ERX_STOP;
+ erx_ctrl_we = 1;
+ end
+ end
+ end
+
+
+ ERX_STOP:
+ begin
+ rxd_bitrate_ctr_inc = 1;
+ if (rxd_bitrate_ctr_reg == bit_rate * stop_bits)
+ begin
+ rxd_syn_new = 1;
+ rxd_syn_we = 1;
+ erx_ctrl_new = ERX_SYN;
+ erx_ctrl_we = 1;
+ end
+ end
+
+
+ ERX_SYN:
+ begin
+ if (rxd_ack)
+ begin
+ rxd_syn_new = 0;
+ rxd_syn_we = 1;
+ erx_ctrl_new = ERX_IDLE;
+ erx_ctrl_we = 1;
+ end
+ end
+
+
+ default:
+ begin
+
+ end
+ endcase // case (erx_ctrl_reg)
+ end // external_rx_engine
+
+
+ //----------------------------------------------------------------
+ // external_tx_engine
+ //
+ // Logic that implements the transmit engine towards
+ // the external interface.
+ //----------------------------------------------------------------
+ always @*
+ begin: external_tx_engine
+ txd_new = 0;
+ txd_we = 0;
+ txd_byte_new = 0;
+ txd_byte_we = 0;
+ txd_bit_ctr_rst = 0;
+ txd_bit_ctr_inc = 0;
+ txd_bitrate_ctr_rst = 0;
+ txd_bitrate_ctr_inc = 0;
+ txd_ack_new = 0;
+ txd_ack_we = 0;
+ etx_ctrl_new = ETX_IDLE;
+ etx_ctrl_we = 0;
+
+ case (etx_ctrl_reg)
+ ETX_IDLE:
+ begin
+ txd_new = 1;
+ txd_we = 1;
+ if (txd_syn)
+ begin
+ txd_byte_new = txd_data;
+ txd_byte_we = 1;
+ txd_ack_new = 1;
+ txd_ack_we = 1;
+ txd_bitrate_ctr_rst = 1;
+ etx_ctrl_new = ETX_ACK;
+ etx_ctrl_we = 1;
+ end
+ end
+
+
+ ETX_ACK:
+ begin
+ if (!txd_syn)
+ begin
+ txd_new = 0;
+ txd_we = 1;
+ txd_ack_new = 0;
+ txd_ack_we = 1;
+ etx_ctrl_new = ETX_START;
+ etx_ctrl_we = 1;
+ end
+ end
+
+ ETX_START:
+ begin
+ if (txd_bitrate_ctr_reg == bit_rate)
+ begin
+ txd_bit_ctr_rst = 1;
+ etx_ctrl_new = ETX_BITS;
+ etx_ctrl_we = 1;
+ end
+ else
+ begin
+ txd_bitrate_ctr_inc = 1;
+ end
+ end
+
+
+ ETX_BITS:
+ begin
+ if (txd_bitrate_ctr_reg < bit_rate)
+ begin
+ txd_bitrate_ctr_inc = 1;
+ end
+ else
+ begin
+ txd_bitrate_ctr_rst = 1;
+
+ if (txd_bit_ctr_reg == data_bits)
+ begin
+ txd_new = 1;
+ txd_we = 1;
+ etx_ctrl_new = ETX_STOP;
+ etx_ctrl_we = 1;
+ end
+ else
+ begin
+ txd_new = txd_byte_reg[txd_bit_ctr_reg];
+ txd_we = 1;
+ txd_bit_ctr_inc = 1;
+ end
+ end
+ end
+
+
+ ETX_STOP:
+ begin
+ txd_bitrate_ctr_inc = 1;
+ if (txd_bitrate_ctr_reg == bit_rate * stop_bits)
+ begin
+ etx_ctrl_new = ETX_IDLE;
+ etx_ctrl_we = 1;
+ end
+ end
+
+
+ default:
+ begin
+
+ end
+ endcase // case (etx_ctrl_reg)
+ end // external_tx_engine
+
+endmodule // uart
+
+//======================================================================
+// EOF uart.v
+//======================================================================
diff --git a/uart/src/rtl/uart_regs.v b/uart/src/rtl/uart_regs.v
new file mode 100644
index 0000000..7c38306
--- /dev/null
+++ b/uart/src/rtl/uart_regs.v
@@ -0,0 +1,155 @@
+//======================================================================
+//
+// uart.v
+// ------
+// Top level wrapper for the uart core.
+//
+// A simple UART interface.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module comm_regs
+ (
+ input wire clk,
+ input wire rst,
+
+ input wire cs,
+ input wire we,
+
+ input wire [ 7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ // API addresses.
+ localparam ADDR_CORE_NAME0 = 8'h00;
+ localparam ADDR_CORE_NAME1 = 8'h01;
+ localparam ADDR_CORE_TYPE = 8'h02;
+ localparam ADDR_CORE_VERSION = 8'h03;
+
+ localparam ADDR_BIT_RATE = 8'h10;
+ localparam ADDR_DATA_BITS = 8'h11;
+ localparam ADDR_STOP_BITS = 8'h12;
+
+ // Core ID constants.
+ localparam CORE_NAME0 = 32'h75617274; // "uart"
+ localparam CORE_NAME1 = 32'h20202020; // " "
+ localparam CORE_TYPE = 32'h20202031; // " 1"
+ localparam CORE_VERSION = 32'h302e3031; // "0.01"
+
+ // The default bit rate is based on target clock frequency
+ // divided by the bit rate times in order to hit the
+ // center of the bits. I.e.
+ // Clock: 50 MHz, 9600 bps
+ // Divisor = 50*10E6 / 9600 = 5208
+ localparam DEFAULT_BIT_RATE = 16'd5208;
+ localparam DEFAULT_DATA_BITS = 4'h8;
+ localparam DEFAULT_STOP_BITS = 2'h1;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [31: 0] tmp_read_data;
+
+ reg [15 : 0] bit_rate;
+ reg [3 : 0] data_bits;
+ reg [1 : 0] stop_bits;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+
+
+ //----------------------------------------------------------------
+ // Access Handler
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ //
+ if (rst) begin
+ bit_rate <= DEFAULT_BIT_RATE;
+ data_bits <= DEFAULT_DATA_BITS;
+ stop_bits <= DEFAULT_STOP_BITS;
+ end
+ else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_BIT_RATE:
+ bit_rate <= write_data[15 : 0];
+ ADDR_DATA_BITS:
+ data_bits <= write_data[3 : 0];
+ ADDR_STOP_BITS:
+ stop_bits <= write_data[1 : 0];
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_CORE_NAME0:
+ tmp_read_data = CORE_NAME0;
+ ADDR_CORE_NAME1:
+ tmp_read_data = CORE_NAME1;
+ ADDR_CORE_TYPE:
+ tmp_read_data = CORE_TYPE;
+ ADDR_CORE_VERSION:
+ tmp_read_data = CORE_VERSION;
+ ADDR_BIT_RATE:
+ tmp_read_data = {16'h0000, bit_rate};
+ ADDR_DATA_BITS:
+ tmp_read_data = {28'h0000000, data_bits};
+ ADDR_STOP_BITS:
+ tmp_read_data = {30'h0000000, stop_bits};
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
+endmodule // uart
+
+//======================================================================
+// EOF uart.v
+//======================================================================
diff --git a/uart/src/sw/seriedebug.py b/uart/src/sw/seriedebug.py
new file mode 100755
index 0000000..44abf2a
--- /dev/null
+++ b/uart/src/sw/seriedebug.py
@@ -0,0 +1,113 @@
+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+#=======================================================================
+#
+# seriedebug.py
+# -------------
+# Program that sends test bytes onto the serial link and print out
+# any response.
+#
+# Note: This proram requires the PySerial module.
+# http://pyserial.sourceforge.net/
+#
+#
+# Author: Joachim Strömbergson
+# Copyright (c) 2014 SUNET
+#
+# Redistribution and use in source and binary forms, with or
+# without modification, are permitted provided that the following
+# conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=======================================================================
+
+#-------------------------------------------------------------------
+# Python module imports.
+#-------------------------------------------------------------------
+import sys
+import serial
+
+
+#-------------------------------------------------------------------
+# main()
+#
+# Parse arguments.
+#-------------------------------------------------------------------
+def main():
+ print "Seriedebug started..."
+ print
+
+ verbose = True
+
+ ser = serial.Serial()
+ ser.port='/dev/cu.usbserial-A801SA6T'
+ ser.baudrate=9600
+ ser.bytesize=8
+ ser.parity='N'
+ ser.stopbits=1
+ ser.timeout=1
+ ser.writeTimeout=0
+
+ # Open the interface.
+ ser.open()
+ if verbose:
+ print "Opening device."
+
+ # Send a byte and try to get the response.
+ testdata = ['\xab', '\xaa', '\x00', '\x01', '\xf1', '\x0f', '\xff', '\x07']
+ for tx_byte in testdata:
+ ser.write(tx_byte)
+ if verbose:
+ print "transmitting byte 0x%02x" % ord(tx_byte)
+
+
+ if verbose:
+ print "Waiting for response..."
+
+ for i in range(8):
+ response = ""
+ while not len(response):
+ response = ser.read()
+ if len(response):
+ print "received response: 0x%02x" % ord(response)
+
+
+
+ # Exit nicely.
+ if verbose:
+ print "Done. Closing device."
+ ser.close()
+
+
+#-------------------------------------------------------------------
+# __name__
+# Python thingy which allows the file to be run standalone as
+# well as parsed from within a Python interpreter.
+#-------------------------------------------------------------------
+if __name__=="__main__":
+ # Run the main function.
+ sys.exit(main())
+
+#=======================================================================
+# EOF seriedebug.py
+#=======================================================================
diff --git a/uart/src/tb/tb_uart.v b/uart/src/tb/tb_uart.v
new file mode 100644
index 0000000..1abdd34
--- /dev/null
+++ b/uart/src/tb/tb_uart.v
@@ -0,0 +1,394 @@
+//======================================================================
+//
+// tb_uart.v
+// ---------
+// Testbench for the UART core.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014, SUNET
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/10ps
+
+module tb_uart();
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter DEBUG = 0;
+ parameter VERBOSE = 0;
+
+ parameter CLK_HALF_PERIOD = 1;
+ parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_rxd;
+ wire tb_txd;
+ wire tb_rxd_syn;
+ wire [7 : 0] tb_rxd_data;
+ wire tb_rxd_ack;
+ wire tb_txd_syn;
+ wire [7 : 0] tb_txd_data;
+ wire tb_txd_ack;
+ reg tb_cs;
+ reg tb_we;
+ reg [7 : 0] tb_address;
+ reg [31 : 0] tb_write_data;
+ wire [31 : 0] tb_read_data;
+ wire tb_error;
+ wire [7 : 0] tb_debug;
+
+ reg txd_state;
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ uart dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .rxd(tb_rxd),
+ .txd(tb_txd),
+
+ .rxd_syn(tb_rxd_syn),
+ .rxd_data(tb_rxd_data),
+ .rxd_ack(tb_rxd_ack),
+
+ // Internal transmit interface.
+ .txd_syn(tb_txd_syn),
+ .txd_data(tb_txd_data),
+ .txd_ack(tb_txd_ack),
+
+ // API interface.
+ .cs(tb_cs),
+ .we(tb_we),
+ .address(tb_address),
+ .write_data(tb_write_data),
+ .read_data(tb_read_data),
+ .error(tb_error),
+
+ .debug(tb_debug)
+ );
+
+ //----------------------------------------------------------------
+ // Concurrent assignments.
+ //----------------------------------------------------------------
+ // We connect the internal facing ports on the dut together.
+ assign tb_txd_syn = tb_rxd_syn;
+ assign tb_txd_data = tb_rxd_data;
+ assign tb_rxd_ack = tb_txd_ack;
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //----------------------------------------------------------------
+ // sys_monitor
+ //----------------------------------------------------------------
+ always
+ begin : sys_monitor
+ #(CLK_PERIOD);
+ if (DEBUG)
+ begin
+ dump_rx_state();
+ dump_tx_state();
+ $display("");
+ end
+ if (VERBOSE)
+ begin
+ $display("cycle: 0x%016x", cycle_ctr);
+ end
+ cycle_ctr = cycle_ctr + 1;
+ end
+
+
+ //----------------------------------------------------------------
+ // tx_monitor
+ //
+ // Observes what happens on the dut tx port and reports it.
+ //----------------------------------------------------------------
+ always @*
+ begin : tx_monitor
+ if ((!tb_txd) && txd_state)
+ begin
+ $display("txd going low.");
+ txd_state = 0;
+ end
+
+ if (tb_txd && (!txd_state))
+ begin
+ $display("txd going high");
+ txd_state = 1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
+ // dump_dut_state()
+ //
+ // Dump the state of the dut when needed.
+ //----------------------------------------------------------------
+ task dump_dut_state();
+ begin
+ $display("State of DUT");
+ $display("------------");
+ $display("Inputs and outputs:");
+ $display("rxd = 0x%01x, txd = 0x%01x,",
+ dut.core.rxd, dut.core.txd);
+ $display("");
+
+ $display("Sample and data registers:");
+ $display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x",
+ dut.core.rxd_reg, dut.core.rxd_byte_reg);
+ $display("");
+
+ $display("Counters:");
+ $display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x",
+ dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg);
+ $display("");
+
+
+ $display("Control signals and FSM state:");
+ $display("erx_ctrl_reg = 0x%02x",
+ dut.core.erx_ctrl_reg);
+ $display("");
+ end
+ endtask // dump_dut_state
+
+
+
+ //----------------------------------------------------------------
+ // dump_rx_state()
+ //
+ // Dump the state of the rx engine.
+ //----------------------------------------------------------------
+ task dump_rx_state();
+ begin
+ $display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
+ dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg,
+ dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg);
+ end
+ endtask // dump_dut_state
+
+
+
+ //----------------------------------------------------------------
+ // dump_tx_state()
+ //
+ // Dump the state of the tx engine.
+ //----------------------------------------------------------------
+ task dump_tx_state();
+ begin
+ $display("txd = 0x%01x, txd_reg = 0x%01x, txd_byte_reg = 0x%01x, txd_bit_ctr_reg = 0x%01x, txd_bitrate_ctr_reg = 0x%02x, txd_ack = 0x%01x, etx_ctrl_reg = 0x%02x",
+ dut.core.txd, dut.core.txd_reg, dut.core.txd_byte_reg, dut.core.txd_bit_ctr_reg,
+ dut.core.txd_bitrate_ctr_reg, dut.core.txd_ack, dut.core.etx_ctrl_reg);
+ end
+ endtask // dump_dut_state
+
+
+ //----------------------------------------------------------------
+ // reset_dut()
+ //----------------------------------------------------------------
+ task reset_dut();
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(2 * CLK_PERIOD);
+ tb_reset_n = 1;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // init_sim()
+ //
+ // Initialize all counters and testbed functionality as well
+ // as setting the DUT inputs to defined values.
+ //----------------------------------------------------------------
+ task init_sim();
+ begin
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
+ tb_rxd = 1;
+ tb_cs = 0;
+ tb_we = 0;
+ tb_address = 8'h00;
+ tb_write_data = 32'h00000000;
+
+ txd_state = 1;
+ end
+ endtask // init_sim
+
+
+ //----------------------------------------------------------------
+ // transmit_byte
+ //
+ // Transmit a byte of data to the DUT receive port.
+ //----------------------------------------------------------------
+ task transmit_byte(input [7 : 0] data);
+ integer i;
+ begin
+ $display("*** Transmitting byte 0x%02x to the dut.", data);
+
+ #10;
+
+ // Start bit
+ $display("*** Transmitting start bit.");
+ tb_rxd = 0;
+ #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
+
+ // Send the bits LSB first.
+ for (i = 0 ; i < 8 ; i = i + 1)
+ begin
+ $display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
+ tb_rxd = data[i];
+ #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
+ end
+
+ // Send two stop bits. I.e. two bit times high (mark) value.
+ $display("*** Transmitting two stop bits.");
+ tb_rxd = 1;
+ #(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS);
+ $display("*** End of transmission.");
+ end
+ endtask // transmit_byte
+
+
+ //----------------------------------------------------------------
+ // check_transmit
+ //
+ // Transmits a byte and checks that it was captured internally
+ // by the dut.
+ //----------------------------------------------------------------
+ task check_transmit(input [7 : 0] data);
+ begin
+ tc_ctr = tc_ctr + 1;
+
+ transmit_byte(data);
+
+ if (dut.core.rxd_byte_reg == data)
+ begin
+ $display("*** Correct data: 0x%01x captured by the dut.",
+ dut.core.rxd_byte_reg);
+ end
+ else
+ begin
+ $display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
+ dut.core.rxd_byte_reg, data);
+ error_ctr = error_ctr + 1;
+ end
+ end
+ endtask // check_transmit
+
+
+ //----------------------------------------------------------------
+ // test_transmit
+ //
+ // Transmit a number of test bytes to the dut.
+ //----------------------------------------------------------------
+ task test_transmit();
+ begin
+ check_transmit(8'h55);
+ check_transmit(8'h42);
+ check_transmit(8'hde);
+ check_transmit(8'had);
+ end
+ endtask // test_transmit
+
+
+ //----------------------------------------------------------------
+ // display_test_result()
+ //
+ // Display the accumulated test results.
+ //----------------------------------------------------------------
+ task display_test_result();
+ begin
+ if (error_ctr == 0)
+ begin
+ $display("*** All %02d test cases completed successfully", tc_ctr);
+ end
+ else
+ begin
+ $display("*** %02d test cases did not complete successfully.", error_ctr);
+ end
+ end
+ endtask // display_test_result
+
+
+ //----------------------------------------------------------------
+ // uart_test
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : uart_test
+ $display(" -- Testbench for uart core started --");
+
+ init_sim();
+ dump_dut_state();
+ reset_dut();
+ dump_dut_state();
+
+ test_transmit();
+
+ display_test_result();
+ $display("*** Simulation done.");
+ $finish;
+ end // uart_test
+endmodule // tb_uart
+
+//======================================================================
+// EOF tb_uart.v
+//======================================================================
diff --git a/uart/toolruns/Makefile b/uart/toolruns/Makefile
new file mode 100755
index 0000000..f088e86
--- /dev/null
+++ b/uart/toolruns/Makefile
@@ -0,0 +1,70 @@
+#===================================================================
+#
+# Makefile
+# --------
+# Makefile for building uart core simulations.
+#
+#
+# Author: Joachim Strombergson
+# Copyright (c) 2014, SUNET
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or
+# without modification, are permitted provided that the following
+# conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#===================================================================
+
+UART_SRC=../src/rtl/uart.v ../src/rtl/uart_core.v
+UART_TB_SRC=../src/tb/tb_uart.v
+
+CC=iverilog
+
+
+all: uart
+
+
+uart: $(UART_TB_SRC) $(UART_SRC)
+ $(CC) -o uart.sim $(UART_TB_SRC) $(UART_SRC)
+
+sim-uart: uart.sim
+ ./uart.sim
+
+
+clean:
+ rm -f uart.sim
+
+
+help:
+ @echo "Supported targets:"
+ @echo "------------------"
+ @echo "all: Build all simulation targets."
+ @echo "uart: Build the uart simulation target."
+ @echo "sim-uart: Run the uart simulation."
+ @echo "clean: Delete all built files."
+
+#===================================================================
+# EOF Makefile
+#===================================================================
+
diff --git a/uart/toolruns/quartus/terasic_c5g/coretest_hashes.qpf b/uart/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
new file mode 100644
index 0000000..6f25a8f
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/coretest_hashes.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+# Date created = 16:43:44 February 25, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.1"
+DATE = "16:43:44 February 25, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "terasic_top"
diff --git a/uart/toolruns/quartus/terasic_c5g/db/prev_cmp_coretest_hashes.qmsg b/uart/toolruns/quartus/terasic_c5g/db/prev_cmp_coretest_hashes.qmsg
new file mode 100644
index 0000000..f927b8f
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/prev_cmp_coretest_hashes.qmsg
@@ -0,0 +1,40 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424902181090 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.1.0 Build 186 12/03/2014 SJ Web Edition " "Version 14.1.0 Build 186 12/03/2014 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424902181091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 25 17:09:40 2015 " "Processing started: Wed Feb 25 17:09:40 2015" { } { } 0 0 "Processing started: %1!s!" 0 [...]
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1424902181091 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1424902181427 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_w_mem " "Found entity 1: sha512_w_mem" { } { { "../../../../sha512/src/rtl/sha512_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v" 40 -1 0 } } } 0 12023 " [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_k_constants " "Found entity 1: sha512_k_constants" { } { { "../../../../sha512/src/rtl/sha512_k_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_h_constants " "Found entity 1: sha512_h_constants" { } { { "../../../../sha512/src/rtl/sha512_h_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_core " "Found entity 1: sha512_core" { } { { "../../../../sha512/src/rtl/sha512_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" 40 -1 0 } } } 0 12023 "Found [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha512.v(78) " "Verilog HDL Declaration information at sha512.v(78): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 78 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha512.v(79) " "Verilog HDL Declaration information at sha512.v(79): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 79 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha512.v(80) " "Verilog HDL Declaration information at sha512.v(80): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 80 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in th [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512 " "Found entity 1: sha512" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quar [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_w_mem " "Found entity 1: sha256_w_mem" { } { { "../../../../sha256/src/rtl/sha256_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v" 39 -1 0 } } } 0 12023 " [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_k_constants " "Found entity 1: sha256_k_constants" { } { { "../../../../sha256/src/rtl/sha256_k_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_core " "Found entity 1: sha256_core" { } { { "../../../../sha256/src/rtl/sha256_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" 39 -1 0 } } } 0 12023 "Found [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha256.v(73) " "Verilog HDL Declaration information at sha256.v(73): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 73 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha256.v(74) " "Verilog HDL Declaration information at sha256.v(74): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 74 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha256.v(75) " "Verilog HDL Declaration information at sha256.v(75): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 75 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in th [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256 " "Found entity 1: sha256" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quar [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1_w_mem " "Found entity 1: sha1_w_mem" { } { { "../../../../sha1/src/rtl/sha1_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1_core " "Found entity 1: sha1_core" { } { { "../../../../sha1/src/rtl/sha1_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha1.v(73) " "Verilog HDL Declaration information at sha1.v(73): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 73 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Q [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha1.v(74) " "Verilog HDL Declaration information at sha1.v(74): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 74 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Q [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha1.v(75) " "Verilog HDL Declaration information at sha1.v(75): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 75 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1 " "Found entity 1: sha1" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424902 [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 rng_selector " "Found entity 1: rng_selector" { } { { "../../../../core_selector/src/rtl/rng_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 hash_selector " "Found entity 1: hash_selector" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_se [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 core_selector " "Found entity 1: core_selector" { } { { "../../../../core_selector/src/rtl/core_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_se [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 cipher_selector " "Found entity 1: cipher_selector" { } { { "../../../../core_selector/src/rtl/cipher_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/r [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_ack RX_ACK coretest.v(48) " "Verilog HDL Declaration information at coretest.v(48): object \"rx_ack\" differs only in case from object \"RX_ACK\" in the same scope" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "tx_syn TX_SYN coretest.v(50) " "Verilog HDL Declaration information at coretest.v(50): object \"tx_syn\" differs only in case from object \"TX_SYN\" in the same scope" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 50 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" { { "Info" "ISGN_ENTITY_NAME" "1 coretest " "Found entity 1: coretest" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 41 -1 0 } } } 0 12023 "Found entity %1! [...]
+{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\":\"; expecting \";\" uart_core.v(72) " "Verilog HDL syntax error at uart_core.v(72) near text \":\"; expecting \";\"" { } { { "../../../src/rtl/uart_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" 72 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "Quartus II" 0 -1 1424902193186 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "uart_core uart_core.v(48) " "Ignored design unit \"uart_core\" at uart_core.v(48) due to previous errors" { } { { "../../../src/rtl/uart_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" 48 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1424902193187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v 0 0 " "Found 0 design units, including 0 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424902193187 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "uart_regs.v(102) " "Verilog HDL information at uart_regs.v(102): always construct contains both blocking and non-blocking assignments" { } { { "../../../src/rtl/uart_regs.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" 102 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1424902193188 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" { { "Info" "ISGN_ENTITY_NAME" "1 comm_regs " "Found entity 1: comm_regs" { } { { "../../../src/rtl/uart_regs.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Qu [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "terasic_top.v 1 1 " "Found 1 design units, including 1 entities, in source file terasic_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 terasic_top " "Found entity 1: terasic_top" { } { { "terasic_top.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424902193189 ""} } { } 0 12021 "Found %2!llu! design units, including [...]
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "915 " "Peak virtual memory: 915 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424902193242 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 25 17:09:53 2015 " "Processing ended: Wed Feb 25 17:09:53 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Qua [...]
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1 " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1424902193858 ""}
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.cdb
new file mode 100644
index 0000000..64a6944
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.hdb
new file mode 100644
index 0000000..b46f1e8
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(0).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.cdb
new file mode 100644
index 0000000..a0f2c95
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.hdb
new file mode 100644
index 0000000..758afde
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(1).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.cdb
new file mode 100644
index 0000000..4a1af47
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.hdb
new file mode 100644
index 0000000..083ad3c
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(10).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.cdb
new file mode 100644
index 0000000..9bbd8c9
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.hdb
new file mode 100644
index 0000000..ecc4242
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(11).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.cdb
new file mode 100644
index 0000000..d7240ed
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.hdb
new file mode 100644
index 0000000..f4dfec2
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(12).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.cdb
new file mode 100644
index 0000000..62248ed
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.hdb
new file mode 100644
index 0000000..6a067b6
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(13).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.cdb
new file mode 100644
index 0000000..1e99c07
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.hdb
new file mode 100644
index 0000000..0407819
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(14).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.cdb
new file mode 100644
index 0000000..30c2f04
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.hdb
new file mode 100644
index 0000000..868f2b5
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(15).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.cdb
new file mode 100644
index 0000000..3edcbb9
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.hdb
new file mode 100644
index 0000000..e1580c1
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(16).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.cdb
new file mode 100644
index 0000000..eaf5c85
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.hdb
new file mode 100644
index 0000000..d4a48b7
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(17).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.cdb
new file mode 100644
index 0000000..613a9fc
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.hdb
new file mode 100644
index 0000000..98c171c
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(2).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.cdb
new file mode 100644
index 0000000..b126325
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.hdb
new file mode 100644
index 0000000..0ad3ae3
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(3).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.cdb
new file mode 100644
index 0000000..9aaee76
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.hdb
new file mode 100644
index 0000000..2f769e5
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(4).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.cdb
new file mode 100644
index 0000000..396e927
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.hdb
new file mode 100644
index 0000000..54f3a4e
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(5).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.cdb
new file mode 100644
index 0000000..62626a2
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.hdb
new file mode 100644
index 0000000..c9c0138
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(6).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.cdb
new file mode 100644
index 0000000..315a96d
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.hdb
new file mode 100644
index 0000000..7b93edb
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(7).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.cdb
new file mode 100644
index 0000000..78f23a7
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.hdb
new file mode 100644
index 0000000..ce8918b
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(8).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.cdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.cdb
new file mode 100644
index 0000000..d5e4f58
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.cdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.hdb
new file mode 100644
index 0000000..362ca09
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.(9).cnf.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cbx.xml b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cbx.xml
new file mode 100644
index 0000000..110dd66
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+ <PROJECT NAME="terasic_top">
+ </PROJECT>
+</LOG_ROOT>
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cmp.rdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cmp.rdb
new file mode 100644
index 0000000..729bead
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.cmp.rdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.db_info b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.db_info
new file mode 100644
index 0000000..f608644
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+Version_Index = 352369152
+Creation_Time = Wed Feb 25 17:12:51 2015
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.hif b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.hif
new file mode 100644
index 0000000..4828699
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.hif differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.logic_util_heuristic.dat b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.logic_util_heuristic.dat
new file mode 100644
index 0000000..e69de29
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.qmsg b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.qmsg
new file mode 100644
index 0000000..5cf7875
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.qmsg
@@ -0,0 +1,63 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424902387407 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.1.0 Build 186 12/03/2014 SJ Web Edition " "Version 14.1.0 Build 186 12/03/2014 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424902387408 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 25 17:13:07 2015 " "Processing started: Wed Feb 25 17:13:07 2015" { } { } 0 0 "Processing started: %1!s!" 0 [...]
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1424902387409 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1424902387728 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_w_mem " "Found entity 1: sha512_w_mem" { } { { "../../../../sha512/src/rtl/sha512_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v" 40 -1 0 } } } 0 12023 " [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_k_constants " "Found entity 1: sha512_k_constants" { } { { "../../../../sha512/src/rtl/sha512_k_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_h_constants " "Found entity 1: sha512_h_constants" { } { { "../../../../sha512/src/rtl/sha512_h_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512_core " "Found entity 1: sha512_core" { } { { "../../../../sha512/src/rtl/sha512_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" 40 -1 0 } } } 0 12023 "Found [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha512.v(78) " "Verilog HDL Declaration information at sha512.v(78): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 78 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha512.v(79) " "Verilog HDL Declaration information at sha512.v(79): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 79 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha512.v(80) " "Verilog HDL Declaration information at sha512.v(80): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 80 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in th [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha512 " "Found entity 1: sha512" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quar [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_w_mem " "Found entity 1: sha256_w_mem" { } { { "../../../../sha256/src/rtl/sha256_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v" 39 -1 0 } } } 0 12023 " [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_k_constants " "Found entity 1: sha256_k_constants" { } { { "../../../../sha256/src/rtl/sha256_k_constants.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_c [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256_core " "Found entity 1: sha256_core" { } { { "../../../../sha256/src/rtl/sha256_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" 39 -1 0 } } } 0 12023 "Found [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha256.v(73) " "Verilog HDL Declaration information at sha256.v(73): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 73 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha256.v(74) " "Verilog HDL Declaration information at sha256.v(74): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 74 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same s [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha256.v(75) " "Verilog HDL Declaration information at sha256.v(75): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 75 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in th [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha256 " "Found entity 1: sha256" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quar [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1_w_mem " "Found entity 1: sha1_w_mem" { } { { "../../../../sha1/src/rtl/sha1_w_mem.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1_core " "Found entity 1: sha1_core" { } { { "../../../../sha1/src/rtl/sha1_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME0 core_name0 sha1.v(73) " "Verilog HDL Declaration information at sha1.v(73): object \"CORE_NAME0\" differs only in case from object \"core_name0\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 73 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Q [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_NAME1 core_name1 sha1.v(74) " "Verilog HDL Declaration information at sha1.v(74): object \"CORE_NAME1\" differs only in case from object \"core_name1\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 74 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Q [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CORE_VERSION core_version sha1.v(75) " "Verilog HDL Declaration information at sha1.v(75): object \"CORE_VERSION\" differs only in case from object \"core_version\" in the same scope" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 75 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" { { "Info" "ISGN_ENTITY_NAME" "1 sha1 " "Found entity 1: sha1" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424902 [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 rng_selector " "Found entity 1: rng_selector" { } { { "../../../../core_selector/src/rtl/rng_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 hash_selector " "Found entity 1: hash_selector" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_se [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 core_selector " "Found entity 1: core_selector" { } { { "../../../../core_selector/src/rtl/core_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_se [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 cipher_selector " "Found entity 1: cipher_selector" { } { { "../../../../core_selector/src/rtl/cipher_selector.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/r [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_ack RX_ACK coretest.v(48) " "Verilog HDL Declaration information at coretest.v(48): object \"rx_ack\" differs only in case from object \"RX_ACK\" in the same scope" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "tx_syn TX_SYN coretest.v(50) " "Verilog HDL Declaration information at coretest.v(50): object \"tx_syn\" differs only in case from object \"TX_SYN\" in the same scope" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 50 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" { { "Info" "ISGN_ENTITY_NAME" "1 coretest " "Found entity 1: coretest" { } { { "../../../../coretest/src/rtl/coretest.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v" 41 -1 0 } } } 0 12023 "Found entity %1! [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_core " "Found entity 1: uart_core" { } { { "../../../src/rtl/uart_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Qu [...]
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "uart_regs.v(102) " "Verilog HDL information at uart_regs.v(102): always construct contains both blocking and non-blocking assignments" { } { { "../../../src/rtl/uart_regs.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" 102 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1424902399496 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" { { "Info" "ISGN_ENTITY_NAME" "1 comm_regs " "Found entity 1: comm_regs" { } { { "../../../src/rtl/uart_regs.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Qu [...]
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "terasic_top.v 1 1 " "Found 1 design units, including 1 entities, in source file terasic_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 terasic_top " "Found entity 1: terasic_top" { } { { "terasic_top.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424902399497 ""} } { } 0 12021 "Found %2!llu! design units, including [...]
+{ "Info" "ISGN_START_ELABORATION_TOP" "terasic_top " "Elaborating entity \"terasic_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1424902399577 ""}
+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "debug terasic_top.v(51) " "Output port \"debug\" at terasic_top.v(51) has no driver" { } { { "terasic_top.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 51 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1424902399579 "|terasic_top"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "core_selector core_selector:cores " "Elaborating entity \"core_selector\" for hierarchy \"core_selector:cores\"" { } { { "terasic_top.v" "cores" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399580 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hash_selector core_selector:cores\|hash_selector:hashes " "Elaborating entity \"hash_selector\" for hierarchy \"core_selector:cores\|hash_selector:hashes\"" { } { { "../../../../core_selector/src/rtl/core_selector.v" "hashes" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" 124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399582 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "comm_regs core_selector:cores\|hash_selector:hashes\|comm_regs:comm_regs " "Elaborating entity \"comm_regs\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|comm_regs:comm_regs\"" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "comm_regs" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" 163 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha1 core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst " "Elaborating entity \"sha1\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst\"" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "sha1_inst" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399587 ""}
+{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "sha1.v(184) " "Verilog HDL Case Statement warning at sha1.v(184): incomplete case statement has no default case item" { } { { "../../../../sha1/src/rtl/sha1.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 184 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Quartus II" 0 -1 1424902399603 "|terasic_top|core_selector:cores|hash_selector: [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha1_core core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst\|sha1_core:core " "Elaborating entity \"sha1_core\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst\|sha1_core:core\"" { } { { "../../../../sha1/src/rtl/sha1.v" "core" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v" 136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399604 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha1_w_mem core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst\|sha1_core:core\|sha1_w_mem:w_mem_inst " "Elaborating entity \"sha1_w_mem\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha1:sha1_inst\|sha1_core:core\|sha1_w_mem:w_mem_inst\"" { } { { "../../../../sha1/src/rtl/sha1_core.v" "w_mem_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v" 141 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha256 core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst " "Elaborating entity \"sha256\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\"" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "sha256_inst" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" 204 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 142 [...]
+{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "sha256.v(184) " "Verilog HDL Case Statement warning at sha256.v(184): incomplete case statement has no default case item" { } { { "../../../../sha256/src/rtl/sha256.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 184 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Quartus II" 0 -1 1424902399635 "|terasic_top|core_selector:cores|ha [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha256_core core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core " "Elaborating entity \"sha256_core\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core\"" { } { { "../../../../sha256/src/rtl/sha256.v" "core" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v" 136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus I [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha256_k_constants core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core\|sha256_k_constants:k_constants_inst " "Elaborating entity \"sha256_k_constants\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core\|sha256_k_constants:k_constants_inst\"" { } { { "../../../../sha256/src/rtl/sha256_core.v" "k_constants_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/r [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha256_w_mem core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core\|sha256_w_mem:w_mem_inst " "Elaborating entity \"sha256_w_mem\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha256:sha256_inst\|sha256_core:core\|sha256_w_mem:w_mem_inst\"" { } { { "../../../../sha256/src/rtl/sha256_core.v" "w_mem_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v" 169 0 0 } } } 0 12128 " [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha512 core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst " "Elaborating entity \"sha512\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\"" { } { { "../../../../core_selector/src/rtl/hash_selector.v" "sha512_inst" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v" 225 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 142 [...]
+{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "sha512.v(219) " "Verilog HDL Case Statement warning at sha512.v(219): incomplete case statement has no default case item" { } { { "../../../../sha512/src/rtl/sha512.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 219 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Quartus II" 0 -1 1424902399686 "|terasic_top|core_selector:cores|ha [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha512_core core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core " "Elaborating entity \"sha512_core\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\"" { } { { "../../../../sha512/src/rtl/sha512.v" "core" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v" 162 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus I [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha512_k_constants core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_k_constants:k_constants_inst " "Elaborating entity \"sha512_k_constants\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_k_constants:k_constants_inst\"" { } { { "../../../../sha512/src/rtl/sha512_core.v" "k_constants_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/r [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha512_h_constants core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_h_constants:h_constants_inst " "Elaborating entity \"sha512_h_constants\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_h_constants:h_constants_inst\"" { } { { "../../../../sha512/src/rtl/sha512_core.v" "h_constants_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/r [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sha512_w_mem core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_w_mem:w_mem_inst " "Elaborating entity \"sha512_w_mem\" for hierarchy \"core_selector:cores\|hash_selector:hashes\|sha512:sha512_inst\|sha512_core:core\|sha512_w_mem:w_mem_inst\"" { } { { "../../../../sha512/src/rtl/sha512_core.v" "w_mem_inst" { Text "/home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v" 194 0 0 } } } 0 12128 " [...]
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rng_selector core_selector:cores\|rng_selector:rngs " "Elaborating entity \"rng_selector\" for hierarchy \"core_selector:cores\|rng_selector:rngs\"" { } { { "../../../../core_selector/src/rtl/core_selector.v" "rngs" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399724 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cipher_selector core_selector:cores\|cipher_selector:ciphers " "Elaborating entity \"cipher_selector\" for hierarchy \"core_selector:cores\|cipher_selector:ciphers\"" { } { { "../../../../core_selector/src/rtl/core_selector.v" "ciphers" { Text "/home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399726 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_core uart_core:uart_core " "Elaborating entity \"uart_core\" for hierarchy \"uart_core:uart_core\"" { } { { "terasic_top.v" "uart_core" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424902399729 ""}
+{ "Error" "EVRFX_VERI_UNRESOLVED_HIERARCHICAL_REFERENCE" "bit_rate uart_core.v(71) " "Verilog HDL error at uart_core.v(71): can't resolve reference to object \"bit_rate\"" { } { { "../../../src/rtl/uart_core.v" "" { Text "/home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v" 71 0 0 } } } 0 10207 "Verilog HDL error at %2!s!: can't resolve reference to object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424902399731 ""}
+{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "uart_core:uart_core " "Can't elaborate user hierarchy \"uart_core:uart_core\"" { } { { "terasic_top.v" "uart_core" { Text "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v" 117 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424902399732 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg " "Generated suppressed messages file /home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1424902399760 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "955 " "Peak virtual memory: 955 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424902399802 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 25 17:13:19 2015 " "Processing ended: Wed Feb 25 17:13:19 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Q [...]
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.rdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.rdb
new file mode 100644
index 0000000..2b0605f
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map.rdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map_bb.hdb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map_bb.hdb
new file mode 100644
index 0000000..20ae694
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.map_bb.hdb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.pti_db_list.ddb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.pti_db_list.ddb
new file mode 100644
index 0000000..d5ce57a
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.pti_db_list.ddb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.rom0_sha256_k_constants_e63d9e28.hdl.mif b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.rom0_sha256_k_constants_e63d9e28.hdl.mif
new file mode 100644
index 0000000..ec19e45
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.rom0_sha256_k_constants_e63d9e28.hdl.mif
@@ -0,0 +1,75 @@
+-- begin_signature
+-- sha256_k_constants
+-- end_signature
+WIDTH=32;
+DEPTH=64;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=BIN;
+
+CONTENT BEGIN
+ 63 : 11000110011100010111100011110010;
+ 62 : 10111110111110011010001111110111;
+ 61 : 10100100010100000110110011101011;
+ 60 : 10010000101111101111111111111010;
+ 59 : 10001100110001110000001000001000;
+ 58 : 10000100110010000111100000010100;
+ 57 : 01111000101001010110001101101111;
+ 56 : 01110100100011111000001011101110;
+ 55 : 01101000001011100110111111110011;
+ 54 : 01011011100111001100101001001111;
+ 53 : 01001110110110001010101001001010;
+ 52 : 00111001000111000000110010110011;
+ 51 : 00110100101100001011110010110101;
+ 50 : 00100111010010000111011101001100;
+ 49 : 00011110001101110110110000001000;
+ 48 : 00011001101001001100000100010110;
+ 47 : 00010000011010101010000001110000;
+ 46 : 11110100000011100011010110000101;
+ 45 : 11010110100110010000011000100100;
+ 44 : 11010001100100101110100000011001;
+ 43 : 11000111011011000101000110100011;
+ 42 : 11000010010010111000101101110000;
+ 41 : 10101000000110100110011001001011;
+ 40 : 10100010101111111110100010100001;
+ 39 : 10010010011100100010110010000101;
+ 38 : 10000001110000101100100100101110;
+ 37 : 01110110011010100000101010111011;
+ 36 : 01100101000010100111001101010100;
+ 35 : 01010011001110000000110100010011;
+ 34 : 01001101001011000110110111111100;
+ 33 : 00101110000110110010000100111000;
+ 32 : 00100111101101110000101010000101;
+ 31 : 00010100001010010010100101100111;
+ 30 : 00000110110010100110001101010001;
+ 29 : 11010101101001111001000101000111;
+ 28 : 11000110111000000000101111110011;
+ 27 : 10111111010110010111111111000111;
+ 26 : 10110000000000110010011111001000;
+ 25 : 10101000001100011100011001101101;
+ 24 : 10011000001111100101000101010010;
+ 23 : 01110110111110011000100011011010;
+ 22 : 01011100101100001010100111011100;
+ 21 : 01001010011101001000010010101010;
+ 20 : 00101101111010010010110001101111;
+ 19 : 00100100000011001010000111001100;
+ 18 : 00001111110000011001110111000110;
+ 17 : 11101111101111100100011110000110;
+ 16 : 11100100100110110110100111000001;
+ 15 : 11000001100110111111000101110100;
+ 14 : 10011011110111000000011010100111;
+ 13 : 10000000110111101011000111111110;
+ 12 : 01110010101111100101110101110100;
+ 11 : 01010101000011000111110111000011;
+ 10 : 00100100001100011000010110111110;
+ 9 : 00010010100000110101101100000001;
+ 8 : 11011000000001111010101010011000;
+ 7 : 10101011000111000101111011010101;
+ 6 : 10010010001111111000001010100100;
+ 5 : 01011001111100010001000111110001;
+ 4 : 00111001010101101100001001011011;
+ 3 : 11101001101101011101101110100101;
+ 2 : 10110101110000001111101111001111;
+ 1 : 01110001001101110100010010010001;
+ 0 : 01000010100010100010111110011000;
+END;
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.sld_design_entry.sci b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.sld_design_entry.sci
new file mode 100644
index 0000000..83b709b
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.sld_design_entry.sci differ
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.smart_action.txt b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.smart_action.txt
new file mode 100644
index 0000000..11b531f
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.smart_action.txt
@@ -0,0 +1 @@
+SOURCE
diff --git a/uart/toolruns/quartus/terasic_c5g/db/terasic_top.tis_db_list.ddb b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.tis_db_list.ddb
new file mode 100644
index 0000000..e8ea40e
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/db/terasic_top.tis_db_list.ddb differ
diff --git a/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.flow.rpt b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.flow.rpt
new file mode 100644
index 0000000..effcb67
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.flow.rpt
@@ -0,0 +1,114 @@
+Flow report for terasic_top
+Wed Feb 25 17:13:19 2015
+Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; Flow Summary ;
++-----------------------------+--------------------------------------------+
+; Flow Status ; Flow Failed - Wed Feb 25 17:13:19 2015 ;
+; Quartus II 64-Bit Version ; 14.1.0 Build 186 12/03/2014 SJ Web Edition ;
+; Revision Name ; terasic_top ;
+; Top-level Entity Name ; terasic_top ;
+; Family ; Cyclone V ;
+; Device ; 5CGXFC5C6F27C7 ;
+; Timing Models ; Final ;
+; Logic utilization (in ALMs) ; N/A until Partition Merge ;
+; Total registers ; N/A until Partition Merge ;
+; Total pins ; N/A until Partition Merge ;
+; Total virtual pins ; N/A until Partition Merge ;
+; Total block memory bits ; N/A until Partition Merge ;
+; Total PLLs ; N/A until Partition Merge ;
+; Total DLLs ; N/A until Partition Merge ;
++-----------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 02/25/2015 17:13:07 ;
+; Main task ; Compilation ;
+; Revision Name ; terasic_top ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 233360587640711.142490238708185 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 955 MB ; 00:00:30 ;
+; Total ; 00:00:12 ; -- ; -- ; 00:00:30 ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++--------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++----------------------+------------------+--------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++----------------------+------------------+--------------+------------+----------------+
+; Analysis & Synthesis ; tin-man ; Ubuntu 14.10 ; 14 ; x86_64 ;
++----------------------+------------------+--------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top
+
+
+
diff --git a/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.rpt b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.rpt
new file mode 100644
index 0000000..3f8cadc
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.rpt
@@ -0,0 +1,242 @@
+Analysis & Synthesis report for terasic_top
+Wed Feb 25 17:13:19 2015
+Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Messages
+ 6. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-----------------------------+--------------------------------------------+
+; Analysis & Synthesis Status ; Failed - Wed Feb 25 17:13:19 2015 ;
+; Quartus II 64-Bit Version ; 14.1.0 Build 186 12/03/2014 SJ Web Edition ;
+; Revision Name ; terasic_top ;
+; Top-level Entity Name ; terasic_top ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A until Partition Merge ;
+; Total registers ; N/A until Partition Merge ;
+; Total pins ; N/A until Partition Merge ;
+; Total virtual pins ; N/A until Partition Merge ;
+; Total block memory bits ; N/A until Partition Merge ;
+; Total PLLs ; N/A until Partition Merge ;
+; Total DLLs ; N/A until Partition Merge ;
++-----------------------------+--------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CGXFC5C6F27C7 ; ;
+; Top-level entity name ; terasic_top ; terasic_top ;
+; Family name ; Cyclone V ; Cyclone IV GX ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation ;
++----------------------------+--------+
+; Processors ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 1 ;
++----------------------------+--------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+ Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+ Info: Processing started: Wed Feb 25 17:13:07 2015
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off coretest_hashes -c terasic_top
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_w_mem.v
+ Info (12023): Found entity 1: sha512_w_mem
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_k_constants.v
+ Info (12023): Found entity 1: sha512_k_constants
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_h_constants.v
+ Info (12023): Found entity 1: sha512_h_constants
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512_core.v
+ Info (12023): Found entity 1: sha512_core
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha512/src/rtl/sha512.v
+ Info (12023): Found entity 1: sha512
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_w_mem.v
+ Info (12023): Found entity 1: sha256_w_mem
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_k_constants.v
+ Info (12023): Found entity 1: sha256_k_constants
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256_core.v
+ Info (12023): Found entity 1: sha256_core
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha256/src/rtl/sha256.v
+ Info (12023): Found entity 1: sha256
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_w_mem.v
+ Info (12023): Found entity 1: sha1_w_mem
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1_core.v
+ Info (12023): Found entity 1: sha1_core
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/sha1/src/rtl/sha1.v
+ Info (12023): Found entity 1: sha1
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/rng_selector.v
+ Info (12023): Found entity 1: rng_selector
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/hash_selector.v
+ Info (12023): Found entity 1: hash_selector
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/core_selector.v
+ Info (12023): Found entity 1: core_selector
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/core_selector/src/rtl/cipher_selector.v
+ Info (12023): Found entity 1: cipher_selector
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/coretest/src/rtl/coretest.v
+ Info (12023): Found entity 1: coretest
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v
+ Info (12023): Found entity 1: uart_core
+Info (12021): Found 1 design units, including 1 entities, in source file /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_regs.v
+ Info (12023): Found entity 1: comm_regs
+Info (12021): Found 1 design units, including 1 entities, in source file terasic_top.v
+ Info (12023): Found entity 1: terasic_top
+Info (12127): Elaborating entity "terasic_top" for the top level hierarchy
+Warning (10034): Output port "debug" at terasic_top.v(51) has no driver
+Info (12128): Elaborating entity "core_selector" for hierarchy "core_selector:cores"
+Info (12128): Elaborating entity "hash_selector" for hierarchy "core_selector:cores|hash_selector:hashes"
+Info (12128): Elaborating entity "comm_regs" for hierarchy "core_selector:cores|hash_selector:hashes|comm_regs:comm_regs"
+Info (12128): Elaborating entity "sha1" for hierarchy "core_selector:cores|hash_selector:hashes|sha1:sha1_inst"
+Warning (10270): Verilog HDL Case Statement warning at sha1.v(184): incomplete case statement has no default case item
+Info (12128): Elaborating entity "sha1_core" for hierarchy "core_selector:cores|hash_selector:hashes|sha1:sha1_inst|sha1_core:core"
+Info (12128): Elaborating entity "sha1_w_mem" for hierarchy "core_selector:cores|hash_selector:hashes|sha1:sha1_inst|sha1_core:core|sha1_w_mem:w_mem_inst"
+Info (12128): Elaborating entity "sha256" for hierarchy "core_selector:cores|hash_selector:hashes|sha256:sha256_inst"
+Warning (10270): Verilog HDL Case Statement warning at sha256.v(184): incomplete case statement has no default case item
+Info (12128): Elaborating entity "sha256_core" for hierarchy "core_selector:cores|hash_selector:hashes|sha256:sha256_inst|sha256_core:core"
+Info (12128): Elaborating entity "sha256_k_constants" for hierarchy "core_selector:cores|hash_selector:hashes|sha256:sha256_inst|sha256_core:core|sha256_k_constants:k_constants_inst"
+Info (12128): Elaborating entity "sha256_w_mem" for hierarchy "core_selector:cores|hash_selector:hashes|sha256:sha256_inst|sha256_core:core|sha256_w_mem:w_mem_inst"
+Info (12128): Elaborating entity "sha512" for hierarchy "core_selector:cores|hash_selector:hashes|sha512:sha512_inst"
+Warning (10270): Verilog HDL Case Statement warning at sha512.v(219): incomplete case statement has no default case item
+Info (12128): Elaborating entity "sha512_core" for hierarchy "core_selector:cores|hash_selector:hashes|sha512:sha512_inst|sha512_core:core"
+Info (12128): Elaborating entity "sha512_k_constants" for hierarchy "core_selector:cores|hash_selector:hashes|sha512:sha512_inst|sha512_core:core|sha512_k_constants:k_constants_inst"
+Info (12128): Elaborating entity "sha512_h_constants" for hierarchy "core_selector:cores|hash_selector:hashes|sha512:sha512_inst|sha512_core:core|sha512_h_constants:h_constants_inst"
+Info (12128): Elaborating entity "sha512_w_mem" for hierarchy "core_selector:cores|hash_selector:hashes|sha512:sha512_inst|sha512_core:core|sha512_w_mem:w_mem_inst"
+Info (12128): Elaborating entity "rng_selector" for hierarchy "core_selector:cores|rng_selector:rngs"
+Info (12128): Elaborating entity "cipher_selector" for hierarchy "core_selector:cores|cipher_selector:ciphers"
+Info (12128): Elaborating entity "uart_core" for hierarchy "uart_core:uart_core"
+Error (10207): Verilog HDL error at uart_core.v(71): can't resolve reference to object "bit_rate" File: /home/pselkirk/cryptech/user/paul/core/uart/src/rtl/uart_core.v Line: 71
+Error (12152): Can't elaborate user hierarchy "uart_core:uart_core" File: /home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/terasic_top.v Line: 117
+Info (144001): Generated suppressed messages file /home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg
+Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings
+ Error: Peak virtual memory: 955 megabytes
+ Error: Processing ended: Wed Feb 25 17:13:19 2015
+ Error: Elapsed time: 00:00:12
+ Error: Total CPU time (on all processors): 00:00:30
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /home/pselkirk/cryptech/user/paul/core/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg.
+
+
diff --git a/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg
new file mode 100644
index 0000000..d1265b7
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.smsg
@@ -0,0 +1,12 @@
+Info (10281): Verilog HDL Declaration information at sha512.v(78): object "CORE_NAME0" differs only in case from object "core_name0" in the same scope
+Info (10281): Verilog HDL Declaration information at sha512.v(79): object "CORE_NAME1" differs only in case from object "core_name1" in the same scope
+Info (10281): Verilog HDL Declaration information at sha512.v(80): object "CORE_VERSION" differs only in case from object "core_version" in the same scope
+Info (10281): Verilog HDL Declaration information at sha256.v(73): object "CORE_NAME0" differs only in case from object "core_name0" in the same scope
+Info (10281): Verilog HDL Declaration information at sha256.v(74): object "CORE_NAME1" differs only in case from object "core_name1" in the same scope
+Info (10281): Verilog HDL Declaration information at sha256.v(75): object "CORE_VERSION" differs only in case from object "core_version" in the same scope
+Info (10281): Verilog HDL Declaration information at sha1.v(73): object "CORE_NAME0" differs only in case from object "core_name0" in the same scope
+Info (10281): Verilog HDL Declaration information at sha1.v(74): object "CORE_NAME1" differs only in case from object "core_name1" in the same scope
+Info (10281): Verilog HDL Declaration information at sha1.v(75): object "CORE_VERSION" differs only in case from object "core_version" in the same scope
+Info (10281): Verilog HDL Declaration information at coretest.v(48): object "rx_ack" differs only in case from object "RX_ACK" in the same scope
+Info (10281): Verilog HDL Declaration information at coretest.v(50): object "tx_syn" differs only in case from object "TX_SYN" in the same scope
+Warning (10268): Verilog HDL information at uart_regs.v(102): always construct contains both blocking and non-blocking assignments
diff --git a/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.summary b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.summary
new file mode 100644
index 0000000..20ab9e3
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/output_files/terasic_top.map.summary
@@ -0,0 +1,12 @@
+Analysis & Synthesis Status : Failed - Wed Feb 25 17:13:19 2015
+Quartus II 64-Bit Version : 14.1.0 Build 186 12/03/2014 SJ Web Edition
+Revision Name : terasic_top
+Top-level Entity Name : terasic_top
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A until Partition Merge
+Total registers : N/A until Partition Merge
+Total pins : N/A until Partition Merge
+Total virtual pins : N/A until Partition Merge
+Total block memory bits : N/A until Partition Merge
+Total PLLs : N/A until Partition Merge
+Total DLLs : N/A until Partition Merge
diff --git a/uart/toolruns/quartus/terasic_c5g/terasic_top.qsf b/uart/toolruns/quartus/terasic_c5g/terasic_top.qsf
new file mode 100644
index 0000000..c2cdb90
--- /dev/null
+++ b/uart/toolruns/quartus/terasic_c5g/terasic_top.qsf
@@ -0,0 +1,100 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
+# Date created = 16:43:44 February 25, 2015
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# terasic_top_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC5C6F27C7
+set_global_assignment -name TOP_LEVEL_ENTITY terasic_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:43:44 FEBRUARY 25, 2015"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_location_assignment PIN_R20 -to clk
+set_location_assignment PIN_P11 -to reset_n
+set_location_assignment PIN_M9 -to rxd
+set_location_assignment PIN_L9 -to txd
+set_location_assignment PIN_L7 -to debug[0]
+set_location_assignment PIN_K6 -to debug[1]
+set_location_assignment PIN_D8 -to debug[2]
+set_location_assignment PIN_E9 -to debug[3]
+set_location_assignment PIN_A5 -to debug[4]
+set_location_assignment PIN_B6 -to debug[5]
+set_location_assignment PIN_H8 -to debug[6]
+set_location_assignment PIN_H9 -to debug[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to txd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_k_constants.v
+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_h_constants.v
+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_core.v
+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512.v
+set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_k_constants.v
+set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256_core.v
+set_global_assignment -name VERILOG_FILE ../../../../sha256/src/rtl/sha256.v
+set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_w_mem.v
+set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1_core.v
+set_global_assignment -name VERILOG_FILE ../../../../sha1/src/rtl/sha1.v
+set_global_assignment -name VERILOG_FILE ../../../../core_selector/src/rtl/rng_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../core_selector/src/rtl/hash_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../core_selector/src/rtl/core_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../core_selector/src/rtl/cipher_selector.v
+set_global_assignment -name VERILOG_FILE ../../../../coretest/src/rtl/coretest.v
+set_global_assignment -name VERILOG_FILE ../../../src/rtl/uart_core.v
+set_global_assignment -name VERILOG_FILE ../../../src/rtl/uart_regs.v
+set_global_assignment -name VERILOG_FILE terasic_top.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/uart/toolruns/quartus/terasic_c5g/terasic_top.qws b/uart/toolruns/quartus/terasic_c5g/terasic_top.qws
new file mode 100644
index 0000000..388e989
Binary files /dev/null and b/uart/toolruns/quartus/terasic_c5g/terasic_top.qws differ
diff --git a/novena/src/rtl/novena_i2c.v b/uart/toolruns/quartus/terasic_c5g/terasic_top.v
similarity index 52%
rename from novena/src/rtl/novena_i2c.v
rename to uart/toolruns/quartus/terasic_c5g/terasic_top.v
index 23ce3d2..d1db725 100644
--- a/novena/src/rtl/novena_i2c.v
+++ b/uart/toolruns/quartus/terasic_c5g/terasic_top.v
@@ -38,63 +38,48 @@
//
//======================================================================
-module novena_baseline_top
+module terasic_top
(
- // Differential input for 50 MHz general clock.
- input wire gclk_p_pin,
- input wire gclk_n_pin,
-
- // Reset controlled by the CPU.
- // this must be configured as input w/pullup
- input wire reset_mcu_b_pin,
-
- // Cryptech avalanche noise board input and LED outputs
- input wire ct_noise,
- output wire [7 : 0] ct_led,
-
- // I2C interface
- input wire i2c_scl,
- inout wire i2c_sda,
-
- // Novena utility ports
- output wire apoptosis_pin, // Hold low to not restart after config.
- output wire led_pin // LED on edge close to the FPGA.
+ input wire clk,
+ input wire reset_n,
+
+ // External interface.
+ input wire rxd,
+ output wire txd,
+
+ output wire [7 : 0] debug
);
-
//----------------------------------------------------------------
- // Clock Manager
+ // Core Selector
//
- // Clock manager is used to buffer BCLK, generate SYS_CLK
- // from GCLK and implement the reset logic.
+ // This multiplexer is used to map different types of cores, such as
+ // hashes, RNGs and ciphers to different regions (segments) of memory.
//----------------------------------------------------------------
- wire sys_clk;
- wire sys_rst = 0;
+ core_selector cores
+ (
+ .sys_clk(clk),
+ .sys_rst(!reset_n),
- IBUFGDS clkibufgds(
- .I(gclk_p_pin),
- .IB(gclk_n_pin),
- .O(sys_clk)
- );
+ .sys_eim_addr(sys_eim_addr),
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+
+ .sys_write_data(coretest_write_data),
+ .sys_read_data(coretest_read_data)
+ );
//----------------------------------------------------------------
- // I2C Interface
+ // UART Interface
//
- // I2C subsystem handles all data transfer to/from CPU via I2C bus.
+ // UART subsystem handles all data transfer to/from host via UART.
//----------------------------------------------------------------
- parameter I2C_DEVICE_ADDR = 7'h0f;
wire [16: 0] sys_eim_addr;
wire sys_eim_wr;
wire sys_eim_rd;
- wire sda_pd;
- wire sda_int;
-
- wire clk = sys_clk;
- wire reset_n = ~sys_rst;
-
// Coretest connections.
wire coretest_reset_n;
wire coretest_cs;
@@ -103,43 +88,32 @@ module novena_baseline_top
wire [31 : 0] coretest_write_data;
wire [31 : 0] coretest_read_data;
- // I2C connections
- wire [6:0] i2c_device_addr;
- wire i2c_rxd_syn;
- wire [7 : 0] i2c_rxd_data;
- wire i2c_rxd_ack;
- wire i2c_txd_syn;
- wire [7 : 0] i2c_txd_data;
- wire i2c_txd_ack;
-
- IOBUF #(.DRIVE(8), .SLEW("SLOW"))
- IOBUF_sda (
- .IO(i2c_sda),
- .I(1'b0),
- .T(!sda_pd),
- .O(sda_int)
- );
-
- i2c_core i2c_core
+ // UART connections
+ wire uart_rxd_syn;
+ wire [7 : 0] uart_rxd_data;
+ wire uart_rxd_ack;
+ wire uart_txd_syn;
+ wire [7 : 0] uart_txd_data;
+ wire uart_txd_ack;
+
+ uart_core uart_core
(
.clk(clk),
- .reset(sys_rst),
+ .reset_n(reset_n),
// External data interface
- .SCL(i2c_scl),
- .SDA(sda_int),
- .SDA_pd(sda_pd),
- .i2c_device_addr(i2c_device_addr),
+ .rxd(rxd),
+ .txd(txd),
// Internal receive interface.
- .rxd_syn(i2c_rxd_syn),
- .rxd_data(i2c_rxd_data),
- .rxd_ack(i2c_rxd_ack),
+ .rxd_syn(uart_rxd_syn),
+ .rxd_data(uart_rxd_data),
+ .rxd_ack(uart_rxd_ack),
// Internal transmit interface.
- .txd_syn(i2c_txd_syn),
- .txd_data(i2c_txd_data),
- .txd_ack(i2c_txd_ack)
+ .txd_syn(uart_txd_syn),
+ .txd_data(uart_txd_data),
+ .txd_ack(uart_txd_ack)
);
coretest coretest
@@ -147,13 +121,13 @@ module novena_baseline_top
.clk(clk),
.reset_n(reset_n),
- .rx_syn(i2c_rxd_syn),
- .rx_data(i2c_rxd_data),
- .rx_ack(i2c_rxd_ack),
+ .rx_syn(uart_rxd_syn),
+ .rx_data(uart_rxd_data),
+ .rx_ack(uart_rxd_ack),
- .tx_syn(i2c_txd_syn),
- .tx_data(i2c_txd_data),
- .tx_ack(i2c_txd_ack),
+ .tx_syn(uart_txd_syn),
+ .tx_data(uart_txd_data),
+ .tx_ack(uart_txd_ack),
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
@@ -164,55 +138,9 @@ module novena_baseline_top
.core_read_data(coretest_read_data)
);
- wire select = (i2c_device_addr == I2C_DEVICE_ADDR);
assign sys_eim_addr = { coretest_address[15:13], 1'b0, coretest_address[12:0] };
- assign sys_eim_wr = select & coretest_cs & coretest_we;
- assign sys_eim_rd = select & coretest_cs & ~coretest_we;
+ assign sys_eim_wr = coretest_cs & coretest_we;
+ assign sys_eim_rd = coretest_cs & ~coretest_we;
- //----------------------------------------------------------------
- // Core Selector
- //
- // This multiplexer is used to map different types of cores, such as
- // hashes, RNGs and ciphers to different regions (segments) of memory.
- //----------------------------------------------------------------
- core_selector cores
- (
- .sys_clk(clk),
- .sys_rst(sys_rst),
-
- .sys_eim_addr(sys_eim_addr),
- .sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
-
- .sys_write_data(coretest_write_data),
- .sys_read_data(coretest_read_data)
- );
-
-
- //----------------------------------------------------------------
- // Cryptech Logic
- //
- // Logic specific to the Cryptech use of the Novena.
- // Currently we just hard wire the LED outputs.
- //----------------------------------------------------------------
- assign ct_led = {8{ct_noise}};
-
-
- //----------------------------------------------------------------
- // Novena Patch
- //
- // Patch logic to keep the Novena board happy.
- // The apoptosis_pin pin must be kept low or the whole board
- // (more exactly the CPU) will be reset after the FPGA has
- // been configured.
- //----------------------------------------------------------------
- assign apoptosis_pin = 1'b0;
-
- assign led_pin = 1'b1;
-
endmodule
-
-//======================================================================
-// EOF novena_baseline_top.v
-//======================================================================
More information about the Commits
mailing list