[Cryptech-Commits] [test/novena_base] 02/05: First stage of integration cleanup.
git at cryptech.is
git at cryptech.is
Wed Feb 11 17:51:18 UTC 2015
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch coretest_hashes
in repository test/novena_base.
commit 0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890
Author: Paul Selkirk <paul at psgd.org>
Date: Tue Feb 10 13:51:40 2015 -0500
First stage of integration cleanup.
Add local SHA core wrappers, due to the need for registered outputs.
Remove unused demo-adder code, and reorganize sw directory.
---
rtl/build/Makefile | 22 +-
rtl/iseconfig/novena_baseline.xise | 34 +--
rtl/iseconfig/novena_baseline_top_guide.ncd | 2 +-
rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 15 -
rtl/src/ipcore/clkmgr_dcm.gise | 25 +-
rtl/src/ipcore/clkmgr_dcm.ncf | 120 ++++----
rtl/src/ipcore/clkmgr_dcm.xise | 4 +-
rtl/src/verilog/core_selector.v | 11 +-
rtl/src/verilog/demo_adder.v | 108 --------
rtl/src/verilog/sha1.v | 204 ++++++++++++++
rtl/src/verilog/sha256.v | 204 ++++++++++++++
rtl/src/verilog/sha512.v | 241 +++++++++++++++++
sw/{test-sha256 => }/Makefile | 9 +-
sw/{test-sha256 => }/hash_tester.c | 0
sw/{test-sha256 => }/novena-eim.c | 0
sw/{test-sha256 => }/novena-eim.h | 0
sw/test-adder/Makefile | 11 -
sw/test-adder/novena-eim.c | 406 ----------------------------
sw/test-adder/novena-eim.h | 297 --------------------
sw/test-adder/test-adder.c | 206 --------------
sw/test-sha256/test-sha256.c | 179 ------------
21 files changed, 769 insertions(+), 1329 deletions(-)
diff --git a/rtl/build/Makefile b/rtl/build/Makefile
index ec03197..cfac6ae 100644
--- a/rtl/build/Makefile
+++ b/rtl/build/Makefile
@@ -7,26 +7,30 @@ isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings64.sh
vfiles = \
- ../src/verilog/novena_baseline_top.v \
- ../src/verilog/novena_clkmgr.v \
../src/verilog/cdc_bus_pulse.v \
+ ../src/verilog/cipher_selector.v \
+ ../src/verilog/core_selector.v \
+ ../src/verilog/eim_arbiter_cdc.v \
../src/verilog/eim_arbiter.v \
../src/verilog/eim_da_phy.v \
- ../src/verilog/eim_arbiter_cdc.v \
- ../src/verilog/core_selector.v \
../src/verilog/eim_indicator.v \
+ ../src/verilog/eim_memory.v \
+ ../src/verilog/novena_baseline_top.v \
+ ../src/verilog/novena_clkmgr.v \
+ ../src/verilog/novena_regs.v \
+ ../src/verilog/rng_selector.v \
+ ../src/verilog/sha1.v \
+ ../src/verilog/sha256.v \
+ ../src/verilog/sha512.v \
../src/ipcore/clkmgr_dcm.v \
+ ../../../../core/sha1/src/rtl/sha1_core.v \
+ ../../../../core/sha1/src/rtl/sha1_w_mem.v \
../../../../core/sha256/src/rtl/sha256_core.v \
../../../../core/sha256/src/rtl/sha256_k_constants.v \
- ../../../../core/sha256/src/rtl/sha256.v \
../../../../core/sha256/src/rtl/sha256_w_mem.v \
- ../../../../core/sha1/src/rtl/sha1_core.v \
- ../../../../core/sha1/src/rtl/sha1.v \
- ../../../../core/sha1/src/rtl/sha1_w_mem.v \
../../../../core/sha512/src/rtl/sha512_core.v \
../../../../core/sha512/src/rtl/sha512_h_constants.v \
../../../../core/sha512/src/rtl/sha512_k_constants.v \
- ../../../../core/sha512/src/rtl/sha512.v \
../../../../core/sha512/src/rtl/sha512_w_mem.v
include xilinx.mk
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise
index d07fb76..06ee7dc 100644
--- a/rtl/iseconfig/novena_baseline.xise
+++ b/rtl/iseconfig/novena_baseline.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG">
@@ -35,10 +35,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
- <file xil_pn:name="../src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
<file xil_pn:name="../src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
@@ -64,51 +60,51 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
- <file xil_pn:name="../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../src/verilog/sha1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
- <file xil_pn:name="../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../src/verilog/sha256.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
- <file xil_pn:name="../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
+ <file xil_pn:name="../src/verilog/sha512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
@@ -167,7 +163,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
diff --git a/rtl/iseconfig/novena_baseline_top_guide.ncd b/rtl/iseconfig/novena_baseline_top_guide.ncd
index f61a8cf..d1b9b4b 100644
--- a/rtl/iseconfig/novena_baseline_top_guide.ncd
+++ b/rtl/iseconfig/novena_baseline_top_guide.ncd
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
-###3760:XlxV32DM 3ff8 e98eNqV2k9vHMcRBfCvsgdfaXNqqqu7w1P+OTCQIEGCANZJkClKIUCLgsTYDvLlsystnf01nEMuWr6d6Xqvel/1knrzxau719f/3q5vvvjr3Q/3H+8f3/3qsH2Zhy/i5mr/7ubq7cPjd68eXj6+f5o3V/fvnj4+/evh7s3478+H+493h6v3h59u6+PDT9mubj++3SOv9sPVj4erh8e397en1YfHN28OV48Ph3/cv/3H4erpsB2ufno6XB+uPty9vf/4dPfh5et/vn+4v331dNTw+e4PhzxcCPj85vdPhzhcvb57enX/cLi6//D53ffn14fbM3788e781uPh3eMPd+9evfzu1ce7h/t3dy+fHt+//P7V+y/f3b7+pWtfvnv7y++/v31z2I+dfzj+83D76ua/3R3f+P70z+ND3XzmPoL3H7Z284vtHff2qW5vThvkNv68P8cu8//Xffu/ [...]
\ No newline at end of file
+###3792:XlxV32DM 3ff4 eb8eNqV2k1vI8cVheG/woW3stW36taHtYrtODAQI0ECA+ZqIGs0YwGyJMwotoP8+ZAzlM2n4CyyGfKQ3XXfqj6n2Zpbn9z01/Gf7fLqk3/c/nz3/u7x4fPd9mndfRJXF+WHq4u3948/XN+/enx6nlcXdw/P75//fX/7Zvz+fnf3/nZ38bT79aa9v/+15sXN+7cl6kXZXfyyu7h/fHt3czx79/jmze7i8X73493bH3cXz7ttd/Hr8+5yd/Hu9u3d++fbd69e/+vp/u7m+vnA8PHod7u6OwP4+OFPz7vYXby+fb6+u99d3L37+OnT6fX+5qQff7k9ffS4e3j8+fbh+tUP1+9v7+8ebl89Pz69+un66dOHm9d/9N2nD2//+POnmze7cpj5u8M/9zfXV7/P7vDBT8d/Hu/b1cfaB/H0bsurP5zeYW2f283VcYFcxt/W5zDL+v9z3/xv7tdX [...]
\ No newline at end of file
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index 04083bd..0000000
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_base/rtl/src/ipcore/clkmgr_dcm.v" into library work</arg>
-</msg>
-
-</messages>
-
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise
index 31ed488..4cfaf34 100644
--- a/rtl/src/ipcore/clkmgr_dcm.gise
+++ b/rtl/src/ipcore/clkmgr_dcm.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
</files>
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2136445705273696504" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5299826667237415001" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2601148782814295670" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
</generated_project>
diff --git a/rtl/src/ipcore/clkmgr_dcm.ncf b/rtl/src/ipcore/clkmgr_dcm.ncf
index 0e5eb73..ef4e259 100644
--- a/rtl/src/ipcore/clkmgr_dcm.ncf
+++ b/rtl/src/ipcore/clkmgr_dcm.ncf
@@ -1,60 +1,60 @@
-# file: clkmgr_dcm.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-PIN "RESET" TIG;
-
-
+# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
+
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise
index a0ba9da..7369d3b 100644
--- a/rtl/src/ipcore/clkmgr_dcm.xise
+++ b/rtl/src/ipcore/clkmgr_dcm.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF">
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index e39a8b1..8ac8909 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -1,7 +1,7 @@
//======================================================================
//
// core_selector.v
-// -----------------
+// ---------------
// Top level wrapper that creates the Cryptech coretest system.
// The wrapper contains instances of external interface, coretest
// and the core to be tested. And if more than one core is
@@ -170,8 +170,7 @@ module core_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha1),
- .error()
+ .read_data(read_data_sha1)
);
`endif
@@ -192,8 +191,7 @@ module core_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha256),
- .error()
+ .read_data(read_data_sha256)
);
`endif
@@ -214,8 +212,7 @@ module core_selector
.address(addr_core_reg),
.write_data(sys_write_data),
- .read_data(read_data_sha512),
- .error()
+ .read_data(read_data_sha512)
);
`endif
diff --git a/rtl/src/verilog/demo_adder.v b/rtl/src/verilog/demo_adder.v
deleted file mode 100644
index 54e7f72..0000000
--- a/rtl/src/verilog/demo_adder.v
+++ /dev/null
@@ -1,108 +0,0 @@
-//======================================================================
-//
-// demo_adder.v
-// ------------
-// Simple test core for the Cryptech Novena FPGA framework. The core
-// s a 32-bit adder that allows us to verfy that we can write registers
-// get a computation done and read out the registers via the EIM.
-//
-//
-// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module demo_adder
- (
- clk, rst,
- x, y, z,
- ctl, sts
- );
-
- //
- // Ports
- //
- input wire clk; // clock
- input wire rst; // reset
-
- input wire [31: 0] x; // x
- input wire [31: 0] y; // y
- output wire [31: 0] z; // z = x + y
-
- input wire [15: 0] ctl; // control
- output wire [15: 0] sts; // status
-
-
- //
- // Internal Registers
- //
- reg [31: 0] z_reg = {32{1'b0}};
- reg [15: 0] sts_reg = {16{1'b0}};
- reg [15: 0] ctl_dly = {16{1'b0}};
-
- assign z = z_reg;
- assign sts = sts_reg;
-
-
- //
- // Control Logic
- //
- always @(posedge clk)
- //
- if (rst) ctl_dly <= {16{1'b0}};
- else ctl_dly <= ctl;
-
- /* This flag is set whenever different value is written to control register. */
-
- wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0;
-
-
- //
- // Adder Logic
- //
- always @(posedge clk)
- //
- if (rst) z_reg <= {32{1'b0}};
- else if (adder_go) z_reg <= x + y;
-
-
- //
- // Status Logic
- //
- always @(posedge clk)
- //
- if (rst) sts_reg <= {16{1'b0}};
- else if (adder_go) sts_reg <= ctl;
-
-
-endmodule
-
-//======================================================================
-// EOF demo_adder.v
-//======================================================================
diff --git a/rtl/src/verilog/sha1.v b/rtl/src/verilog/sha1.v
new file mode 100644
index 0000000..2595132
--- /dev/null
+++ b/rtl/src/verilog/sha1.v
@@ -0,0 +1,204 @@
+//======================================================================
+//
+// sha1.v
+// ------
+// Top level wrapper for the SHA-1 hash function providing
+// a simple memory like interface with 32 bit data access.
+//
+// Authors: Joachim Strömbergson, Paul Selkirk
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha1(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter ADDR_NAME0 = 8'h00;
+ parameter ADDR_NAME1 = 8'h01;
+ parameter ADDR_VERSION = 8'h02;
+
+ parameter ADDR_CTRL = 8'h08;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+
+ parameter ADDR_STATUS = 8'h09;
+ parameter STATUS_READY_BIT = 0;
+ parameter STATUS_VALID_BIT = 1;
+
+ parameter ADDR_BLOCK = 8'h10;
+
+ parameter ADDR_DIGEST = 8'h20;
+
+ parameter CORE_NAME0 = 32'h73686131; // "sha1"
+ parameter CORE_NAME1 = 32'h20202020; // " "
+ parameter CORE_VERSION = 32'h302e3530; // "0.50"
+
+ parameter BLOCK_BITS = 512;
+ parameter DIGEST_BITS = 160;
+ parameter BLOCK_WORDS = BLOCK_BITS / 32;
+ parameter DIGEST_WORDS = DIGEST_BITS / 32;
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [0 : BLOCK_BITS - 1] block_reg;
+ reg [0 : DIGEST_BITS - 1] digest_reg;
+ reg init_reg;
+ reg next_reg;
+
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [0 : BLOCK_BITS - 1] core_block;
+ wire [0 : DIGEST_BITS - 1] core_digest;
+ wire core_digest_valid;
+
+ wire [31 : 0] core_name0 = CORE_NAME0;
+ wire [31 : 0] core_name1 = CORE_NAME1;
+ wire [31 : 0] core_version = CORE_VERSION;
+ wire [31 : 0] core_ctrl;
+ wire [31 : 0] core_status;
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_ctrl = { 30'b0, next_reg, init_reg };
+ assign core_status = { 30'b0, core_digest_valid, core_ready };
+ assign core_block = block_reg;
+
+ assign read_data = tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ sha1_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .init(core_init),
+ .next(core_next),
+
+ .block(core_block),
+
+ .ready(core_ready),
+
+ .digest(core_digest),
+ .digest_valid(core_digest_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // latch in digest when ready
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ if (core_digest_valid)
+ digest_reg <= core_digest;
+ end
+
+ //----------------------------------------------------------------
+ // storage registers for mapping memory to core interface
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ init_reg <= 0;
+ next_reg <= 0;
+
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ end
+ end
+ end
+
+ always @*
+ begin
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
+ endcase
+ end
+ end
+
+ always @(posedge clk)
+ begin
+ tmp_read_data_reg <= tmp_read_data;
+ end
+
+endmodule // sha1
diff --git a/rtl/src/verilog/sha256.v b/rtl/src/verilog/sha256.v
new file mode 100644
index 0000000..d6fb133
--- /dev/null
+++ b/rtl/src/verilog/sha256.v
@@ -0,0 +1,204 @@
+//======================================================================
+//
+// sha256.v
+// ------
+// Top level wrapper for the SHA-256 hash function providing
+// a simple memory like interface with 32 bit data access.
+//
+// Authors: Joachim Strömbergson, Paul Selkirk
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha256(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter ADDR_NAME0 = 8'h00;
+ parameter ADDR_NAME1 = 8'h01;
+ parameter ADDR_VERSION = 8'h02;
+
+ parameter ADDR_CTRL = 8'h08;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+
+ parameter ADDR_STATUS = 8'h09;
+ parameter STATUS_READY_BIT = 0;
+ parameter STATUS_VALID_BIT = 1;
+
+ parameter ADDR_BLOCK = 8'h10;
+
+ parameter ADDR_DIGEST = 8'h20;
+
+ parameter CORE_NAME0 = 32'h73686132; // "sha2"
+ parameter CORE_NAME1 = 32'h2d323536; // "-256"
+ parameter CORE_VERSION = 32'h302e3830; // "0.80"
+
+ parameter BLOCK_BITS = 512;
+ parameter DIGEST_BITS = 256;
+ parameter BLOCK_WORDS = BLOCK_BITS / 32;
+ parameter DIGEST_WORDS = DIGEST_BITS / 32;
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [0 : BLOCK_BITS - 1] block_reg;
+ reg [0 : DIGEST_BITS - 1] digest_reg;
+ reg init_reg;
+ reg next_reg;
+
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [0 : BLOCK_BITS - 1] core_block;
+ wire [0 : DIGEST_BITS - 1] core_digest;
+ wire core_digest_valid;
+
+ wire [31 : 0] core_name0 = CORE_NAME0;
+ wire [31 : 0] core_name1 = CORE_NAME1;
+ wire [31 : 0] core_version = CORE_VERSION;
+ wire [31 : 0] core_ctrl;
+ wire [31 : 0] core_status;
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_ctrl = { 30'b0, next_reg, init_reg };
+ assign core_status = { 30'b0, core_digest_valid, core_ready };
+ assign core_block = block_reg;
+
+ assign read_data = tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ sha256_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .init(core_init),
+ .next(core_next),
+
+ .block(core_block),
+
+ .ready(core_ready),
+
+ .digest(core_digest),
+ .digest_valid(core_digest_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // latch in digest when ready
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ if (core_digest_valid)
+ digest_reg <= core_digest;
+ end
+
+ //----------------------------------------------------------------
+ // storage registers for mapping memory to core interface
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ init_reg <= 0;
+ next_reg <= 0;
+
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ end
+ end
+ end
+
+ always @*
+ begin
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
+ endcase
+ end
+ end
+
+ always @(posedge clk)
+ begin
+ tmp_read_data_reg <= tmp_read_data;
+ end
+
+endmodule // sha256
diff --git a/rtl/src/verilog/sha512.v b/rtl/src/verilog/sha512.v
new file mode 100644
index 0000000..4d2a9e7
--- /dev/null
+++ b/rtl/src/verilog/sha512.v
@@ -0,0 +1,241 @@
+//======================================================================
+//
+// sha512.v
+// ------
+// Top level wrapper for the SHA-512 hash function providing
+// a simple memory like interface with 32 bit data access.
+//
+// Authors: Joachim Strömbergson, Paul Selkirk
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module sha512(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter ADDR_NAME0 = 8'h00;
+ parameter ADDR_NAME1 = 8'h01;
+ parameter ADDR_VERSION = 8'h02;
+
+ parameter ADDR_CTRL = 8'h08;
+ parameter CTRL_INIT_BIT = 0;
+ parameter CTRL_NEXT_BIT = 1;
+ parameter CTRL_MODE_LOW_BIT = 2;
+ parameter CTRL_MODE_HIGH_BIT = 3;
+ parameter CTRL_WORK_FACTOR_BIT = 7;
+
+ parameter ADDR_STATUS = 8'h09;
+ parameter STATUS_READY_BIT = 0;
+ parameter STATUS_VALID_BIT = 1;
+
+ parameter ADDR_WORK_FACTOR_NUM = 8'h0a;
+
+ parameter ADDR_BLOCK = 8'h10;
+
+ parameter ADDR_DIGEST = 8'h40;
+
+ parameter CORE_NAME0 = 32'h73686132; // "sha2"
+ parameter CORE_NAME1 = 32'h2d353132; // "-512"
+ parameter CORE_VERSION = 32'h302e3830; // "0.80"
+
+ parameter MODE_SHA_512_224 = 2'h0;
+ parameter MODE_SHA_512_256 = 2'h1;
+ parameter MODE_SHA_384 = 2'h2;
+ parameter MODE_SHA_512 = 2'h3;
+
+ parameter DEFAULT_WORK_FACTOR_NUM = 32'h000f0000;
+
+ parameter BLOCK_BITS = 1024;
+ parameter DIGEST_BITS = 512;
+ parameter BLOCK_WORDS = BLOCK_BITS / 32;
+ parameter DIGEST_WORDS = DIGEST_BITS / 32;
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [0 : BLOCK_BITS - 1] block_reg;
+ reg [0 : DIGEST_BITS - 1] digest_reg;
+ reg init_reg;
+ reg next_reg;
+ reg [1 : 0] mode_reg;
+ reg work_factor_reg;
+ reg [31 : 0] work_factor_num_reg;
+
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire core_init;
+ wire core_next;
+ wire core_ready;
+ wire [1 : 0] core_mode;
+ wire core_work_factor;
+ wire [31 : 0] core_work_factor_num;
+ wire [0 : BLOCK_BITS - 1] core_block;
+ wire [0 : DIGEST_BITS - 1] core_digest;
+ wire core_digest_valid;
+
+ wire [31 : 0] core_name0 = CORE_NAME0;
+ wire [31 : 0] core_name1 = CORE_NAME1;
+ wire [31 : 0] core_version = CORE_VERSION;
+ wire [31 : 0] core_ctrl;
+ wire [31 : 0] core_status;
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign core_init = init_reg;
+ assign core_next = next_reg;
+ assign core_mode = mode_reg;
+ assign core_work_factor = work_factor_reg;
+ assign core_work_factor_num = work_factor_num_reg;
+ assign core_ctrl = {24'h000000, work_factor_reg, 3'b000,
+ mode_reg, next_reg, init_reg};
+ assign core_status = { 30'b0, core_digest_valid, core_ready };
+ assign core_block = block_reg;
+
+ assign read_data = tmp_read_data_reg;
+
+ //----------------------------------------------------------------
+ // core instantiation.
+ //----------------------------------------------------------------
+ sha512_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .init(core_init),
+ .next(core_next),
+ .mode(core_mode),
+
+ .work_factor(core_work_factor),
+ .work_factor_num(core_work_factor_num),
+
+ .block(core_block),
+
+ .ready(core_ready),
+
+ .digest(core_digest),
+ .digest_valid(core_digest_valid)
+ );
+
+
+ //----------------------------------------------------------------
+ // latch in digest when ready
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ if (core_digest_valid)
+ digest_reg <= core_digest;
+ end
+
+ //----------------------------------------------------------------
+ // storage registers for mapping memory to core interface
+ //----------------------------------------------------------------
+ always @(posedge clk)
+ begin
+ init_reg <= 0;
+ next_reg <= 0;
+ mode_reg <= MODE_SHA_512;
+ work_factor_reg <= 0;
+ work_factor_num_reg <= DEFAULT_WORK_FACTOR_NUM;
+
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ mode_reg <= write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
+ work_factor_reg <= write_data[CTRL_WORK_FACTOR_BIT];
+ end
+ else if (address == ADDR_WORK_FACTOR_NUM)
+ begin
+ work_factor_num_reg <= write_data;
+ end
+ end
+ end
+
+ always @*
+ begin
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
+ ADDR_WORK_FACTOR_NUM:
+ tmp_read_data = work_factor_num_reg;
+ endcase
+ end
+ end
+
+ always @(posedge clk)
+ begin
+ tmp_read_data_reg <= tmp_read_data;
+ end
+
+endmodule // sha512
diff --git a/sw/test-sha256/Makefile b/sw/Makefile
similarity index 50%
rename from sw/test-sha256/Makefile
rename to sw/Makefile
index ee8536e..b9fb6a2 100755
--- a/sw/test-sha256/Makefile
+++ b/sw/Makefile
@@ -1,13 +1,8 @@
-all: test-sha256 hash_tester
+all: hash_tester
.c.o:
gcc -c -Wall -o $@ $<
-test-sha256 : test-sha256.o novena-eim.o
- gcc -o test-sha256 test-sha256.o novena-eim.o
-
-test-sha256.o: test-sha256.c novena-eim.h
-
hash_tester : hash_tester.o novena-eim.o
gcc -o hash_tester hash_tester.o novena-eim.o
@@ -16,4 +11,4 @@ hash_tester.o: hash_tester.c novena-eim.h
novena-eim.o: novena-eim.c novena-eim.h
clean:
- rm -f *.o test-adder test-sha256 hash_tester
+ rm -f *.o hash_tester
diff --git a/sw/test-sha256/hash_tester.c b/sw/hash_tester.c
similarity index 100%
rename from sw/test-sha256/hash_tester.c
rename to sw/hash_tester.c
diff --git a/sw/test-sha256/novena-eim.c b/sw/novena-eim.c
similarity index 100%
rename from sw/test-sha256/novena-eim.c
rename to sw/novena-eim.c
diff --git a/sw/test-sha256/novena-eim.h b/sw/novena-eim.h
similarity index 100%
rename from sw/test-sha256/novena-eim.h
rename to sw/novena-eim.h
diff --git a/sw/test-adder/Makefile b/sw/test-adder/Makefile
deleted file mode 100755
index 5271b70..0000000
--- a/sw/test-adder/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-all: test-adder
-
-test-adder : test-adder.o novena-eim.o
- gcc -o test-adder test-adder.o novena-eim.o
-
-test-adder.o: test-adder.c novena-eim.h novena-eim.c
- gcc -c test-adder.c
- gcc -c novena-eim.c
-
-clean:
- rm -f *.o test-adder
diff --git a/sw/test-adder/novena-eim.c b/sw/test-adder/novena-eim.c
deleted file mode 100644
index 9ea76ef..0000000
--- a/sw/test-adder/novena-eim.c
+++ /dev/null
@@ -1,406 +0,0 @@
-//------------------------------------------------------------------------------
-// novena-eim.c
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/mman.h>
-#include "novena-eim.h"
-
-
-//------------------------------------------------------------------------------
-// Variables
-//------------------------------------------------------------------------------
-static long mem_page_size = 0;
-static int mem_dev_fd = -1;
-static void * mem_map_ptr = MAP_FAILED;
-static off_t mem_base_addr = 0;
-
-
-//------------------------------------------------------------------------------
-int eim_setup()
-//------------------------------------------------------------------------------
-{
- // register cleanup function
- int ok = atexit(_eim_cleanup);
- if (ok != 0)
- { printf("ERROR: atexit() failed.\n");
- return -1;
- }
-
- // determine memory page size to use in mmap()
- mem_page_size = sysconf(_SC_PAGESIZE);
- if (mem_page_size < 1)
- { printf("ERROR: sysconf(_SC_PAGESIZE) == %l\n", mem_page_size);
- return -1;
- }
-
- // try to open memory device
- mem_dev_fd = open(MEMORY_DEVICE, O_RDWR | O_SYNC);
- if (mem_dev_fd == -1)
- { printf("ERROR: open(%s) failed.\n", MEMORY_DEVICE);
- return -1;
- }
-
- /* Several blocks in the CPU have common pins, we can use I/O MUX Controller
- * to configure what block will actually use I/O pins. We wait EIM module to be able
- * to communicate with the on-board FPGA. Let's configure IOMUXC accordingly.
- */
- _eim_setup_iomuxc();
-
- /* We need to enable clocking of EIM block in order to be able to use it.
- * Let's configure Clock Controller Module accordingly.
- */
- _eim_setup_ccm();
-
- /* We need to properly configure EIM mode and all the corresponding parameters.
- * That's a lot of code, let's do it now.
- */
- _eim_setup_eim();
-
-
- // done
- return 1;
-}
-
-
-//------------------------------------------------------------------------------
-void _eim_cleanup()
-//------------------------------------------------------------------------------
-{
- // unmap memory if needed
- if (mem_map_ptr != MAP_FAILED)
- { int ok = munmap(mem_map_ptr, mem_page_size);
- if (ok != 0) printf("WARNING: munmap() failed.\n");
- }
-
- // close memory device if needed
- if (mem_dev_fd != -1)
- { int ok = close(mem_dev_fd);
- if (ok != 0) printf("WARNING: close() failed.\n");
- }
-}
-
-
-//------------------------------------------------------------------------------
-void _eim_setup_iomuxc()
-//------------------------------------------------------------------------------
-{
- // create structures
- struct IOMUXC_SW_MUX_CTL_PAD_EIM reg_mux; // mux control register
- struct IOMUXC_SW_PAD_CTL_PAD_EIM reg_pad; // pad control register
-
- // setup mux control register
- reg_mux.mux_mode = IOMUXC_MUX_MODE_ALT0; // ALT0 mode must be used for EIM
- reg_mux.sion = 0; // forced input not needed
- reg_mux.reserved_3 = 0; // must be 0
- reg_mux.reserved_31_5 = 0; // must be 0
-
- // setup pad control register
- reg_pad.sre = IOMUXC_PAD_CTL_SRE_FAST; // fast slew rate
- reg_pad.dse = IOMUXC_PAD_CTL_DSE_33_OHM; // highest drive strength
- reg_pad.speed = IOMUXC_PAD_CTL_SPEED_MEDIUM_10; // medium speed
- reg_pad.ode = IOMUXC_PAD_CTL_ODE_DISABLED; // open drain not needed
- reg_pad.pke = IOMUXC_PAD_CTL_PKE_DISABLED; // neither pull nor keeper are needed
- reg_pad.pue = IOMUXC_PAD_CTL_PUE_PULL; // doesn't matter actually, because PKE is disabled
- reg_pad.pus = IOMUXC_PAD_CTL_PUS_100K_OHM_PU; // doesn't matter actually, because PKE is disabled
- reg_pad.hys = IOMUXC_PAD_CTL_HYS_DISABLED; // use CMOS, not Schmitt trigger input
- reg_pad.reserved_2_1 = 0; // must be 0
- reg_pad.reserved_10_8 = 0; // must be 0
- reg_pad.reserved_31_17 = 0; // must be 0
-
- // all the pins must be configured to use the same ALT0 mode
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_RW, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B, (unsigned int *)®_mux);
- eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, (unsigned int *)®_mux);
-
- // we need to configure all the I/O pads too
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_RW, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B, (unsigned int *)®_pad);
- eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, (unsigned int *)®_pad);
-}
-
-
-//------------------------------------------------------------------------------
-void _eim_setup_ccm()
-//------------------------------------------------------------------------------
-{
- // create structure
- struct CCM_CCGR6 ccm_ccgr6;
-
- // read register
- eim_read_32(CCM_CCGR6, (unsigned int *)&ccm_ccgr6);
-
- // modify register
- ccm_ccgr6.cg0_usboh3 = CCM_CGR_ON_EXCEPT_STOP;
- ccm_ccgr6.cg1_usdhc1 = CCM_CGR_OFF;
- ccm_ccgr6.cg2_usdhc2 = CCM_CGR_ON_EXCEPT_STOP;
- ccm_ccgr6.cg3_usdhc3 = CCM_CGR_ON_EXCEPT_STOP;
-
- ccm_ccgr6.cg3_usdhc4 = CCM_CGR_OFF;
- ccm_ccgr6.cg5_eim_slow = CCM_CGR_ON_EXCEPT_STOP;
- ccm_ccgr6.cg6_vdoaxiclk = CCM_CGR_OFF;
- ccm_ccgr6.cg7_vpu = CCM_CGR_OFF;
-
- ccm_ccgr6.cg8_reserved = 0;
- ccm_ccgr6.cg9_reserved = 0;
- ccm_ccgr6.cg10_reserved = 0;
- ccm_ccgr6.cg11_reserved = 0;
- ccm_ccgr6.cg12_reserved = 0;
- ccm_ccgr6.cg13_reserved = 0;
- ccm_ccgr6.cg14_reserved = 0;
- ccm_ccgr6.cg15_reserved = 0;
-
- // write register
- eim_write_32(CCM_CCGR6, (unsigned int *)&ccm_ccgr6);
-}
-
-
-//------------------------------------------------------------------------------
-void _eim_setup_eim()
-//------------------------------------------------------------------------------
-{
- // create structures
- struct EIM_CS_GCR1 gcr1;
- struct EIM_CS_GCR2 gcr2;
- struct EIM_CS_RCR1 rcr1;
- struct EIM_CS_RCR2 rcr2;
- struct EIM_CS_WCR1 wcr1;
- struct EIM_CS_WCR2 wcr2;
-
- struct EIM_WCR wcr;
- struct EIM_WIAR wiar;
- struct EIM_EAR ear;
-
- // read all the registers
- eim_read_32(EIM_CS0GCR1, (unsigned int *)&gcr1);
- eim_read_32(EIM_CS0GCR2, (unsigned int *)&gcr2);
- eim_read_32(EIM_CS0RCR1, (unsigned int *)&rcr1);
- eim_read_32(EIM_CS0RCR2, (unsigned int *)&rcr2);
- eim_read_32(EIM_CS0WCR1, (unsigned int *)&wcr1);
- eim_read_32(EIM_CS0WCR2, (unsigned int *)&wcr2);
-
- eim_read_32(EIM_WCR, (unsigned int *)&wcr);
- eim_read_32(EIM_WIAR, (unsigned int *)&wiar);
- eim_read_32(EIM_EAR, (unsigned int *)&ear);
-
- // manipulate registers as needed
- gcr1.csen = 1; // chip select is enabled |
- gcr1.swr = 1; // write is sync |
- gcr1.srd = 1; // read is sync |
- gcr1.mum = 1; // address and data are multiplexed |
- gcr1.wfl = 0; // write latency is not fixed |
- gcr1.rfl = 0; // read latency is not fixed |
- gcr1.cre = 0; // CRE signal not needed |
- //gcr1.crep = x; // don't care, CRE not used |
- gcr1.bl = 4; // burst length | ?
- gcr1.wc = 0; // write is not continuous | ?
- gcr1.bcd = 3; // BCLK divisor is 3+1=4 |
- gcr1.bcs = 1; // delay from ~CS to BCLK is 1 cycle |
- gcr1.dsz = 1; // 16 bits per databeat at DATA[15:0] |
- gcr1.sp = 0; // supervisor protection is disabled |
- gcr1.csrec = 1; // ~CS recovery is 1 cycle |
- gcr1.aus = 1; // address is not shifted |
- gcr1.gbc = 1; // ~CS gap is 1 cycle |
- gcr1.wp = 0; // write protection is not enabled |
- //gcr1.psz = x; // don't care, page mode is not used |
-
- gcr2.adh = 0; // address hold duration is 1 cycle |
- //gcr2.daps = x; // don't care, DTACK is not used |
- gcr2.dae = 0; // DTACK is not used |
- //gcr2.dap = x; // don't care, DTACK is not used |
- gcr2.mux16_byp_grant = 1; // enable grant mechanism | ?
- gcr2.reserved_3_2 = 0; // must be 0 |
- gcr2.reserved_11_10 = 0; // must be 0 |
- gcr2.reserved_31_13 = 0; // must be 0 |
-
- //rcr1.rcsn = x; // don't care in sync mode |
- rcr1.rcsa = 0; // no delay for ~CS needed |
- //rcr1.oen = x; // don't care in sync mode |
- rcr1.oea = 0; // no delay for ~OE needed |
- rcr1.radvn = 0; // no delay for ~LBA needed |
- rcr1.ral = 0; // clear ~LBA when needed |
- rcr1.radva = 0; // no delay for ~LBA needed |
- rcr1.rwsc = 1; // one wait state |
- rcr1.reserved_3 = 0; // must be 0 |
- rcr1.reserved_7 = 0; // must be 0 |
- rcr1.reserved_11 = 0; // must be 0 |
- rcr1.reserved_15 = 0; // must be 0 |
- rcr1.reserved_23 = 0; // must be 0 |
- rcr1.reserved_31_30 = 0; // must be 0 |
-
- //rcr2.rben = x; // don't care in sync mode |
- rcr2.rbe = 0; // BE is disabled |
- //rcr2.rbea = x; // don't care when BE is not used |
- rcr2.rl = 0; // read latency is 0 | ?
- //rcr2.pat = x; // don't care when page read is not used |
- rcr2.apr = 0; // page read mode is not used |
- rcr2.reserved_7 = 0; // must be 0 |
- rcr2.reserved_11_10 = 0; // must be 0 |
- rcr2.reserved_31_16 = 0; // must be 0 |
-
- //wcr1.wcsn = x; // don't care in sync mode |
- wcr1.wcsa = 0; // no delay for ~CS needed |
- //wcr1.wen = x; // don't care in sync mode |
- wcr1.wea = 0; // no delay for ~WR_N needed |
- //wcr1.wben = x; // don't care in sync mode |
- //wcr1.wbea = x; // don't care in sync mode |
- wcr1.wadvn = 0; // no delay for ~LBA needed |
- wcr1.wadva = 0; // no delay for ~LBA needed |
- wcr1.wwsc = 1; // no wait state in needed |
- wcr1.wbed = 1; // BE is disabled |
- wcr1.wal = 0; // clear ~LBA when needed |
-
- wcr2.wbcdd = 0; // write clock division is not needed |
- wcr2.reserved_31_1 = 0; // must be 0 |
-
- wcr.bcm = 0; // clock is only active during access |
- //wcr.gbcd = x; // don't care when BCM=0 |
- wcr.inten = 0; // interrupt is not used |
- //wcr.intpol = x; // don't care when interrupt is not used |
- wcr.wdog_en = 1; // watchdog is enabled |
- wcr.wdog_limit = 00; // timeout is 128 BCLK cycles |
- wcr.reserved_3 = 0; // must be 0 |
- wcr.reserved_7_6 = 0; // must be 0 |
- wcr.reserved_31_11 = 0; // must be 0 |
-
- wiar.ips_req = 0; // IPS not needed |
- wiar.ips_ack = 0; // IPS not needed |
- //wiar.irq = x; // don't touch |
- //wiar.errst = x; // don't touch |
- wiar.aclk_en = 1; // clock is enabled |
- wiar.reserved_31_5 = 0; // must be 0 |
-
- //ear.error_addr = x; // read-only |
-
- // write modified registers
- eim_write_32(EIM_CS0GCR1, (unsigned int *)&gcr1);
- eim_write_32(EIM_CS0GCR2, (unsigned int *)&gcr2);
- eim_write_32(EIM_CS0RCR1, (unsigned int *)&rcr1);
- eim_write_32(EIM_CS0RCR2, (unsigned int *)&rcr2);
- eim_write_32(EIM_CS0WCR1, (unsigned int *)&wcr1);
- eim_write_32(EIM_CS0WCR2, (unsigned int *)&wcr2);
- eim_write_32(EIM_WCR, (unsigned int *)&wcr);
- eim_write_32(EIM_WIAR, (unsigned int *)&wiar);/*
- eim_write_32(EIM_EAR, (unsigned int *)&ear);*/
-}
-
-
-//------------------------------------------------------------------------------
-void eim_write_32(off_t offset, unsigned int *pvalue)
-//------------------------------------------------------------------------------
-{
- // calculate memory offset
- unsigned int *ptr = (unsigned int *)_eim_calc_offset(offset);
-
- // write data to memory
- memcpy(ptr, pvalue, sizeof(unsigned int));
-}
-
-//------------------------------------------------------------------------------
-void eim_read_32(off_t offset, unsigned int *pvalue)
-//------------------------------------------------------------------------------
-{
- // calculate memory offset
- unsigned int *ptr = (unsigned int *)_eim_calc_offset(offset);
-
- // read data from memory
- memcpy(pvalue, ptr, sizeof(unsigned int));
-}
-
-
-//------------------------------------------------------------------------------
-off_t _eim_calc_offset(off_t offset)
-//------------------------------------------------------------------------------
-{
- // make sure that memory is mapped
- if (mem_map_ptr == MAP_FAILED) _eim_remap_mem(offset);
-
- // calculate starting and ending addresses of currently mapped page
- off_t offset_low = mem_base_addr;
- off_t offset_high = mem_base_addr + (mem_page_size - 1);
-
- // check that offset is in currently mapped page, remap new page otherwise
- if ((offset < offset_low) || (offset > offset_high)) _eim_remap_mem(offset);
-
- // calculate pointer
- return (off_t)mem_map_ptr + (offset - mem_base_addr);
-}
-
-
-//------------------------------------------------------------------------------
-void _eim_remap_mem(off_t offset)
-//------------------------------------------------------------------------------
-{
- // unmap old memory page if needed
- if (mem_map_ptr != MAP_FAILED)
- { int ok = munmap(mem_map_ptr, mem_page_size);
- if (ok != 0)
- { printf("ERROR: munmap() failed.\n");
- exit(EXIT_FAILURE);
- }
- }
-
- // calculate starting address of new page
- while (offset % mem_page_size) offset--;
-
- // try to map new memory page
- mem_map_ptr = mmap(NULL, mem_page_size, PROT_READ | PROT_WRITE, MAP_SHARED, mem_dev_fd, offset);
- if (mem_map_ptr == MAP_FAILED)
- { printf("ERROR: mmap() failed.\n");
- exit(EXIT_FAILURE);
- }
-
- // save last mapped page address
- mem_base_addr = offset;
-}
-
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/sw/test-adder/novena-eim.h b/sw/test-adder/novena-eim.h
deleted file mode 100644
index fdcf5a5..0000000
--- a/sw/test-adder/novena-eim.h
+++ /dev/null
@@ -1,297 +0,0 @@
-//------------------------------------------------------------------------------
-// novena-eim.h
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Defined Values
-//------------------------------------------------------------------------------
-#define MEMORY_DEVICE "/dev/mem"
-
-
-//------------------------------------------------------------------------------
-// IOMUXC Values
-//------------------------------------------------------------------------------
-#define IOMUXC_MUX_MODE_ALT0 0 // 000
-
-#define IOMUXC_PAD_CTL_SRE_FAST 1 // 1
-#define IOMUXC_PAD_CTL_DSE_33_OHM 7 // 111
-#define IOMUXC_PAD_CTL_SPEED_MEDIUM_10 2 // 10
-#define IOMUXC_PAD_CTL_ODE_DISABLED 0 // 0
-#define IOMUXC_PAD_CTL_PKE_DISABLED 0 // 0
-#define IOMUXC_PAD_CTL_PUE_PULL 1 // 1
-#define IOMUXC_PAD_CTL_PUS_100K_OHM_PU 2 // 10
-#define IOMUXC_PAD_CTL_HYS_DISABLED 0 // 0
-
-//------------------------------------------------------------------------------
-// CCM Values
-//------------------------------------------------------------------------------
-#define CCM_CGR_OFF 0 // 00
-#define CCM_CGR_ON_EXCEPT_STOP 3 // 11
-
-
-//------------------------------------------------------------------------------
-// CPU Registers
-//------------------------------------------------------------------------------
-enum IMX6DQ_REGISTER_OFFSET
-{
- IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0x020E00F8,
- IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0x020E0100,
- IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0x020E0104,
- IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0x020E0108,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 = 0x020E0114,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 = 0x020E0118,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 = 0x020E011C,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 = 0x020E0120,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 = 0x020E0124,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 = 0x020E0128,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 = 0x020E012C,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 = 0x020E0130,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 = 0x020E0134,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 = 0x020E0138,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 = 0x020E013C,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 = 0x020E0140,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 = 0x020E0144,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 = 0x020E0148,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 = 0x020E014C,
- IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 = 0x020E0150,
- IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B = 0x020E0154,
- IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK = 0x020E0158,
-
- IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B = 0x020E040C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B = 0x020E0414,
- IOMUXC_SW_PAD_CTL_PAD_EIM_RW = 0x020E0418,
- IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B = 0x020E041C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 = 0x020E0428,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 = 0x020E042C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 = 0x020E0430,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 = 0x020E0434,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 = 0x020E0438,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 = 0x020E043C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 = 0x020E0440,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 = 0x020E0444,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 = 0x020E0448,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 = 0x020E044C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 = 0x020E0450,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 = 0x020E0454,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 = 0x020E0458,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 = 0x020E045C,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 = 0x020E0460,
- IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 = 0x020E0464,
- IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B = 0x020E0468,
- IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK = 0x020E046C,
-
- CCM_CCGR6 = 0x020C4080,
-
- EIM_CS0GCR1 = 0x021B8000,
- EIM_CS0GCR2 = 0x021B8004,
- EIM_CS0RCR1 = 0x021B8008,
- EIM_CS0RCR2 = 0x021B800C,
- EIM_CS0WCR1 = 0x021B8010,
- EIM_CS0WCR2 = 0x021B8014,
-
- EIM_WCR = 0x021B8090,
- EIM_WIAR = 0x021B8094,
- EIM_EAR = 0x021B8098,
-
- EIM_BASE_ADDR = 0x08000000
-};
-
-
-//------------------------------------------------------------------------------
-struct IOMUXC_SW_MUX_CTL_PAD_EIM
-//------------------------------------------------------------------------------
-{
- unsigned int mux_mode : 3;
- unsigned int reserved_3 : 1;
- unsigned int sion : 1;
- unsigned int reserved_31_5 : 27;
-};
-//------------------------------------------------------------------------------
-struct IOMUXC_SW_PAD_CTL_PAD_EIM
-//------------------------------------------------------------------------------
-{
- unsigned int sre : 1;
- unsigned int reserved_2_1 : 2;
- unsigned int dse : 3;
- unsigned int speed : 2;
- unsigned int reserved_10_8 : 3;
- unsigned int ode : 1;
- unsigned int pke : 1;
- unsigned int pue : 1;
- unsigned int pus : 2;
- unsigned int hys : 1;
- unsigned int reserved_31_17 : 15;
-};
-
-
-//------------------------------------------------------------------------------
-struct CCM_CCGR6
-//------------------------------------------------------------------------------
-{
- unsigned int cg0_usboh3 : 2;
- unsigned int cg1_usdhc1 : 2;
- unsigned int cg2_usdhc2 : 2;
- unsigned int cg3_usdhc3 : 2;
-
- unsigned int cg3_usdhc4 : 2;
- unsigned int cg5_eim_slow : 2;
- unsigned int cg6_vdoaxiclk : 2;
- unsigned int cg7_vpu : 2;
-
- unsigned int cg8_reserved : 2;
- unsigned int cg9_reserved : 2;
- unsigned int cg10_reserved : 2;
- unsigned int cg11_reserved : 2;
-
- unsigned int cg12_reserved : 2;
- unsigned int cg13_reserved : 2;
- unsigned int cg14_reserved : 2;
- unsigned int cg15_reserved : 2;
-};
-
-
-//------------------------------------------------------------------------------
-struct EIM_CS_GCR1
-//------------------------------------------------------------------------------
-{
- unsigned int csen : 1;
- unsigned int swr : 1;
- unsigned int srd : 1;
- unsigned int mum : 1;
- unsigned int wfl : 1;
- unsigned int rfl : 1;
- unsigned int cre : 1;
- unsigned int crep : 1;
- unsigned int bl : 3;
- unsigned int wc : 1;
- unsigned int bcd : 2;
- unsigned int bcs : 2;
- unsigned int dsz : 3;
- unsigned int sp : 1;
- unsigned int csrec : 3;
- unsigned int aus : 1;
- unsigned int gbc : 3;
- unsigned int wp : 1;
- unsigned int psz : 4;
-};
-//------------------------------------------------------------------------------
-struct EIM_CS_GCR2
-//------------------------------------------------------------------------------
-{
- unsigned int adh : 2;
- unsigned int reserved_3_2 : 2;
- unsigned int daps : 4;
- unsigned int dae : 1;
- unsigned int dap : 1;
- unsigned int reserved_11_10 : 2;
- unsigned int mux16_byp_grant : 1;
- unsigned int reserved_31_13 : 19;
-};
-//------------------------------------------------------------------------------
-struct EIM_CS_RCR1
-//------------------------------------------------------------------------------
-{
- unsigned int rcsn : 3;
- unsigned int reserved_3 : 1;
- unsigned int rcsa : 3;
- unsigned int reserved_7 : 1;
- unsigned int oen : 3;
- unsigned int reserved_11 : 1;
- unsigned int oea : 3;
- unsigned int reserved_15 : 1;
- unsigned int radvn : 3;
- unsigned int ral : 1;
- unsigned int radva : 3;
- unsigned int reserved_23 : 1;
- unsigned int rwsc : 6;
- unsigned int reserved_31_30 : 2;
-};
-//------------------------------------------------------------------------------
-struct EIM_CS_RCR2
-//------------------------------------------------------------------------------
-{
- unsigned int rben : 3;
- unsigned int rbe : 1;
- unsigned int rbea : 3;
- unsigned int reserved_7 : 1;
- unsigned int rl : 2;
- unsigned int reserved_11_10 : 2;
- unsigned int pat : 3;
- unsigned int apr : 1;
- unsigned int reserved_31_16 : 16;
-};
-//------------------------------------------------------------------------------
-struct EIM_CS_WCR1
-//------------------------------------------------------------------------------
-{
- unsigned int wcsn : 3;
- unsigned int wcsa : 3;
- unsigned int wen : 3;
- unsigned int wea : 3;
- unsigned int wben : 3;
- unsigned int wbea : 3;
- unsigned int wadvn : 3;
- unsigned int wadva : 3;
- unsigned int wwsc : 6;
- unsigned int wbed : 1;
- unsigned int wal : 1;
-};
-//------------------------------------------------------------------------------
-struct EIM_CS_WCR2
-//------------------------------------------------------------------------------
-{
- unsigned int wbcdd : 1;
- unsigned int reserved_31_1 : 31;
-};
-//------------------------------------------------------------------------------
-struct EIM_WCR
-//------------------------------------------------------------------------------
-{
- unsigned int bcm : 1;
- unsigned int gbcd : 2;
- unsigned int reserved_3 : 1;
- unsigned int inten : 1;
- unsigned int intpol : 1;
- unsigned int reserved_7_6 : 2;
- unsigned int wdog_en : 1;
- unsigned int wdog_limit : 2;
- unsigned int reserved_31_11 : 21;
-};
-//------------------------------------------------------------------------------
-struct EIM_WIAR
-//------------------------------------------------------------------------------
-{
- unsigned int ips_req : 1;
- unsigned int ips_ack : 1;
- unsigned int irq : 1;
- unsigned int errst : 1;
- unsigned int aclk_en : 1;
- unsigned int reserved_31_5 : 27;
-};
-//------------------------------------------------------------------------------
-struct EIM_EAR
-//------------------------------------------------------------------------------
-{
- unsigned int error_addr : 32;
-};
-
-
-//------------------------------------------------------------------------------
-// Prototypes
-//------------------------------------------------------------------------------
-int eim_setup ();
-void eim_write_32 (off_t, unsigned int *);
-void eim_read_32 (off_t, unsigned int *);
-
-void _eim_setup_iomuxc ();
-void _eim_setup_ccm ();
-void _eim_setup_eim ();
-void _eim_cleanup ();
-off_t _eim_calc_offset (off_t);
-void _eim_remap_mem (off_t);
-
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/sw/test-adder/test-adder.c b/sw/test-adder/test-adder.c
deleted file mode 100644
index 70415d8..0000000
--- a/sw/test-adder/test-adder.c
+++ /dev/null
@@ -1,206 +0,0 @@
-//------------------------------------------------------------------------------
-// setup-eim.c
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include <stdio.h>
-#include <stdlib.h>
-#include "novena-eim.h"
-
-
-//------------------------------------------------------------------------------
-// Demo Adder
-//------------------------------------------------------------------------------
-#define DEMO_ADDER_BASE_ADDR (0x3210)
-#define DEMO_ADDER_REG_X (EIM_BASE_ADDR + DEMO_ADDER_BASE_ADDR + (0<<2))
-#define DEMO_ADDER_REG_Y (EIM_BASE_ADDR + DEMO_ADDER_BASE_ADDR + (1<<2))
-#define DEMO_ADDER_REG_Z (EIM_BASE_ADDR + DEMO_ADDER_BASE_ADDR + (2<<2))
-#define DEMO_ADDER_REG_SC (EIM_BASE_ADDR + DEMO_ADDER_BASE_ADDR + (3<<2))
-
-
-//------------------------------------------------------------------------------
-// Prototypes
-//------------------------------------------------------------------------------
-unsigned int demo_adder_test_round (unsigned int, unsigned int);
-unsigned int lfsr_next_x (unsigned int);
-unsigned int lfsr_next_y (unsigned int);
-
-
-//------------------------------------------------------------------------------
-// Testing Parameters
-//------------------------------------------------------------------------------
-const int NUM_TEST_ROUNDS = 10000;
-const int PRINT_XYZ_VALUES = 1;
-
-
-//------------------------------------------------------------------------------
-int main()
-//------------------------------------------------------------------------------
-{
- // try to setup eim (return value should be 1)
- printf("Configuring EIM .. ");
- int ok = eim_setup();
- if (ok < 1)
- { printf("ERROR\n");
- return EXIT_FAILURE;
- }
- else printf("OK\n");
-
- // run test
- int i;
- unsigned int x = 0x12341234, y = 0xABCDABCD, zyx;
- printf("Testing started.\n");
- for (i=0; i<NUM_TEST_ROUNDS; i++)
- {
- // run another round
- unsigned int z = demo_adder_test_round(x, y);
-
- // calculate correct answer
- zyx = x + y;
-
- // check result
- if (z != zyx)
- { printf("ERROR: round %10d of %10d: x == 0x%08X, y == 0x%08X, z == 0x%08X [z should be 0x%08X]\n", i+1, NUM_TEST_ROUNDS, x, y, z, zyx);
- exit(EXIT_FAILURE);
- }
- else if (PRINT_XYZ_VALUES) printf("OK: round %10d of %10d: x == 0x%08X, y == 0x%08X, z == 0x%08X\n", i+1, NUM_TEST_ROUNDS, x, y, z);
-
- // update input values
- x = lfsr_next_x(x);
- y = lfsr_next_x(y);
- }
-
- // ok
- printf("Testing completed successfully.\n");
-
- // done
- return EXIT_SUCCESS;
-}
-
-
-//------------------------------------------------------------------------------
-unsigned int demo_adder_test_round(unsigned int x, unsigned int y)
-//------------------------------------------------------------------------------
-{
- // write x
- eim_write_32(DEMO_ADDER_REG_X, &x);
-
- // write y
- eim_write_32(DEMO_ADDER_REG_Y, &y);
-
- /* To make adder calculate something we need to change its control register,
- * so we read it, increment and write back. Control register is in the lower 16 bits.
- */
- unsigned int ctl;
- eim_read_32(DEMO_ADDER_REG_SC, &ctl);
- ctl += 1;
- ctl &= 0x0000FFFF;
- eim_write_32(DEMO_ADDER_REG_SC, &ctl);
-
- /* When adder is done, it will write new control value into its status register. Adder has 1-cycle latency
- * which is very small, we don't even need to poll, just check that status was updated. Status register is
- * in the upper 16 bits.
- */
- unsigned int sts;
- eim_read_32(DEMO_ADDER_REG_SC, &sts);
- sts >>= 16;
- if (sts != ctl)
- { printf("ERROR: Adder timeout!\n");
- exit(EXIT_FAILURE);
- }
-
- // read z
- unsigned int z;
- eim_read_32(DEMO_ADDER_REG_Z, &z);
-
- // uncomment to trigger an error
- /**
- z++;
- **/
-
- // done
- return z;
-}
-
-
-//------------------------------------------------------------------------------
-unsigned int lfsr_next_x(unsigned int value)
-//------------------------------------------------------------------------------
-{
- //
- // [32, 31, 29, 28, 27, 25, 24, 23, 21, 19, 17, 14, 10, 6, 4, 2]
- // 0 1 3 4 5 7 8 9 11 13 15 18 22 24 28 30
- //
-
- unsigned int carry = 0;
-
- carry ^= (value >> 0);
- carry ^= (value >> 1);
- carry ^= (value >> 3);
- carry ^= (value >> 4);
-
- carry ^= (value >> 5);
- carry ^= (value >> 7);
- carry ^= (value >> 8);
- carry ^= (value >> 9);
-
- carry ^= (value >> 11);
- carry ^= (value >> 13);
- carry ^= (value >> 15);
- carry ^= (value >> 18);
-
- carry ^= (value >> 22);
- carry ^= (value >> 24);
- carry ^= (value >> 28);
- carry ^= (value >> 30);
-
- value >>= 1, value |= (carry << 31);
-
- return value;
-}
-
-
-//------------------------------------------------------------------------------
-unsigned int lfsr_next_y(unsigned int value)
-//------------------------------------------------------------------------------
-{
- //
- // [32, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 1]
- // 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31
- //
-
- unsigned int carry = 0;
-
- carry ^= (value >> 0);
- carry ^= (value >> 15);
- carry ^= (value >> 16);
- carry ^= (value >> 17);
-
- carry ^= (value >> 18);
- carry ^= (value >> 19);
- carry ^= (value >> 20);
- carry ^= (value >> 21);
-
- carry ^= (value >> 22);
- carry ^= (value >> 23);
- carry ^= (value >> 24);
- carry ^= (value >> 25);
-
- carry ^= (value >> 26);
- carry ^= (value >> 27);
- carry ^= (value >> 28);
- carry ^= (value >> 31);
-
- value >>= 1, value |= (carry << 31);
-
- return value;
-}
-
-
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
diff --git a/sw/test-sha256/test-sha256.c b/sw/test-sha256/test-sha256.c
deleted file mode 100644
index 0ea0d8c..0000000
--- a/sw/test-sha256/test-sha256.c
+++ /dev/null
@@ -1,179 +0,0 @@
-//======================================================================
-//
-// test-sha256.c
-// -------------
-// test program for Cryptech Novena framwwork with EIM interface
-// using the sha256 core.
-//
-//======================================================================
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "novena-eim.h"
-
-
-//------------------------------------------------------------------------------
-// Defines
-//
-// Symbolic names for the SHA256 core API.
-//------------------------------------------------------------------------------
-#define SHA256_PREFIX (0x0000)
-#define SHA256_BASE (EIM_BASE_ADDR + SHA256_PREFIX)
-
-#define ADDR_NAME0 (SHA256_BASE + (0x00 << 2))
-#define ADDR_NAME1 (SHA256_BASE + (0x01 << 2))
-#define ADDR_VERSION (SHA256_BASE + (0x02 << 2))
-
-#define ADDR_CTRL (SHA256_BASE + (0x08 << 2))
-#define CTRL_INIT_BIT 0
-#define CTRL_NEXT_BIT 1
-
-#define ADDR_STATUS (SHA256_BASE + (0x09 << 2))
-#define STATUS_READY_BIT 0
-#define STATUS_VALID_BIT 1
-
-#define ADDR_BLOCK0 (SHA256_BASE + (0x10 << 2))
-#define ADDR_BLOCK1 (SHA256_BASE + (0x11 << 2))
-#define ADDR_BLOCK2 (SHA256_BASE + (0x12 << 2))
-#define ADDR_BLOCK3 (SHA256_BASE + (0x13 << 2))
-#define ADDR_BLOCK4 (SHA256_BASE + (0x14 << 2))
-#define ADDR_BLOCK5 (SHA256_BASE + (0x15 << 2))
-#define ADDR_BLOCK6 (SHA256_BASE + (0x16 << 2))
-#define ADDR_BLOCK7 (SHA256_BASE + (0x17 << 2))
-#define ADDR_BLOCK8 (SHA256_BASE + (0x18 << 2))
-#define ADDR_BLOCK9 (SHA256_BASE + (0x19 << 2))
-#define ADDR_BLOCK10 (SHA256_BASE + (0x1a << 2))
-#define ADDR_BLOCK11 (SHA256_BASE + (0x1b << 2))
-#define ADDR_BLOCK12 (SHA256_BASE + (0x1c << 2))
-#define ADDR_BLOCK13 (SHA256_BASE + (0x1d << 2))
-#define ADDR_BLOCK14 (SHA256_BASE + (0x1e << 2))
-#define ADDR_BLOCK15 (SHA256_BASE + (0x1f << 2))
-
-#define ADDR_DIGEST0 (SHA256_BASE + (0x20 << 2))
-#define ADDR_DIGEST1 (SHA256_BASE + (0x21 << 2))
-#define ADDR_DIGEST2 (SHA256_BASE + (0x22 << 2))
-#define ADDR_DIGEST3 (SHA256_BASE + (0x23 << 2))
-#define ADDR_DIGEST4 (SHA256_BASE + (0x24 << 2))
-#define ADDR_DIGEST5 (SHA256_BASE + (0x25 << 2))
-#define ADDR_DIGEST6 (SHA256_BASE + (0x26 << 2))
-#define ADDR_DIGEST7 (SHA256_BASE + (0x27 << 2))
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-uint32_t get_w32(uint32_t addr)
-{
- unsigned int read_data;
-
- eim_read_32(addr, &read_data);
-
- return read_data;
-}
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-void test_single_block()
-{
- uint32_t write_data;
-
- write_data = 0x61626380;
- eim_write_32(ADDR_BLOCK0, &write_data);
- write_data = 0x00000000;
- eim_write_32(ADDR_BLOCK1, &write_data);
- eim_write_32(ADDR_BLOCK2, &write_data);
- eim_write_32(ADDR_BLOCK3, &write_data);
- eim_write_32(ADDR_BLOCK4, &write_data);
- eim_write_32(ADDR_BLOCK5, &write_data);
- eim_write_32(ADDR_BLOCK6, &write_data);
- eim_write_32(ADDR_BLOCK7, &write_data);
- eim_write_32(ADDR_BLOCK8, &write_data);
- eim_write_32(ADDR_BLOCK9, &write_data);
- eim_write_32(ADDR_BLOCK10, &write_data);
- eim_write_32(ADDR_BLOCK11, &write_data);
- eim_write_32(ADDR_BLOCK12, &write_data);
- eim_write_32(ADDR_BLOCK13, &write_data);
- eim_write_32(ADDR_BLOCK14, &write_data);
- write_data = 0x00000018;
- eim_write_32(ADDR_BLOCK15, &write_data);
-
- write_data = 0x00000001;
- eim_write_32(ADDR_CTRL, &write_data);
-
- printf("digest0 = 0x%08x\n", get_w32(ADDR_DIGEST0));
- printf("digest1 = 0x%08x\n", get_w32(ADDR_DIGEST1));
- printf("digest2 = 0x%08x\n", get_w32(ADDR_DIGEST2));
- printf("digest3 = 0x%08x\n", get_w32(ADDR_DIGEST3));
- printf("digest4 = 0x%08x\n", get_w32(ADDR_DIGEST4));
- printf("digest5 = 0x%08x\n", get_w32(ADDR_DIGEST5));
- printf("digest6 = 0x%08x\n", get_w32(ADDR_DIGEST6));
- printf("digest7 = 0x%08x\n", get_w32(ADDR_DIGEST7));
-
- // What we want to see:
- // res0 = 256'hBA7816BF8F01CFEA414140DE5DAE2223B00361A396177A9CB410FF61F20015AD;
-
-}
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-void test_dual_block()
-{
- // Dual block test vectors as specified by NIST.
- // tc1_0 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
- // res1_0 = 256'h85E655D6417A17953363376A624CDE5C76E09589CAC5F811CC4B32C1F20E533A;
- // tc1_1 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
- // res1_1 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
-
-
-}
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-void test_sha256()
-{
-
- test_single_block();
-
-}
-
-
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-int config_eim()
-{
- int ok;
-
- // try to setup eim (return value should be 1)
- printf("Configuring EIM .. ");
- ok = eim_setup();
- if (ok < 1) {
- printf("ERROR\n");
- return EXIT_FAILURE;
- }
- else {
- printf("EIM Setup ok.\n");
- }
-
- return EXIT_SUCCESS;
-}
-
-//------------------------------------------------------------------------------
-// main()
-//------------------------------------------------------------------------------
-int main()
-{
- config_eim();
- test_sha256();
-
- return 0;
-}
-
-//======================================================================
-// EOF test-sha256.c
-//======================================================================
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