[Cryptech-Commits] [test/novena_base] 01/01: Adding a bit of test logic to see that the noise board is properly connected.
git at cryptech.is
git at cryptech.is
Fri Feb 6 12:55:17 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository test/novena_base.
commit b251321a08306c0c8954749c13178b869fc54b01
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri Feb 6 13:55:11 2015 +0100
Adding a bit of test logic to see that the noise board is properly connected.
---
rtl/src/verilog/novena_baseline_top.v | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v
index 20bf28d..15e1be4 100644
--- a/rtl/src/verilog/novena_baseline_top.v
+++ b/rtl/src/verilog/novena_baseline_top.v
@@ -164,9 +164,37 @@ module novena_baseline_top
// Cryptech Logic
//
// Logic specific to the Cryptech use of the Novena.
- // Currently we just hard wire the LED outputs.
+ // Currently we just sample the noise and drive the LEDs
+ // with this signal.
//----------------------------------------------------------------
- assign ct_avalanche_led = 8'h55;
+ reg ct_noise_sample0_reg;
+ reg ct_noise_sample1_reg;
+ reg [7 : 0] ct_led_reg;
+
+ always @ (posedge sys_clk)
+ begin
+ if (sys_rst)
+ begin
+ ct_led_reg <= 8'h00;
+ ct_noise_sample0_reg <= 1'b0;
+ ct_noise_sample1_reg <= 1'b0;
+ end
+ else
+ begin
+ ct_noise_sample0_reg <= ct_avalanche_noise;
+ ct_noise_sample1_reg <= ct_noise_sample0_reg;
+ ct_led_reg[0] <= ct_noise_sample1_reg;
+ ct_led_reg[1] <= ct_noise_sample1_reg;
+ ct_led_reg[2] <= ct_noise_sample1_reg;
+ ct_led_reg[3] <= ct_noise_sample1_reg;
+ ct_led_reg[4] <= ct_noise_sample1_reg;
+ ct_led_reg[5] <= ct_noise_sample1_reg;
+ ct_led_reg[6] <= ct_noise_sample1_reg;
+ ct_led_reg[7] <= ct_noise_sample1_reg;
+ end
+ end
+
+ assign ct_avalanche_led = ct_led_reg;
//----------------------------------------------------------------
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