[Cryptech-Commits] [test/novena_base] 01/01: (1) Updated core selector with logic to connect sha256. (2) Adding test sw that is able to talk to the sha256 core and perform a hash operation.
git at cryptech.is
git at cryptech.is
Tue Feb 3 20:45:29 UTC 2015
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joachim at secworks.se pushed a commit to branch sha256_core
in repository test/novena_base.
commit f0ded923cc20dbc39336f3f2e8f083033dba6f9c
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Tue Feb 3 21:45:24 2015 +0100
(1) Updated core selector with logic to connect sha256. (2) Adding test sw that is able to talk to the sha256 core and perform a hash operation.
---
rtl/src/verilog/core_selector.v | 106 +++++++++++++++++++++++++++++++++------
sw/test-sha256/test-sha256.c | 107 ++++++++++++++++++++++++++++++++++++----
2 files changed, 187 insertions(+), 26 deletions(-)
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index a18bfe6..3f74a26 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -48,26 +48,100 @@ module core_selector
input wire [31 : 0] write_data
);
- localparam SHA256_BASE_ADDR = 6'h14;
- wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0;
- wire read_access = sys_eim_rd & access_sha256;
- wire write_access = sys_eim_wr & access_sha256;
- wire select = read_access | write_access;
- assign read_data = (sys_eim_rd) ? 32'hdeadbeef : 32'haa55aa55;
+ //
+ // Parameters
+ //
+ localparam ADDER_BASE_ADDR = 6'h00; // upper 6 bits of address
+ localparam ADDER_OFFSET_X_REG = 8'h00; // X
+ localparam ADDER_OFFSET_Y_REG = 8'h01; // Y
-// sha256 sha256_inst(
-// .clk(sys_clk),
-// .reset_n(~sys_rst),
+
+ /* This flag detects whether adder core is being addressed. */
+ wire eim_access_adder = (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
+
+ /* These flags detect whether write or read access is requested. */
+ wire eim_access_write = sys_eim_wr & eim_access_adder;
+ wire eim_access_read = sys_eim_rd & eim_access_adder;
+ wire select = eim_access_read | eim_access_write;
+
+// reg [31 : 0] read_data_reg;
+// reg [31 : 0] y_reg;
+// reg [31 : 0] x_reg;
+//
+// //
+// // Write Request Handler
+// //
+// always @(posedge sys_clk)
+// //
+// if (sys_rst) begin
+// x_reg <= 32'hdeaddead;
+// y_reg <= 32'hbeefbeef;
+// end
+// else if (eim_access_write) begin
+// case (sys_eim_addr[7:0])
+// ADDER_OFFSET_X_REG: x_reg <= write_data;
+// ADDER_OFFSET_Y_REG: y_reg <= write_data;
+// endcase
+// end
+//
+//
+// //
+// // Read Request Handler
+// always @(posedge sys_clk)
+// //
+// if (sys_rst)
+// read_data_reg <= 32'h00000000;
+// //
+// else if (eim_access_read) begin
+// //
+// case (sys_eim_addr[7:0])
+// ADDER_OFFSET_X_REG: read_data_reg <= x_reg;
+// ADDER_OFFSET_Y_REG: read_data_reg <= y_reg;
+// endcase
+// //
+// end
+
+// assign read_data = read_data_reg;
+
+
+ // localparam SHA256_BASE_ADDR = 6'h14;
+ //
+ // wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0;
+ // wire read_access = sys_eim_rd & access_sha256;
+ // wire write_access = sys_eim_wr & access_sha256;
+ // wire select = read_access | write_access;
+
+// reg [31 : 0] read_data_reg;
+// wire [31 : 0] sha_read_data;
//
-// .cs(select),
-// .we(write_access),
+// assign read_data = read_data_reg;
//
-// .address(sys_eim_addr[7 : 0]),
-// .write_data(write_data),
-// .read_data(read_data),
-// .error()
-// );
+// always @ (posedge sys_clk)
+// begin
+// if (sys_rst)
+// begin
+// read_data_reg <= 32'h00000000;
+// end
+// else
+// begin
+// read_data_reg <= sha_read_data;
+// end
+// end
+
+
+ sha256 sha256_inst(
+ .clk(sys_clk),
+ .reset_n(1'b1),
+
+ .cs(eim_access_adder),
+ .we(sys_eim_wr),
+
+ .address(sys_eim_addr[7 : 0]),
+ .write_data(write_data),
+ .read_data(read_data),
+ .error()
+ );
endmodule
diff --git a/sw/test-sha256/test-sha256.c b/sw/test-sha256/test-sha256.c
index 25845d0..9f7b331 100644
--- a/sw/test-sha256/test-sha256.c
+++ b/sw/test-sha256/test-sha256.c
@@ -19,9 +19,13 @@
//------------------------------------------------------------------------------
// Defines
//------------------------------------------------------------------------------
-#define SHA256_PREFIX (0x14)
+#define SHA256_PREFIX (0x0000)
#define SHA_BASE (EIM_BASE_ADDR + SHA256_PREFIX)
+#define DEMO_ADDER_BASE_ADDR (EIM_BASE_ADDR + 0x0000)
+#define DEMO_ADDER_X_REG (DEMO_ADDER_BASE_ADDR + 0)
+#define DEMO_ADDER_Y_REG (DEMO_ADDER_BASE_ADDR + 4)
+
//------------------------------------------------------------------------------
// Testing Parameters
@@ -29,16 +33,104 @@
//------------------------------------------------------------------------------
-// main()
//------------------------------------------------------------------------------
-int main()
+void test_regs()
{
unsigned int read_addr;
unsigned int read_data;
+ unsigned int write_addr;
+ unsigned int write_data;
+ unsigned int i;
+
+//
+// for (i = 0 ; i < 0x40000 ; i += 4) {
+// read_addr = EIM_BASE_ADDR + i;
+// eim_read_32(read_addr, &read_data);
+// printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+// }
+
+ read_addr = DEMO_ADDER_X_REG;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+
+ read_addr = DEMO_ADDER_Y_REG;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+
+ write_addr = DEMO_ADDER_Y_REG;
+ write_data = 0xaa55aa55;
+ eim_write_32(write_addr, &write_data);
+
+ read_addr = DEMO_ADDER_Y_REG;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+}
+
+
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+void test_sha256()
+{
+ unsigned int write_addr;
+ unsigned int write_data;
+ unsigned int read_addr;
+ unsigned int read_data;
+ int ok;
+ unsigned int i;
+
+ // Dump register contents. See if we have the core.
+ for (i = 0 ; i < 200 ; i += 4) {
+ read_addr = SHA_BASE + i;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+ }
+
+ // Try to iniate block processing and then dump
+ write_addr = SHA_BASE + 0x20;
+ write_data = 0x00000001;
+ eim_write_32(write_addr, &write_data);
+
+ // Dump register contents. See if we have the core.
+ for (i = 0 ; i < 200 ; i += 4) {
+ read_addr = SHA_BASE + i;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+ }
+
+ // Dump register contents. See if we have the core.
+ for (i = 0 ; i < 200 ; i += 4) {
+ read_addr = SHA_BASE + i;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+ }
+
+ // Dump register contents. See if we have the core.
+ for (i = 0 ; i < 200 ; i += 4) {
+ read_addr = SHA_BASE + i;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+ }
+
+ // Dump register contents. See if we have the core.
+ for (i = 0 ; i < 200 ; i += 4) {
+ read_addr = SHA_BASE + i;
+ eim_read_32(read_addr, &read_data);
+ printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
+ }
+
+}
+
+//------------------------------------------------------------------------------
+// main()
+//------------------------------------------------------------------------------
+int main()
+{
+ int ok;
+ unsigned int i;
// try to setup eim (return value should be 1)
printf("Configuring EIM .. ");
- int ok = eim_setup();
+ ok = eim_setup();
if (ok < 1) {
printf("ERROR\n");
return EXIT_FAILURE;
@@ -47,12 +139,7 @@ int main()
printf("EIM Setup ok.\n");
}
- // Dump register contents. See if we have the core.
- for (unsigned int i = 0 ; i < 100 ; i += 3) {
- read_addr = SHA_BASE + i;
- eim_read_32(read_addr, &read_data);
- printf("address 0x%08x = 0x%08x\n", read_addr, read_data);
- }
+ test_sha256();
return 0;
}
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