[Cryptech-Commits] [test/novena_base] 01/02: Removed trailing whitespace and DOS ^M.

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Sun Feb 1 08:03:45 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository test/novena_base.

commit 0d258b832847ca29bcf47f1904b7cc4a76e2a191
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sun Feb 1 08:54:53 2015 +0100

    Removed trailing whitespace and DOS ^M.
---
 rtl/src/ucf/novena_baseline.ucf | 176 ++++++++++++++++++++--------------------
 1 file changed, 88 insertions(+), 88 deletions(-)

diff --git a/rtl/src/ucf/novena_baseline.ucf b/rtl/src/ucf/novena_baseline.ucf
index 6638d7b..ec2f17d 100644
--- a/rtl/src/ucf/novena_baseline.ucf
+++ b/rtl/src/ucf/novena_baseline.ucf
@@ -1,98 +1,98 @@
-#-------------------------------------------------------------------------------
-# FPGA Config
-#-------------------------------------------------------------------------------
-CONFIG  VCCAUX = 3.3 ;
-#-------------------------------------------------------------------------------
-
-
+#-------------------------------------------------------------------------------
+# FPGA Config
+#-------------------------------------------------------------------------------
+CONFIG  VCCAUX = 3.3 ;
+#-------------------------------------------------------------------------------
+
+
 #--------------------------------------------------------------------------------
 # GCLK Timing
 #--------------------------------------------------------------------------------
 NET  "gclk_p_pin" TNM_NET = TNM_gclk ;
-TIMESPEC  TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50% ;
-
-
-#-------------------------------------------------------------------------------
-# BCLK Timing
-#-------------------------------------------------------------------------------
+TIMESPEC  TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50% ;
+
+
+#-------------------------------------------------------------------------------
+# BCLK Timing
+#-------------------------------------------------------------------------------
 NET  "eim_bclk" TNM_NET = TNM_bclk ;
-TIMESPEC  TS_bclk = PERIOD TNM_bclk 30 ns HIGH 50% ;
-
-
-#-------------------------------------------------------------------------------
-# FPGA Pinout
-#-------------------------------------------------------------------------------
-NET  "led_pin"         LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
-NET  "apoptosis_pin"   LOC = "K1"  | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
-NET  "reset_mcu_b_pin" LOC = "F1"  | IOSTANDARD = "LVCMOS33" | PULLUP ;
-
+TIMESPEC  TS_bclk = PERIOD TNM_bclk 30 ns HIGH 50% ;
+
+
+#-------------------------------------------------------------------------------
+# FPGA Pinout
+#-------------------------------------------------------------------------------
+NET  "led_pin"         LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
+NET  "apoptosis_pin"   LOC = "K1"  | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 12 ;
+NET  "reset_mcu_b_pin" LOC = "F1"  | IOSTANDARD = "LVCMOS33" | PULLUP ;
+
 NET  "gclk_p_pin"      LOC = "H2"  | IOSTANDARD = "LVDS_33"  | DIFF_TERM = "TRUE" ;
-NET  "gclk_n_pin"      LOC = "H1"  | IOSTANDARD = "LVDS_33"  | DIFF_TERM = "TRUE" ;
-
-NET  "eim_bclk"        LOC = "C9"  | IOSTANDARD = "LVCMOS33" ;
-NET  "eim_cs0_n"       LOC = "B11" | IOSTANDARD = "LVCMOS33" ;
-
-NET  "eim_da<0>"       LOC = "G9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<1>"       LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<2>"       LOC = "F9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<3>"       LOC = "B9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<4>"       LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<5>"       LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<6>"       LOC = "A9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<7>"       LOC = "A8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<8>"       LOC = "B8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<9>"       LOC = "D8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<10>"      LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<11>"      LOC = "C8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<12>"      LOC = "C7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<13>"      LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<14>"      LOC = "C4"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-NET  "eim_da<15>"      LOC = "B6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-
-NET  "eim_lba_n"       LOC = "B14" | IOSTANDARD = "LVCMOS33" ;
-NET  "eim_wr_n"        LOC = "C14" | IOSTANDARD = "LVCMOS33" ;
-NET  "eim_oe_n"        LOC = "C10" | IOSTANDARD = "LVCMOS33" ;
-NET  "eim_wait_n"      LOC = "A7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
-
-
-#-------------------------------------------------------------------------------
-# EIM Input Timing
-#-------------------------------------------------------------------------------
+NET  "gclk_n_pin"      LOC = "H1"  | IOSTANDARD = "LVDS_33"  | DIFF_TERM = "TRUE" ;
+
+NET  "eim_bclk"        LOC = "C9"  | IOSTANDARD = "LVCMOS33" ;
+NET  "eim_cs0_n"       LOC = "B11" | IOSTANDARD = "LVCMOS33" ;
+
+NET  "eim_da<0>"       LOC = "G9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<1>"       LOC = "A10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<2>"       LOC = "F9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<3>"       LOC = "B9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<4>"       LOC = "E13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<5>"       LOC = "F13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<6>"       LOC = "A9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<7>"       LOC = "A8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<8>"       LOC = "B8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<9>"       LOC = "D8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<10>"      LOC = "D11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<11>"      LOC = "C8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<12>"      LOC = "C7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<13>"      LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<14>"      LOC = "C4"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+NET  "eim_da<15>"      LOC = "B6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+
+NET  "eim_lba_n"       LOC = "B14" | IOSTANDARD = "LVCMOS33" ;
+NET  "eim_wr_n"        LOC = "C14" | IOSTANDARD = "LVCMOS33" ;
+NET  "eim_oe_n"        LOC = "C10" | IOSTANDARD = "LVCMOS33" ;
+NET  "eim_wait_n"      LOC = "A7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+
+
+#-------------------------------------------------------------------------------
+# EIM Input Timing
+#-------------------------------------------------------------------------------
 NET  "eim_cs0_n" TNM = "TNM_EIM_IN" ;
-NET  "eim_da<*>" TNM = "TNM_EIM_IN" ;
-NET  "eim_lba_n" TNM = "TNM_EIM_IN" ;
-NET  "eim_wr_n"  TNM = "TNM_EIM_IN" ;
-NET  "eim_oe_n"  TNM = "TNM_EIM_IN" ;
-
-TIMEGRP  "TNM_EIM_IN" OFFSET = IN 9.75 ns VALID 16.0 ns BEFORE "eim_bclk" RISING  ;
-
-
-#-------------------------------------------------------------------------------
-# EIM Output Timing
+NET  "eim_da<*>" TNM = "TNM_EIM_IN" ;
+NET  "eim_lba_n" TNM = "TNM_EIM_IN" ;
+NET  "eim_wr_n"  TNM = "TNM_EIM_IN" ;
+NET  "eim_oe_n"  TNM = "TNM_EIM_IN" ;
+
+TIMEGRP  "TNM_EIM_IN" OFFSET = IN 9.75 ns VALID 16.0 ns BEFORE "eim_bclk" RISING  ;
+
+
+#-------------------------------------------------------------------------------
+# EIM Output Timing
+#-------------------------------------------------------------------------------
+NET  "eim_da<*>"  TNM = "TNM_EIM_OUT" ;
+NET  "eim_wait_n" TNM = "TNM_EIM_OUT" ;
+
+TIMEGRP  "TNM_EIM_OUT" OFFSET = OUT 13.0 ns AFTER "eim_bclk" FALLING ;
+
+
+#-------------------------------------------------------------------------------
+# CDC Paths
 #-------------------------------------------------------------------------------
-NET  "eim_da<*>"  TNM = "TNM_EIM_OUT" ;
-NET  "eim_wait_n" TNM = "TNM_EIM_OUT" ;
-
-TIMEGRP  "TNM_EIM_OUT" OFFSET = OUT 13.0 ns AFTER "eim_bclk" FALLING ;
-
-
-#-------------------------------------------------------------------------------
-# CDC Paths
-#-------------------------------------------------------------------------------
-INST  "eim/eim_cdc/cdc_eim_sys/src_ff"     TNM = "TNM_from_bclk"    ;
-INST  "eim/eim_cdc/cdc_eim_sys/src_latch*" TNM = "TNM_from_bclk"    ;
+INST  "eim/eim_cdc/cdc_eim_sys/src_ff"     TNM = "TNM_from_bclk"    ;
+INST  "eim/eim_cdc/cdc_eim_sys/src_latch*" TNM = "TNM_from_bclk"    ;
 INST  "eim/eim_cdc/cdc_eim_sys/ff_sync*"   TNM = "TNM_to_sys_clk"   ;
-INST  "eim/eim_cdc/cdc_eim_sys/dst_latch*" TNM = "TNM_to_sys_clk"   ;
-
-INST  "eim/eim_cdc/cdc_sys_eim/src_ff"     TNM = "TNM_from_sys_clk" ;
-INST  "eim/eim_cdc/cdc_sys_eim/src_latch*" TNM = "TNM_from_sys_clk" ;
+INST  "eim/eim_cdc/cdc_eim_sys/dst_latch*" TNM = "TNM_to_sys_clk"   ;
+
+INST  "eim/eim_cdc/cdc_sys_eim/src_ff"     TNM = "TNM_from_sys_clk" ;
+INST  "eim/eim_cdc/cdc_sys_eim/src_latch*" TNM = "TNM_from_sys_clk" ;
 INST  "eim/eim_cdc/cdc_sys_eim/ff_sync*"   TNM = "TNM_to_bclk"      ;
-INST  "eim/eim_cdc/cdc_sys_eim/dst_latch*" TNM = "TNM_to_bclk"      ;
-
-TIMESPEC  "TS_bclk_2_sys_clk" = FROM "TNM_from_bclk"    TO "TNM_to_sys_clk" TIG ;
-TIMESPEC  "TS_sys_clk_2_bclk" = FROM "TNM_from_sys_clk" TO "TNM_to_bclk"    TIG ;
-
-
-#-------------------------------------------------------------------------------
-# End-of-File
-#-------------------------------------------------------------------------------
+INST  "eim/eim_cdc/cdc_sys_eim/dst_latch*" TNM = "TNM_to_bclk"      ;
+
+TIMESPEC  "TS_bclk_2_sys_clk" = FROM "TNM_from_bclk"    TO "TNM_to_sys_clk" TIG ;
+TIMESPEC  "TS_sys_clk_2_bclk" = FROM "TNM_from_sys_clk" TO "TNM_to_bclk"    TIG ;
+
+
+#-------------------------------------------------------------------------------
+# End-of-File
+#-------------------------------------------------------------------------------
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