[Cryptech-Commits] [hardware] branch master updated: connect first SDRAM, add USB MGMT UART.

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fredrik at thulin.net pushed a commit to branch master
in repository hardware.

The following commit(s) were added to refs/heads/master by this push:
       new  0b3b03d   connect first SDRAM, add USB MGMT UART.
0b3b03d is described below

commit 0b3b03d2948ca52a12032143a914c95a3b69ad91
Author: Fredrik Thulin <fredrik at thulin.net>
Date:   Wed Dec 16 21:58:33 2015 +0100

    connect first SDRAM, add USB MGMT UART.
---
 eagle/alpha/rev02/rev02.brd | 1604 +++++++++++++++++++++++++++----------------
 eagle/alpha/rev02/rev02.pdf |  Bin 612741 -> 662185 bytes
 eagle/alpha/rev02/rev02.sch | 1462 +++++++++++++++++++++++++++++++++++----
 eagle/lbr/Alpha-IC.lbr      |   10 +-
 4 files changed, 2354 insertions(+), 722 deletions(-)

diff --git a/eagle/alpha/rev02/rev02.brd b/eagle/alpha/rev02/rev02.brd
index f137e64..7a32981 100644
--- a/eagle/alpha/rev02/rev02.brd
+++ b/eagle/alpha/rev02/rev02.brd
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@@ -6379,10 +6379,10 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
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@@ -6489,65 +6489,65 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
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 </element>
 <element name="C168" library="resistor" package="C1210" value="47 uF" x="10.668" y="93.8784">
 <attribute name="RATED_VOLTAGE" value="16V" x="-177.0888" y="-717.1944" size="1.778" layer="27" display="off"/>
@@ -6559,25 +6559,25 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
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 <attribute name="TOLERANCE" value="20%" x="-189.6872" y="-765.556" size="1.778" layer="27" display="off"/>
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+<attribute name="RATED_VOLTAGE" value="16V" x="-138.7348" y="-730.8088" size="1.778" layer="27" display="off"/>
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 </element>
 <element name="C174" library="resistor" package="C1210" value="47 uF" x="156.464" y="58.928">
 <attribute name="RATED_VOLTAGE" value="16V" x="18.9992" y="-788.7208" size="1.778" layer="27" display="off"/>
@@ -6654,23 +6654,147 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
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 <attribute name="RATED_VOLTAGE" value="10V" x="53.086" y="1.524" size="1.778" layer="27" display="off"/>
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 <element name="IC1" library="Alpha-IC" package="TSOP2-86L" value="IS45S32160F" x="-7.112" y="13.462"/>
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+<attribute name="RATED_VOLTAGE" value="10V" x="-12.192" y="-51.816" size="1.778" layer="27" display="off"/>
+</element>
+<element name="C201" library="resistor" package="C0402" value="0.1 uF" x="3.556" y="-3.556">
+<attribute name="DIELECTRIC" value="X7R" x="-12.192" y="-56.642" size="1.778" layer="27" display="off"/>
+<attribute name="RATED_VOLTAGE" value="10V" x="-12.192" y="-56.642" size="1.778" layer="27" display="off"/>
+</element>
+<element name="C206" library="resistor" package="C0402" value="0.1uF" x="-5.588" y="-27.686">
+<attribute name="DIELECTRIC" value="X7R" x="-12.192" y="-80.772" size="1.778" layer="27" display="off"/>
+<attribute name="RATED_VOLTAGE" value="10V" x="-12.192" y="-80.772" size="1.778" layer="27" display="off"/>
+</element>
+<element name="C207" library="resistor" package="C0402" value="0.1uF" x="1.016" y="-27.686">
+<attribute name="DIELECTRIC" value="X7R" x="-12.192" y="-85.598" size="1.778" layer="27" display="off"/>
+<attribute name="RATED_VOLTAGE" value="10V" x="-12.192" y="-85.598" size="1.778" layer="27" display="off"/>
+</element>
+<element name="C208" library="resistor" package="C0402" value="0.1uF" x="-12.192" y="-32.512">
+<attribute name="DIELECTRIC" value="X7R" x="-12.192" y="-90.424" size="1.778" layer="27" display="off"/>
+<attribute name="RATED_VOLTAGE" value="10V" x="-12.192" y="-90.424" size="1.778" layer="27" display="off"/>
+</element>
 </elements>
 <signals>
 <signal name="GND" class="1">
@@ -7326,6 +7450,58 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <contactref element="U1" pad="7"/>
 <contactref element="R32" pad="1"/>
 <contactref element="C8" pad="2"/>
+<contactref element="U$10" pad="10"/>
+<contactref element="U$10" pad="11"/>
+<contactref element="U$10" pad="22"/>
+<contactref element="U$10" pad="23"/>
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+<contactref element="U$10" pad="36"/>
+<contactref element="U$10" pad="47"/>
+<contactref element="U$10" pad="48"/>
+<contactref element="CN2" pad="GND"/>
+<contactref element="C9" pad="2"/>
+<contactref element="C10" pad="2"/>
+<contactref element="R70" pad="2"/>
+<contactref element="U$10" pad="4"/>
+<contactref element="U$10" pad="9"/>
+<contactref element="U$10" pad="41"/>
+<contactref element="U$10" pad="42"/>
+<contactref element="C12" pad="1"/>
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+<contactref element="IC1" pad="86"/>
+<contactref element="IC1" pad="6"/>
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+<contactref element="IC1" pad="38"/>
+<contactref element="IC1" pad="46"/>
+<contactref element="IC1" pad="52"/>
+<contactref element="IC1" pad="78"/>
+<contactref element="IC1" pad="84"/>
+<contactref element="IC1" pad="44"/>
+<contactref element="IC1" pad="58"/>
+<contactref element="IC1" pad="72"/>
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@@ -7354,86 +7530,149 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
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+<wire x1="144.4752" y1="18.6944" x2="144.4752" y2="28.1944" width="0" layer="19" extent="1-1"/>
+<wire x1="143.2052" y1="18.6944" x2="144.4752" y2="18.6944" width="0" layer="19" extent="1-1"/>
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+<wire x1="144.656" y1="10.16" x2="144.656" y2="13.208" width="0" layer="19" extent="1-1"/>
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+<wire x1="137.326" y1="13.208" x2="134.732" y2="10.164" width="0" layer="19" extent="1-1"/>
 <wire x1="9.693" y1="18.826" x2="23.7998" y2="11.6078" width="0" layer="19" extent="1-1"/>
 <wire x1="7.874" y1="17.922" x2="9.693" y2="18.826" width="0" layer="19" extent="1-1"/>
 <wire x1="5.588" y1="17.36" x2="7.874" y2="17.922" width="0" layer="19" extent="1-1"/>
 <wire x1="9.002" y1="25.146" x2="9.693" y2="18.826" width="0" layer="19" extent="1-1"/>
 <wire x1="6.03" y1="25.316" x2="9.002" y2="25.146" width="0" layer="19" extent="1-1"/>
 <wire x1="13.374" y1="26.416" x2="9.002" y2="25.146" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="16.962" x2="5.588" y2="17.36" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="19.962" x2="-1.182" y2="16.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="22.962" x2="-1.182" y2="19.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="23.962" x2="-1.182" y2="22.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="9.962" x2="-1.182" y2="16.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="6.962" x2="-1.182" y2="9.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="3.962" x2="-1.182" y2="6.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="2.962" x2="-1.182" y2="3.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-3.668" y1="-3.556" x2="-1.182" y2="2.962" width="0" layer="19" extent="1-1"/>
+<wire x1="-11.542" y1="-3.556" x2="-3.668" y2="-3.556" width="0" layer="19" extent="1-1"/>
+<wire x1="4.206" y1="-3.556" x2="-3.668" y2="-3.556" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="5.462" x2="-11.542" y2="-3.556" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="8.462" x2="-13.042" y2="5.462" width="0" layer="19" extent="1-1"/>
+<wire x1="-4.938" y1="-13.208" x2="-3.668" y2="-3.556" width="0" layer="19" extent="1-1"/>
+<wire x1="-4.938" y1="-18.034" x2="-4.938" y2="-13.208" width="0" layer="19" extent="1-1"/>
+<wire x1="-11.542" y1="-18.034" x2="-4.938" y2="-18.034" width="0" layer="19" extent="1-1"/>
+<wire x1="1.666" y1="-18.034" x2="-4.938" y2="-18.034" width="0" layer="19" extent="1-1"/>
+<wire x1="1.666" y1="-13.208" x2="1.666" y2="-18.034" width="0" layer="19" extent="1-1"/>
+<wire x1="-4.938" y1="-27.686" x2="-4.938" y2="-18.034" width="0" layer="19" extent="1-1"/>
+<wire x1="1.666" y1="-27.686" x2="-4.938" y2="-27.686" width="0" layer="19" extent="1-1"/>
+<wire x1="-11.542" y1="-32.512" x2="-4.938" y2="-27.686" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="18.462" x2="-13.042" y2="8.462" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="21.462" x2="-13.042" y2="18.462" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="AMPLIFIED">
 <contactref element="U2" pad="2"/>
@@ -8029,7 +8257,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="86.0016" y1="67.592" x2="83.2584" y2="67.592" width="0.3048" layer="1"/>
 <wire x1="83.2584" y1="67.592" x2="81.4296" y2="69.4208" width="0.3048" layer="1"/>
 <contactref element="U7" pad="Y14"/>
+<contactref element="IC1" pad="69"/>
 <wire x1="41.0808" y1="55.2088" x2="81.4296" y2="69.4208" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="15.462" x2="41.0808" y2="55.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A13" class="3">
 <contactref element="U$1" pad="130"/>
@@ -8047,7 +8277,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="85.392" y1="66.3728" x2="80.82" y2="66.3728" width="0.3048" layer="1"/>
 <wire x1="80.82" y1="66.3728" x2="77.772" y2="69.4208" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AB12"/>
+<contactref element="IC1" pad="22"/>
 <wire x1="39.0808" y1="57.2088" x2="77.772" y2="69.4208" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="13.462" x2="39.0808" y2="57.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A16" class="3">
 <contactref element="U$1" pad="111"/>
@@ -8145,22 +8377,14 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="43.0808" y1="59.2088" x2="65.532" y2="35.9408" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A20">
-<contactref element="U$1" pad="3"/>
-<wire x1="78.3086" y1="31.138" x2="78.3086" y2="29.419" width="0.3048" layer="1"/>
-<wire x1="78.3086" y1="29.419" x2="77.772" y2="28.8824" width="0.3048" layer="1"/>
-<wire x1="77.772" y1="28.8824" x2="71.676" y2="28.8824" width="0.3048" layer="1"/>
-<wire x1="65.2272" y1="35.3312" x2="71.676" y2="28.8824" width="0.3048" layer="1"/>
 <contactref element="U7" pad="W10"/>
-<wire x1="65.2272" y1="35.3312" x2="42.0808" y2="59.2088" width="0" layer="19" extent="1-1"/>
+<contactref element="U$1" pad="3"/>
+<wire x1="42.0808" y1="59.2088" x2="78.3086" y2="31.138" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A21">
-<contactref element="U$1" pad="4"/>
-<wire x1="78.8166" y1="31.138" x2="78.8166" y2="29.0126" width="0.3048" layer="1"/>
-<wire x1="78.8166" y1="29.0126" x2="78.0768" y2="28.2728" width="0.3048" layer="1"/>
-<wire x1="78.0768" y1="28.2728" x2="71.346" y2="28.2728" width="0.3048" layer="1"/>
-<wire x1="64.77" y1="34.8488" x2="71.346" y2="28.2728" width="0.3048" layer="1"/>
 <contactref element="U7" pad="Y11"/>
-<wire x1="41.0808" y1="58.2088" x2="64.77" y2="34.8488" width="0" layer="19" extent="1-1"/>
+<contactref element="U$1" pad="4"/>
+<wire x1="41.0808" y1="58.2088" x2="78.8166" y2="31.138" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D30" class="2">
 <contactref element="U$1" pad="11"/>
@@ -8191,7 +8415,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="83.5632" y1="26.444" x2="70.4088" y2="26.444" width="0.3048" layer="1"/>
 <wire x1="70.4088" y1="26.444" x2="63.246" y2="33.6068" width="0.3048" layer="1"/>
 <contactref element="U7" pad="Y17"/>
+<contactref element="IC1" pad="25"/>
 <wire x1="41.0808" y1="52.2088" x2="63.246" y2="33.6068" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="11.962" x2="41.0808" y2="52.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A1" class="3">
 <contactref element="U$1" pad="17"/>
@@ -8200,7 +8426,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="83.868" y1="25.8344" x2="70.104" y2="25.8344" width="0.3048" layer="1"/>
 <wire x1="70.104" y1="25.8344" x2="62.7888" y2="33.1496" width="0.3048" layer="1"/>
 <contactref element="U7" pad="Y16"/>
+<contactref element="IC1" pad="26"/>
 <wire x1="41.0808" y1="53.2088" x2="62.7888" y2="33.1496" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="11.462" x2="41.0808" y2="53.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A2" class="3">
 <contactref element="U$1" pad="18"/>
@@ -8209,7 +8437,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="84.1728" y1="25.2248" x2="69.8472" y2="25.2248" width="0.3048" layer="1"/>
 <wire x1="69.8472" y1="25.2248" x2="62.3796" y2="32.6924" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA16"/>
+<contactref element="IC1" pad="27"/>
 <wire x1="40.0808" y1="53.2088" x2="62.3796" y2="32.6924" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="10.962" x2="40.0808" y2="53.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A3" class="3">
 <contactref element="U$1" pad="22"/>
@@ -8218,7 +8448,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="86.6112" y1="24.6152" x2="69.5424" y2="24.6152" width="0.3048" layer="1"/>
 <wire x1="69.5424" y1="24.6152" x2="61.9224" y2="32.2352" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AB16"/>
+<contactref element="IC1" pad="60"/>
 <wire x1="39.0808" y1="53.2088" x2="61.9224" y2="32.2352" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="10.962" x2="39.0808" y2="53.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A4" class="3">
 <contactref element="U$1" pad="23"/>
@@ -8227,7 +8459,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="86.916" y1="24.0056" x2="69.2376" y2="24.0056" width="0.3048" layer="1"/>
 <wire x1="69.2376" y1="24.0056" x2="61.6176" y2="31.6256" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AB17"/>
+<contactref element="IC1" pad="61"/>
 <wire x1="39.0808" y1="52.2088" x2="61.6176" y2="31.6256" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="11.462" x2="39.0808" y2="52.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A5" class="3">
 <contactref element="U$1" pad="24"/>
@@ -8236,7 +8470,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="87.2208" y1="23.396" x2="68.9328" y2="23.396" width="0.3048" layer="1"/>
 <wire x1="68.9328" y1="23.396" x2="61.3128" y2="31.016" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA13"/>
+<contactref element="IC1" pad="62"/>
 <wire x1="61.3128" y1="31.016" x2="40.0808" y2="56.2088" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="11.962" x2="40.0808" y2="56.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A6" class="3">
 <contactref element="U$1" pad="71"/>
@@ -8246,7 +8482,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <via x="94.536" y="38.9408" extent="1-16" drill="0.6" shape="square"/>
 <wire x1="93.9648" y1="38.5976" x2="94.536" y2="38.9408" width="0.3048" layer="16"/>
 <contactref element="U7" pad="AB13"/>
+<contactref element="IC1" pad="63"/>
 <wire x1="39.0808" y1="56.2088" x2="93.9648" y2="38.5976" width="0" layer="19" extent="1-16"/>
+<wire x1="-1.182" y1="12.462" x2="39.0808" y2="56.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A7" class="3">
 <contactref element="U$1" pad="74"/>
@@ -8256,7 +8494,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <via x="92.7072" y="40.16" extent="1-16" drill="0.6" shape="square"/>
 <wire x1="91.6448" y1="39.0976" x2="92.7072" y2="40.16" width="0.3048" layer="16"/>
 <contactref element="U7" pad="AA15"/>
+<contactref element="IC1" pad="64"/>
 <wire x1="40.0808" y1="54.2088" x2="91.6448" y2="39.0976" width="0" layer="19" extent="1-16"/>
+<wire x1="-1.182" y1="12.962" x2="40.0808" y2="54.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A8" class="3">
 <contactref element="U$1" pad="75"/>
@@ -8267,7 +8507,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="100.0224" y1="41.3792" x2="92.0976" y2="41.3792" width="0.3048" layer="1"/>
 <wire x1="92.0976" y1="41.3792" x2="91.1832" y2="40.4648" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AB15"/>
+<contactref element="IC1" pad="65"/>
 <wire x1="39.0808" y1="54.2088" x2="90.316" y2="39.5976" width="0" layer="19" extent="1-16"/>
+<wire x1="-1.182" y1="13.462" x2="39.0808" y2="54.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A9" class="3">
 <contactref element="U$1" pad="76"/>
@@ -8280,7 +8522,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="99.7176" y1="41.9888" x2="89.6592" y2="41.9888" width="0.3048" layer="1"/>
 <wire x1="89.6592" y1="41.9888" x2="89.3544" y2="41.684" width="0.3048" layer="1"/>
 <contactref element="U7" pad="Y13"/>
+<contactref element="IC1" pad="66"/>
 <wire x1="41.0808" y1="56.2088" x2="88.6344" y2="40.0976" width="0" layer="19" extent="1-16"/>
+<wire x1="-1.182" y1="13.962" x2="41.0808" y2="56.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A10" class="3">
 <contactref element="U$1" pad="77"/>
@@ -8293,7 +8537,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="88.392" y1="42.9032" x2="86.5632" y2="41.0744" width="0.3048" layer="1"/>
 <wire x1="86.5632" y1="41.0744" x2="85.392" y2="41.0744" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA14"/>
+<contactref element="IC1" pad="24"/>
 <wire x1="40.0808" y1="55.2088" x2="85.0872" y2="41.3792" width="0" layer="19" extent="1-16"/>
+<wire x1="-13.042" y1="12.462" x2="40.0808" y2="55.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A11" class="3">
 <contactref element="U$1" pad="78"/>
@@ -8306,7 +8552,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="88.0872" y1="43.5128" x2="86.868" y2="42.2936" width="0.3048" layer="1"/>
 <wire x1="86.868" y1="42.2936" x2="83.5632" y2="42.2936" width="0.3048" layer="1"/>
 <contactref element="U7" pad="W14"/>
+<contactref element="IC1" pad="21"/>
 <wire x1="42.0808" y1="55.2088" x2="81.648" y2="41.5976" width="0" layer="19" extent="1-16"/>
+<wire x1="-13.042" y1="13.962" x2="42.0808" y2="55.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D4" class="2">
 <contactref element="U$1" pad="79"/>
@@ -8343,7 +8591,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="93.2336" y1="54.0976" x2="93.9264" y2="54.7904" width="0.3048" layer="16"/>
 <wire x1="96.1058" y1="56.9698" x2="93.9264" y2="54.7904" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA5"/>
+<contactref element="IC1" pad="36"/>
 <wire x1="40.0808" y1="64.2088" x2="93.2336" y2="54.0976" width="0" layer="19" extent="1-16"/>
+<wire x1="-13.042" y1="6.462" x2="40.0808" y2="64.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D18" class="2">
 <contactref element="U$1" pad="100"/>
@@ -8354,10 +8604,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="95.2272" y1="54.1808" x2="97.5082" y2="56.4618" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA3"/>
 <contactref element="IC1" pad="34"/>
-<contactref element="IC1" pad="36"/>
 <wire x1="40.0808" y1="66.2088" x2="94.5624" y2="53.5976" width="0" layer="19" extent="1-16"/>
 <wire x1="-13.042" y1="7.462" x2="40.0808" y2="66.2088" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="6.462" x2="-13.042" y2="7.462" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D17" class="2">
 <contactref element="U$1" pad="99"/>
@@ -8419,9 +8667,11 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="86.657" y1="49.9594" x2="85.6968" y2="48.9992" width="0.3048" layer="1"/>
 <wire x1="85.2952" y1="48.5976" x2="85.6968" y2="48.9992" width="0.3048" layer="16"/>
 <contactref element="U7" pad="Y1"/>
+<contactref element="IC1" pad="76"/>
 <contactref element="IC1" pad="77"/>
 <wire x1="41.0808" y1="68.2088" x2="85.2952" y2="48.5976" width="0" layer="19" extent="1-16"/>
 <wire x1="-1.182" y1="19.462" x2="41.0808" y2="68.2088" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="18.962" x2="-1.182" y2="19.462" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D9" class="2">
 <contactref element="U$1" pad="86"/>
@@ -8431,9 +8681,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="88.6128" y1="49.4768" x2="87.5256" y2="48.3896" width="0.3048" layer="1"/>
 <wire x1="86.7336" y1="47.5976" x2="87.5256" y2="48.3896" width="0.3048" layer="16"/>
 <contactref element="U7" pad="W1"/>
-<contactref element="IC1" pad="76"/>
 <wire x1="42.0808" y1="68.2088" x2="86.7336" y2="47.5976" width="0" layer="19" extent="1-16"/>
-<wire x1="-1.182" y1="18.962" x2="42.0808" y2="68.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D8" class="2">
 <contactref element="U$1" pad="85"/>
@@ -8498,7 +8746,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="85.0872" y1="65.7632" x2="79.9056" y2="65.7632" width="0.3048" layer="1"/>
 <wire x1="79.9056" y1="65.7632" x2="78.3816" y2="67.2872" width="0.3048" layer="1"/>
 <contactref element="U7" pad="AA9"/>
+<contactref element="IC1" pad="23"/>
 <wire x1="40.0808" y1="60.2088" x2="78.3816" y2="67.2872" width="0" layer="19" extent="1-1"/>
+<wire x1="-13.042" y1="12.962" x2="40.0808" y2="60.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_D2" class="2">
 <contactref element="U$1" pad="164"/>
@@ -8804,6 +9054,12 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="95.9868" y1="9.1032" x2="95.7868" y2="6.6648" width="0.6096" layer="1"/>
 <wire x1="95.8596" y1="4.3688" x2="95.9868" y2="4.4608" width="0.6096" layer="1"/>
 <wire x1="95.9868" y1="4.4608" x2="95.7868" y2="6.6648" width="0.6096" layer="1"/>
+<contactref element="C183" pad="1"/>
+<contactref element="C184" pad="1"/>
+<contactref element="FB4" pad="2"/>
+<wire x1="116.19" y1="91.694" x2="123.256" y2="99.06" width="0" layer="19" extent="1-1"/>
+<wire x1="115.062" y1="89.408" x2="116.19" y2="91.694" width="0" layer="19" extent="1-1"/>
+<wire x1="107.5156" y1="14.7148" x2="115.062" y2="89.408" width="0" layer="19" extent="1-1"/>
 <wire x1="96.0868" y1="9.1032" x2="96.784" y2="9.1032" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FT_VPLL">
@@ -9144,8 +9400,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="84.7344" y1="3.7846" x2="85.5472" y2="2.9718" width="0.4064" layer="1"/>
 <contactref element="U1" pad="16"/>
 <contactref element="C8" pad="1"/>
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-<wire x1="68.9102" y1="17.145" x2="100.442" y2="83.566" width="0" layer="19" extent="1-1"/>
+<wire x1="84.694" y1="84.582" x2="93.6498" y2="91.821" width="0" layer="19" extent="1-1"/>
+<wire x1="68.9102" y1="17.145" x2="84.694" y2="84.582" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="AVR_GPIO_11">
 <contactref element="U3" pad="22"/>
@@ -9207,7 +9463,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="89.0016" y1="10.7696" x2="87.4268" y2="10.7696" width="0.3048" layer="1"/>
 <wire x1="87.4268" y1="10.7696" x2="87.4014" y2="10.795" width="0.3048" layer="1"/>
 <contactref element="R6" pad="2"/>
-<wire x1="100.3304" y1="31.138" x2="102.504" y2="88.392" width="0" layer="19" extent="1-1"/>
+<wire x1="100.3304" y1="31.138" x2="86.756" y2="89.408" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="RTC_SCL">
 <contactref element="U6" pad="6"/>
@@ -9221,7 +9477,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="89.0016" y1="9.5504" x2="87.4268" y2="9.5504" width="0.3048" layer="1"/>
 <wire x1="87.4268" y1="9.5504" x2="87.4014" y2="9.525" width="0.3048" layer="1"/>
 <contactref element="R30" pad="2"/>
-<wire x1="100.813" y1="31.138" x2="101.996" y2="87.122" width="0" layer="19" extent="1-1"/>
+<wire x1="100.813" y1="31.138" x2="86.248" y2="88.138" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="RTC_SDA">
 <contactref element="U6" pad="5"/>
@@ -9235,7 +9491,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="89.0016" y1="8.3312" x2="87.4776" y2="8.3312" width="0.3048" layer="1"/>
 <wire x1="87.4776" y1="8.3312" x2="87.4014" y2="8.255" width="0.3048" layer="1"/>
 <contactref element="R31" pad="2"/>
-<wire x1="101.321" y1="31.138" x2="101.742" y2="85.344" width="0" layer="19" extent="1-1"/>
+<wire x1="101.321" y1="31.138" x2="85.994" y2="86.36" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="N$12">
 <polygon width="0.4064" layer="2">
@@ -9277,8 +9533,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <contactref element="U7" pad="P12"/>
 <contactref element="U7" pad="M12"/>
 <contactref element="U7" pad="K12"/>
-<wire x1="77.4836" y1="99.6696" x2="157.886" y2="61.976" width="0" layer="19" extent="1-1"/>
-<wire x1="51.0808" y1="59.2088" x2="77.4836" y2="99.6696" width="0" layer="19" extent="1-1"/>
+<wire x1="72.1496" y1="100.4316" x2="157.886" y2="61.976" width="0" layer="19" extent="1-1"/>
+<wire x1="51.0808" y1="59.2088" x2="72.1496" y2="100.4316" width="0" layer="19" extent="1-1"/>
 <wire x1="51.0808" y1="57.2088" x2="51.0808" y2="59.2088" width="0" layer="19" extent="1-1"/>
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 <wire x1="49.0808" y1="57.2088" x2="51.0808" y2="57.2088" width="0" layer="19" extent="1-1"/>
@@ -9726,21 +9982,53 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <contactref element="U7" pad="P18"/>
 <contactref element="U7" pad="M14"/>
 <contactref element="R27" pad="2"/>
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-<wire x1="80.3152" y1="60.2972" x2="79.728" y2="78.6892" width="0" layer="19" extent="1-1"/>
+<contactref element="C201" pad="1"/>
+<contactref element="C200" pad="1"/>
+<contactref element="C197" pad="1"/>
+<contactref element="C196" pad="1"/>
+<contactref element="C195" pad="1"/>
+<contactref element="C194" pad="1"/>
+<contactref element="C199" pad="1"/>
+<contactref element="C198" pad="1"/>
+<contactref element="C208" pad="1"/>
+<contactref element="C207" pad="1"/>
+<contactref element="C206" pad="1"/>
+<contactref element="IC1" pad="43"/>
+<contactref element="IC1" pad="29"/>
+<contactref element="IC1" pad="15"/>
+<contactref element="IC1" pad="81"/>
+<contactref element="IC1" pad="75"/>
+<contactref element="IC1" pad="55"/>
+<contactref element="IC1" pad="49"/>
+<contactref element="IC1" pad="41"/>
+<contactref element="IC1" pad="35"/>
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@@ -9794,82 +10082,92 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <wire x1="26.162" y1="75.946" x2="23.622" y2="75.946" width="0" layer="19" extent="1-1"/>
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-</signal>
-<signal name="FPGA_FMC_CLK">
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+<wire x1="48.88" y1="101.6" x2="45.832" y2="101.6" width="0" layer="19" extent="1-1"/>
+<wire x1="48.88" y1="100.584" x2="48.88" y2="101.6" width="0" layer="19" extent="1-1"/>
+<wire x1="52.744" y1="101.6" x2="48.88" y2="101.6" width="0" layer="19" extent="1-1"/>
+<wire x1="52.744" y1="99.568" x2="52.744" y2="101.6" width="0" layer="19" extent="1-1"/>
+<wire x1="53.76" y1="95.504" x2="52.744" y2="99.568" width="0" layer="19" extent="1-1"/>
+<wire x1="53.76" y1="93.472" x2="53.76" y2="95.504" width="0" layer="19" extent="1-1"/>
+<wire x1="48.88" y1="95.504" x2="53.76" y2="95.504" width="0" layer="19" extent="1-1"/>
+<wire x1="48.88" y1="94.488" x2="48.88" y2="95.504" width="0" layer="19" extent="1-1"/>
+<wire x1="45.832" y1="94.488" x2="48.88" y2="94.488" width="0" layer="19" extent="1-1"/>
+<wire x1="45.832" y1="95.504" x2="45.832" y2="94.488" width="0" layer="19" extent="1-1"/>
+<wire x1="61.6428" y1="94.8944" x2="53.76" y2="95.504" width="0" layer="19" extent="1-1"/>
+<wire x1="61.5412" y1="98.7552" x2="61.6428" y2="94.8944" width="0" layer="19" extent="1-1"/>
+<wire x1="66.5196" y1="94.6912" x2="61.6428" y2="94.8944" width="0" layer="19" extent="1-1"/>
+<wire x1="66.6212" y1="98.9584" x2="66.5196" y2="94.6912" width="0" layer="19" extent="1-1"/>
+<wire x1="77.49" y1="99.194" x2="66.6212" y2="98.9584" width="0" layer="19" extent="1-1"/>
+<wire x1="77.89" y1="101.092" x2="77.49" y2="99.194" width="0" layer="19" extent="1-1"/>
+<wire x1="79.59" y1="94.996" x2="77.49" y2="99.194" width="0" layer="19" extent="1-1"/>
+<wire x1="84.836" y1="99.822" x2="77.89" y2="101.092" width="0" layer="19" extent="1-1"/>
+<wire x1="94.0054" y1="100.457" x2="84.836" y2="99.822" width="0" layer="19" extent="1-1"/>
+<wire x1="94.0054" y1="99.187" x2="94.0054" y2="100.457" width="0" layer="19" extent="1-1"/>
+<wire x1="96.178" y1="96.52" x2="94.0054" y2="99.187" width="0" layer="19" extent="1-1"/>
+<wire x1="97.878" y1="100.584" x2="94.0054" y2="100.457" width="0" layer="19" extent="1-1"/>
+<wire x1="79.728" y1="78.6892" x2="79.59" y2="94.996" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_CLK">
 <contactref element="U7" pad="W11"/>
 <contactref element="U$1" pad="167"/>
 <wire x1="75.4892" y1="53.4646" x2="68.7782" y2="53.4646" width="0.3048" layer="1"/>
+<contactref element="IC1" pad="68"/>
 <wire x1="42.0808" y1="58.2088" x2="68.7782" y2="53.4646" width="0" layer="19" extent="1-1"/>
+<wire x1="-1.182" y1="14.962" x2="42.0808" y2="58.2088" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_PROM_SCLK">
 <contactref element="IC3" pad="6"/>
 <contactref element="U1" pad="11"/>
-<wire x1="109.3978" y1="84.455" x2="109.7534" y2="96.901" width="0" layer="19" extent="1-1"/>
+<wire x1="93.6498" y1="85.471" x2="94.0054" y2="97.917" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_PROM_MOSI">
 <contactref element="IC3" pad="5"/>
 <contactref element="U1" pad="6"/>
-<wire x1="104.4702" y1="84.455" x2="109.7534" y2="95.631" width="0" layer="19" extent="1-1"/>
+<wire x1="88.7222" y1="85.471" x2="94.0054" y2="96.647" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_PROM_CS_N">
 <contactref element="IC3" pad="1"/>
 <contactref element="R9" pad="1"/>
 <contactref element="U1" pad="2"/>
-<wire x1="103.6066" y1="99.441" x2="111.926" y2="99.568" width="0" layer="19" extent="1-1"/>
-<wire x1="104.4702" y1="89.535" x2="103.6066" y2="99.441" width="0" layer="19" extent="1-1"/>
+<wire x1="87.8586" y1="100.457" x2="96.178" y2="100.584" width="0" layer="19" extent="1-1"/>
+<wire x1="88.7222" y1="90.551" x2="87.8586" y2="100.457" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_PROM_MISO">
 <contactref element="IC3" pad="2"/>
 <contactref element="U1" pad="15"/>
-<wire x1="109.3978" y1="89.535" x2="103.6066" y2="98.171" width="0" layer="19" extent="1-1"/>
+<wire x1="93.6498" y1="90.551" x2="87.8586" y2="99.187" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_PROM_W_N">
 <contactref element="IC3" pad="3"/>
 <contactref element="R20" pad="2"/>
 <contactref element="JP7" pad="1"/>
-<wire x1="103.6066" y1="96.901" x2="113.626" y2="97.536" width="0" layer="19" extent="1-1"/>
-<wire x1="100.584" y1="96.266" x2="103.6066" y2="96.901" width="0" layer="19" extent="1-1"/>
+<wire x1="87.8586" y1="97.917" x2="97.878" y2="98.552" width="0" layer="19" extent="1-1"/>
+<wire x1="84.836" y1="97.282" x2="87.8586" y2="97.917" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_GPIO_TAMPER_0">
 <contactref element="U7" pad="F15"/>
@@ -9984,7 +10282,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <signal name="FPGA_GCLK">
 <contactref element="U7" pad="D17"/>
 <contactref element="Q5" pad="3"/>
-<wire x1="57.0808" y1="52.2088" x2="90.658" y2="98.686" width="0" layer="19" extent="1-1"/>
+<wire x1="57.0808" y1="52.2088" x2="79.99" y2="99.194" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="DIGITIZED_NOISE">
 <contactref element="U7" pad="W19"/>
@@ -10097,7 +10395,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <signal name="N$33">
 <contactref element="Q5" pad="1"/>
 <contactref element="R28" pad="1"/>
-<wire x1="88.558" y1="94.488" x2="88.158" y2="96.386" width="0" layer="19" extent="1-1"/>
+<wire x1="77.89" y1="94.996" x2="77.49" y2="96.894" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_INIT_B_INT">
 <contactref element="U7" pad="U12"/>
@@ -10473,15 +10771,23 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 </signal>
 <signal name="FMC_A22">
 <contactref element="U7" pad="Y12"/>
+<contactref element="U$1" pad="5"/>
+<wire x1="41.0808" y1="57.2088" x2="79.3246" y2="31.138" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A23">
 <contactref element="U7" pad="W12"/>
+<contactref element="U$1" pad="1"/>
+<wire x1="42.0808" y1="57.2088" x2="77.318" y2="31.138" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A24">
 <contactref element="U7" pad="V13"/>
+<contactref element="U$1" pad="182"/>
+<wire x1="43.0808" y1="56.2088" x2="75.4892" y2="45.9716" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FMC_A25">
 <contactref element="U7" pad="V14"/>
+<contactref element="U$1" pad="183"/>
+<wire x1="43.0808" y1="55.2088" x2="75.4892" y2="45.4636" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="15V_STABLE">
 <contactref element="R2" pad="1"/>
@@ -10533,30 +10839,30 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <contactref element="R30" pad="1"/>
 <contactref element="R31" pad="1"/>
 <contactref element="R6" pad="1"/>
-<wire x1="101.204" y1="88.392" x2="100.696" y2="87.122" width="0" layer="19" extent="1-1"/>
-<wire x1="100.442" y1="85.344" x2="100.696" y2="87.122" width="0" layer="19" extent="1-1"/>
-<wire x1="56.6928" y1="2.9718" x2="100.442" y2="85.344" width="0" layer="19" extent="1-1"/>
+<wire x1="84.948" y1="88.138" x2="85.456" y2="89.408" width="0" layer="19" extent="1-1"/>
+<wire x1="84.694" y1="86.36" x2="84.948" y2="88.138" width="0" layer="19" extent="1-1"/>
+<wire x1="56.6928" y1="2.9718" x2="84.694" y2="86.36" width="0" layer="19" extent="1-1"/>
 <wire x1="52.436" y1="1.524" x2="56.6928" y2="2.9718" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_CFG_SCLK">
 <contactref element="U1" pad="13"/>
 <contactref element="U7" pad="L12"/>
-<wire x1="50.0808" y1="57.2088" x2="109.3978" y2="86.995" width="0" layer="19" extent="1-1"/>
+<wire x1="50.0808" y1="57.2088" x2="93.6498" y2="88.011" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_CFG_MOSI">
 <contactref element="U1" pad="5"/>
 <contactref element="U7" pad="P22"/>
-<wire x1="47.0808" y1="47.2088" x2="104.4702" y2="85.725" width="0" layer="19" extent="1-1"/>
+<wire x1="47.0808" y1="47.2088" x2="88.7222" y2="86.741" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_CFG_CS_N">
 <contactref element="U1" pad="4"/>
 <contactref element="U7" pad="T19"/>
-<wire x1="45.0808" y1="50.2088" x2="104.4702" y2="86.995" width="0" layer="19" extent="1-1"/>
+<wire x1="45.0808" y1="50.2088" x2="88.7222" y2="88.011" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="FPGA_CFG_MISO">
 <contactref element="U1" pad="14"/>
 <contactref element="U7" pad="R22"/>
-<wire x1="46.0808" y1="47.2088" x2="109.3978" y2="88.265" width="0" layer="19" extent="1-1"/>
+<wire x1="46.0808" y1="47.2088" x2="93.6498" y2="89.281" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="ARM_FPGA_CFG_CS_N">
 <contactref element="U1" pad="3"/>
@@ -10564,79 +10870,209 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 <signal name="ARM_FPGA_CFG_MOSI">
 <contactref element="U1" pad="10"/>
 <contactref element="U$1" pad="163"/>
-<wire x1="75.4892" y1="55.4712" x2="109.3978" y2="83.185" width="0" layer="19" extent="1-1"/>
+<wire x1="75.4892" y1="55.4712" x2="93.6498" y2="84.201" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="ARM_FPGA_CFG_MISO">
 <contactref element="U1" pad="1"/>
 <contactref element="U$1" pad="162"/>
-<wire x1="75.4892" y1="55.9792" x2="104.4702" y2="90.805" width="0" layer="19" extent="1-1"/>
+<wire x1="75.4892" y1="55.9792" x2="88.7222" y2="91.821" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="ARM_FPGA_CFG_SCLK">
 <contactref element="U1" pad="12"/>
 <contactref element="U$1" pad="161"/>
-<wire x1="75.4892" y1="56.4618" x2="109.3978" y2="85.725" width="0" layer="19" extent="1-1"/>
+<wire x1="75.4892" y1="56.4618" x2="93.6498" y2="86.741" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="N$3">
 <contactref element="U1" pad="9"/>
 <contactref element="R32" pad="2"/>
 <contactref element="JP8" pad="1"/>
-<wire x1="109.3978" y1="81.915" x2="112.522" y2="85.852" width="0" layer="19" extent="1-1"/>
-<wire x1="101.688" y1="82.296" x2="109.3978" y2="81.915" width="0" layer="19" extent="1-1"/>
+<wire x1="93.6498" y1="82.931" x2="96.774" y2="86.868" width="0" layer="19" extent="1-1"/>
+<wire x1="85.94" y1="83.312" x2="93.6498" y2="82.931" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="ARM_FPGA_CFG_CONTROL">
 <contactref element="JP8" pad="2"/>
 <contactref element="U$1" pad="166"/>
-<wire x1="75.4892" y1="53.9726" x2="112.522" y2="88.392" width="0" layer="19" extent="1-1"/>
+<wire x1="75.4892" y1="53.9726" x2="96.774" y2="89.408" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="VDD">
 <contactref element="IC1" pad="1"/>
-<contactref element="IC1" pad="15"/>
-<contactref element="IC1" pad="29"/>
-<contactref element="IC1" pad="43"/>
-<wire x1="-13.042" y1="16.962" x2="-13.042" y2="23.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="9.962" x2="-13.042" y2="16.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="2.962" x2="-13.042" y2="9.962" width="0" layer="19" extent="1-1"/>
 </signal>
 <signal name="VDDQ">
 <contactref element="IC1" pad="3"/>
-<contactref element="IC1" pad="35"/>
-<contactref element="IC1" pad="41"/>
-<contactref element="IC1" pad="49"/>
-<contactref element="IC1" pad="55"/>
-<contactref element="IC1" pad="75"/>
-<contactref element="IC1" pad="81"/>
-<wire x1="-1.182" y1="18.462" x2="-1.182" y2="21.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="8.462" x2="-1.182" y2="18.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="5.462" x2="-1.182" y2="8.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="22.962" x2="-1.182" y2="21.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="3.962" x2="-1.182" y2="5.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="6.962" x2="-13.042" y2="3.962" width="0" layer="19" extent="1-1"/>
 </signal>
-<signal name="VSSQ">
-<contactref element="IC1" pad="6"/>
-<contactref element="IC1" pad="12"/>
-<contactref element="IC1" pad="32"/>
-<contactref element="IC1" pad="38"/>
-<contactref element="IC1" pad="46"/>
-<contactref element="IC1" pad="52"/>
-<contactref element="IC1" pad="78"/>
-<contactref element="IC1" pad="84"/>
-<wire x1="-1.182" y1="19.962" x2="-1.182" y2="22.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="21.462" x2="-1.182" y2="22.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="18.462" x2="-13.042" y2="21.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="8.462" x2="-13.042" y2="18.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-13.042" y1="5.462" x2="-13.042" y2="8.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="6.962" x2="-13.042" y2="8.462" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="3.962" x2="-1.182" y2="6.962" width="0" layer="19" extent="1-1"/>
-</signal>
-<signal name="VSS">
-<contactref element="IC1" pad="44"/>
-<contactref element="IC1" pad="58"/>
-<contactref element="IC1" pad="72"/>
-<contactref element="IC1" pad="86"/>
-<wire x1="-1.182" y1="16.962" x2="-1.182" y2="23.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="9.962" x2="-1.182" y2="16.962" width="0" layer="19" extent="1-1"/>
-<wire x1="-1.182" y1="2.962" x2="-1.182" y2="9.962" width="0" layer="19" extent="1-1"/>
+<signal name="FT_RESET1">
+<contactref element="U$10" pad="34"/>
+<contactref element="R69" pad="1"/>
+<wire x1="116.444" y1="90.424" x2="115.598" y2="101.532" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_VCCA1">
+<contactref element="U$10" pad="37"/>
+<contactref element="C9" pad="1"/>
+<wire x1="113.098" y1="100.032" x2="123.302" y2="95.25" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_VCCORE1">
+<contactref element="U$10" pad="38"/>
+<contactref element="C10" pad="1"/>
+<wire x1="113.098" y1="99.532" x2="123.048" y2="96.774" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_REF1">
+<contactref element="U$10" pad="5"/>
+<contactref element="R70" pad="1"/>
+<wire x1="116.598" y1="93.032" x2="125.73" y2="100.188" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$6">
+<contactref element="R71" pad="1"/>
+<contactref element="LED17" pad="C"/>
+<wire x1="123.329" y1="91.186" x2="123.302" y2="101.6" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$7">
+<contactref element="R72" pad="1"/>
+<contactref element="LED18" pad="C"/>
+<wire x1="123.329" y1="92.456" x2="120.762" y2="101.6" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_RXLED1">
+<contactref element="U$10" pad="27"/>
+<contactref element="R71" pad="2"/>
+<wire x1="119.098" y1="101.532" x2="124.602" y2="101.6" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_TXLED1">
+<contactref element="U$10" pad="28"/>
+<contactref element="R72" pad="2"/>
+<wire x1="118.598" y1="101.532" x2="122.062" y2="101.6" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$8">
+<contactref element="C11" pad="2"/>
+<contactref element="U$10" pad="2"/>
+<contactref element="Y2" pad="2"/>
+<wire x1="115.098" y1="93.032" x2="125.31" y2="88.9" width="0" layer="19" extent="1-1"/>
+<wire x1="118.448" y1="98.336" x2="115.098" y2="93.032" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$9">
+<contactref element="C12" pad="2"/>
+<contactref element="U$10" pad="1"/>
+<contactref element="Y2" pad="1"/>
+<wire x1="114.598" y1="93.032" x2="116.248" y2="96.736" width="0" layer="19" extent="1-1"/>
+<wire x1="120.738" y1="90.424" x2="114.598" y2="93.032" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_MGMT_VREGIN">
+<contactref element="U$10" pad="40"/>
+<contactref element="CN2" pad="VBUS"/>
+<contactref element="C180" pad="1"/>
+<contactref element="C179" pad="1"/>
+<wire x1="110.602" y1="100.584" x2="113.098" y2="98.532" width="0" layer="19" extent="1-1"/>
+<wire x1="107.608" y1="101.092" x2="110.602" y2="100.584" width="0" layer="19" extent="1-1"/>
+<wire x1="105.334" y1="99.06" x2="107.608" y2="101.092" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_MGMT_VCC3V3">
+<contactref element="U$10" pad="39"/>
+<contactref element="R69" pad="2"/>
+<contactref element="LED17" pad="A"/>
+<contactref element="LED18" pad="A"/>
+<contactref element="C181" pad="1"/>
+<contactref element="C182" pad="1"/>
+<contactref element="U$10" pad="46"/>
+<contactref element="U$10" pad="24"/>
+<contactref element="U$10" pad="12"/>
+<contactref element="C187" pad="1"/>
+<contactref element="C188" pad="1"/>
+<contactref element="C189" pad="1"/>
+<contactref element="FB4" pad="1"/>
+<contactref element="FB3" pad="1"/>
+<wire x1="123.356" y1="93.726" x2="121.598" y2="100.032" width="0" layer="19" extent="1-1"/>
+<wire x1="125.083" y1="92.456" x2="123.356" y2="93.726" width="0" layer="19" extent="1-1"/>
+<wire x1="125.083" y1="91.186" x2="125.083" y2="92.456" width="0" layer="19" extent="1-1"/>
+<wire x1="120.098" y1="93.032" x2="123.356" y2="93.726" width="0" layer="19" extent="1-1"/>
+<wire x1="118.984" y1="91.694" x2="120.098" y2="93.032" width="0" layer="19" extent="1-1"/>
+<wire x1="117.744" y1="90.424" x2="118.984" y2="91.694" width="0" layer="19" extent="1-1"/>
+<wire x1="117.856" y1="88.9" x2="117.744" y2="90.424" width="0" layer="19" extent="1-1"/>
+<wire x1="120.762" y1="88.9" x2="117.856" y2="88.9" width="0" layer="19" extent="1-1"/>
+<wire x1="113.396" y1="90.424" x2="117.744" y2="90.424" width="0" layer="19" extent="1-1"/>
+<wire x1="113.538" y1="89.408" x2="113.396" y2="90.424" width="0" layer="19" extent="1-1"/>
+<wire x1="113.396" y1="91.694" x2="113.396" y2="90.424" width="0" layer="19" extent="1-1"/>
+<wire x1="113.098" y1="95.532" x2="113.396" y2="91.694" width="0" layer="19" extent="1-1"/>
+<wire x1="113.098" y1="99.032" x2="113.098" y2="95.532" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="USB_MGMT_DP">
+<contactref element="CN2" pad="D+"/>
+<contactref element="U$10" pad="7"/>
+<wire x1="106.934" y1="99.06" x2="117.598" y2="93.032" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="USB_MGMT_DM">
+<contactref element="U$10" pad="6"/>
+<contactref element="CN2" pad="D-"/>
+<wire x1="106.134" y1="99.06" x2="117.098" y2="93.032" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_MGMT_VPLL">
+<contactref element="U$10" pad="8"/>
+<contactref element="C185" pad="1"/>
+<contactref element="C186" pad="1"/>
+<contactref element="FB3" pad="2"/>
+<wire x1="119.38" y1="88.9" x2="123.556" y2="90.17" width="0" layer="19" extent="1-1"/>
+<wire x1="118.098" y1="93.032" x2="119.38" y2="88.9" width="0" layer="19" extent="1-1"/>
+<wire x1="102.936" y1="101.346" x2="118.098" y2="93.032" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FT_MGMT_VPHY">
+<contactref element="U$10" pad="3"/>
+</signal>
+<signal name="FT_MGMT_TXD">
+<contactref element="U$10" pad="13"/>
+</signal>
+<signal name="FT_MGMT_RXD">
+<contactref element="U$10" pad="14"/>
+</signal>
+<signal name="FT_MGMT_RTS">
+<contactref element="U$10" pad="15"/>
+</signal>
+<signal name="FT_MGMT_CTS">
+<contactref element="U$10" pad="16"/>
+</signal>
+<signal name="FT_MGMT_DTR">
+<contactref element="U$10" pad="17"/>
+</signal>
+<signal name="FMC_SDCKE0">
+<contactref element="U$1" pad="38"/>
+<contactref element="IC1" pad="67"/>
+<wire x1="-1.182" y1="14.462" x2="95.8092" y2="31.138" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_SDNE0">
+<contactref element="U$1" pad="37"/>
+<contactref element="IC1" pad="20"/>
+<wire x1="-13.042" y1="14.462" x2="95.3266" y2="31.138" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_SDNWE">
+<contactref element="U$1" pad="35"/>
+<contactref element="IC1" pad="17"/>
+<wire x1="-13.042" y1="15.962" x2="94.3106" y2="31.138" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_SDNCAS">
+<contactref element="U$1" pad="191"/>
+<contactref element="IC1" pad="18"/>
+<wire x1="-13.042" y1="15.462" x2="75.4892" y2="41.4758" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_SDNRAS">
+<contactref element="U$1" pad="70"/>
+<contactref element="IC1" pad="19"/>
+<wire x1="-13.042" y1="14.962" x2="104.6484" y2="41.4758" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_NBL0">
+<contactref element="IC1" pad="16"/>
+<contactref element="U$1" pad="200"/>
+<wire x1="-13.042" y1="16.462" x2="75.4892" y2="36.98" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_NBL1">
+<contactref element="IC1" pad="71"/>
+<contactref element="U$1" pad="201"/>
+<wire x1="-1.182" y1="16.462" x2="75.4892" y2="36.472" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_NBL2">
+<contactref element="IC1" pad="28"/>
+<contactref element="U$1" pad="205"/>
+<wire x1="-13.042" y1="10.462" x2="75.4892" y2="34.4654" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="FMC_NBL3">
+<contactref element="IC1" pad="59"/>
+<contactref element="U$1" pad="206"/>
+<wire x1="-1.182" y1="10.462" x2="75.4892" y2="33.9574" width="0" layer="19" extent="1-1"/>
 </signal>
 </signals>
 <errors>
diff --git a/eagle/alpha/rev02/rev02.pdf b/eagle/alpha/rev02/rev02.pdf
index b0e8966..66dd8d6 100644
Binary files a/eagle/alpha/rev02/rev02.pdf and b/eagle/alpha/rev02/rev02.pdf differ
diff --git a/eagle/alpha/rev02/rev02.sch b/eagle/alpha/rev02/rev02.sch
index dd781d0..748d8ad 100644
--- a/eagle/alpha/rev02/rev02.sch
+++ b/eagle/alpha/rev02/rev02.sch
@@ -36664,6 +36664,155 @@ Source:</description>
 <part name="FRAME10" library="microbuilder" deviceset="FRAME_A3" device=""/>
 <part name="JP8" library="jumper" deviceset="JP1Q" device=""/>
 <part name="IC1" library="Alpha-IC" deviceset="IS45S32160F" device=""/>
+<part name="U$10" library="FT232H" deviceset="FT232H_SERIAL" device=""/>
+<part name="R69" library="resistor" deviceset="R-EU_" device="R0402" value="10K"/>
+<part name="C9" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C10" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY15" library="supply2" deviceset="GND" device=""/>
+<part name="SUPPLY16" library="supply2" deviceset="GND" device=""/>
+<part name="R70" library="resistor" deviceset="R-EU_" device="R0402" value="12K">
+<attribute name="TOLERANCE" value="1%"/>
+</part>
+<part name="R71" library="resistor" deviceset="R-EU_" device="R0402" value="220"/>
+<part name="R72" library="resistor" deviceset="R-EU_" device="R0402" value="220"/>
+<part name="LED17" library="SparkFun-LED" deviceset="LED" device="0603" value="YELLOW"/>
+<part name="LED18" library="SparkFun-LED" deviceset="LED" device="0603" value="GREEN"/>
+<part name="SUPPLY17" library="supply2" deviceset="GND" device=""/>
+<part name="C11" library="rcl" deviceset="C-EU" device="C0603" value="5 pF">
+<attribute name="DIELECTRIC" value="C0G"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C12" library="rcl" deviceset="C-EU" device="C0603" value="5 pF">
+<attribute name="DIELECTRIC" value="C0G"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY32" library="supply2" deviceset="GND" device=""/>
+<part name="SUPPLY58" library="supply2" deviceset="GND" device=""/>
+<part name="FT_VCC3V1" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_10" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="C179" library="resistor" deviceset="C-EU" device="C0603" value="4.7 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C180" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY186" library="supply2" deviceset="GND" device=""/>
+<part name="C181" library="resistor" deviceset="C-EU" device="C0603" value="4.7 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C182" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY187" library="supply2" deviceset="GND" device=""/>
+<part name="C183" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C184" library="resistor" deviceset="C-EU" device="C0805" value="10 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY188" library="supply2" deviceset="GND" device=""/>
+<part name="C185" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C186" library="resistor" deviceset="C-EU" device="C0805" value="10 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY199" library="supply2" deviceset="GND" device=""/>
+<part name="C187" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C188" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C189" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="SUPPLY212" library="supply2" deviceset="GND" device=""/>
+<part name="FT_VCC3V3_11" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FB3" library="microbuilder" deviceset="FERRITE" device="_0603MP" value="600R 500mA"/>
+<part name="FB4" library="microbuilder" deviceset="FERRITE" device="_0603MP" value="600R 500mA"/>
+<part name="CN2" library="adafruit" deviceset="USB" device="MINIB" value="HOST"/>
+<part name="SUPPLY213" library="supply2" deviceset="GND" device=""/>
+<part name="Y2" library="microbuilder" deviceset="CRYSTAL" device="THIN" value="12 MHz">
+<attribute name="MPN" value="ABM8G-12.000MHZ-4Y-T3"/>
+<attribute name="OC_FARNELL" value="2467837"/>
+<attribute name="SUPPLIER" value="ABRACON"/>
+<attribute name="TOLERANCE" value="±30 ppm"/>
+</part>
+<part name="FRAME24" library="frames" deviceset="A3L-LOC" device=""/>
+<part name="FT_VCC3V3_12" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_13" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_14" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_15" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_16" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_17" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="FT_VCC3V3_18" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="P+58" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="SUPPLY214" library="supply2" deviceset="GND" device=""/>
+<part name="C194" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C195" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C196" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C197" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C198" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C199" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C200" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C201" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C206" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C207" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="C208" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF">
+<attribute name="DIELECTRIC" value="X7R"/>
+<attribute name="RATED_VOLTAGE" value="10V"/>
+</part>
+<part name="P+59" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="P+60" library="SUPPLY1" deviceset="VCC" device=""/>
+<part name="SUPPLY215" library="supply2" deviceset="GND" device=""/>
 </parts>
 <sheets>
 <sheet>
@@ -36702,9 +36851,9 @@ Source:</description>
 and supplying stable 15V to noise source</text>
 <text x="-172.72" y="63.5" size="3.81" layer="91">Main power input
 18V DC</text>
-<text x="-53.34" y="55.88" size="1.778" layer="91">Jumper deciding if FPGA/ARM/None
-should be allowed to turn off the
-entropy source
+<text x="-83.82" y="50.8" size="1.778" layer="91">To mitigate component ageing in the avalanche noise circuit,
+this jumper can be used to decide if FPGA/ARM/None should
+be allowed to turn off the entropy source
 (default On through pull-up)</text>
 <text x="88.9" y="17.78" size="1.778" layer="91">Max 3 ohm ESR</text>
 <text x="-55.88" y="-40.64" size="2.54" layer="91">*) Intermediate Regulator: 18V -> 5V</text>
@@ -36713,6 +36862,8 @@ entropy source
 *) Current sharing not used
 
 *) SYNC is not used</text>
+<text x="-81.28" y="17.78" size="1.778" layer="91">XXX add circuitry to allow FPGA/ARM to control sinking
+of the 18V from the 10K pull-up on pin 2.</text>
 </plain>
 <instances>
 <instance part="FRAME6" gate="G$1" x="-198.12" y="-142.24"/>
@@ -36740,8 +36891,8 @@ entropy source
 <attribute name="RATED_VOLTAGE" x="86.36" y="27.94" size="1.778" layer="96" display="off"/>
 </instance>
 <instance part="SUPPLY12" gate="GND" x="86.36" y="12.7" rot="MR0"/>
-<instance part="JP2" gate="G$1" x="-25.4" y="33.02" rot="R180"/>
-<instance part="R22" gate="G$1" x="-12.7" y="40.64" rot="R270"/>
+<instance part="JP2" gate="G$1" x="-33.02" y="33.02" rot="R180"/>
+<instance part="R22" gate="G$1" x="-20.32" y="40.64" rot="R270"/>
 <instance part="PWR_18V" gate="VCC" x="-142.24" y="55.88" smashed="yes">
 <attribute name="VALUE" x="-139.7" y="55.88" size="1.778" layer="96"/>
 </instance>
@@ -36840,8 +36991,8 @@ entropy source
 <instance part="PWR_18V3" gate="VCC" x="-124.46" y="-48.26" smashed="yes">
 <attribute name="VALUE" x="-121.92" y="-48.26" size="1.778" layer="96"/>
 </instance>
-<instance part="PWR_18V4" gate="VCC" x="-12.7" y="50.8" smashed="yes">
-<attribute name="VALUE" x="-10.16" y="50.8" size="1.778" layer="96"/>
+<instance part="PWR_18V4" gate="VCC" x="-20.32" y="50.8" smashed="yes">
+<attribute name="VALUE" x="-17.78" y="50.8" size="1.778" layer="96"/>
 </instance>
 <instance part="PWR_18V5" gate="VCC" x="83.82" y="-48.26" smashed="yes">
 <attribute name="VALUE" x="86.36" y="-48.26" size="1.778" layer="96"/>
@@ -36988,9 +37139,9 @@ entropy source
 </segment>
 <segment>
 <pinref part="R22" gate="G$1" pin="1"/>
-<wire x1="-12.7" y1="48.26" x2="-12.7" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="-20.32" y1="48.26" x2="-20.32" y2="45.72" width="0.1524" layer="91"/>
 <pinref part="PWR_18V4" gate="VCC" pin="VCC"/>
-<label x="-10.16" y="48.26" size="1.778" layer="95"/>
+<label x="-17.78" y="48.26" size="1.778" layer="95"/>
 </segment>
 </net>
 <net name="N$1" class="0">
@@ -37009,20 +37160,20 @@ entropy source
 </net>
 <net name="FPGA_ENTROPY_ENABLE" class="0">
 <segment>
-<wire x1="-33.02" y1="35.56" x2="-63.5" y2="35.56" width="0.1524" layer="91"/>
-<label x="-33.02" y="38.1" size="1.778" layer="95" rot="R180"/>
+<wire x1="-40.64" y1="35.56" x2="-71.12" y2="35.56" width="0.1524" layer="91"/>
+<label x="-40.64" y="38.1" size="1.778" layer="95" rot="R180"/>
 <pinref part="JP2" gate="G$1" pin="1"/>
 </segment>
 </net>
 <net name="15V_LDO_ENABLE" class="0">
 <segment>
 <pinref part="JP2" gate="G$1" pin="2"/>
-<wire x1="-33.02" y1="33.02" x2="-12.7" y2="33.02" width="0.1524" layer="91"/>
-<label x="-17.78" y="30.48" size="1.778" layer="95"/>
+<wire x1="-40.64" y1="33.02" x2="-20.32" y2="33.02" width="0.1524" layer="91"/>
+<label x="-25.4" y="30.48" size="1.778" layer="95"/>
 <pinref part="R22" gate="G$1" pin="2"/>
-<wire x1="-12.7" y1="33.02" x2="2.54" y2="33.02" width="0.1524" layer="91"/>
-<wire x1="-12.7" y1="35.56" x2="-12.7" y2="33.02" width="0.1524" layer="91"/>
-<junction x="-12.7" y="33.02"/>
+<wire x1="-20.32" y1="33.02" x2="-5.08" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="-20.32" y1="35.56" x2="-20.32" y2="33.02" width="0.1524" layer="91"/>
+<junction x="-20.32" y="33.02"/>
 </segment>
 <segment>
 <pinref part="U$9" gate="G$1" pin="!SHDN"/>
@@ -37383,10 +37534,10 @@ Ethernet, USB OTG and I2C</text>
 Reset circuit not needed,
 but pull-down cap
 recommended.</text>
-<text x="276.86" y="17.78" size="0.8128" layer="91">PDR_ON high enables
+<text x="299.72" y="17.78" size="0.8128" layer="91">PDR_ON high enables
 internal power regulator</text>
 <text x="368.3" y="40.64" size="1.778" layer="91">CL 10pF</text>
-<text x="104.14" y="147.32" size="1.27" layer="91">FPGA_DONE can be swapped with any
+<text x="116.84" y="137.16" size="1.27" layer="91">FPGA_DONE can be swapped with any
 other available GPIO pin on the ARM</text>
 <text x="137.16" y="-46.99" size="1.778" layer="91">*) FPGA_GPIO_*, FPGA_IRQ_N_* and
 FPGA_{PROGRAM,INIT}_B signals
@@ -37433,7 +37584,7 @@ available GPIO on the ARM</text>
 </instance>
 <instance part="SUPPLY25" gate="GND" x="350.52" y="124.46"/>
 <instance part="P+10" gate="VCC" x="350.52" y="152.4" smashed="yes"/>
-<instance part="P+11" gate="VCC" x="403.86" y="161.29"/>
+<instance part="P+11" gate="VCC" x="403.86" y="161.29" smashed="yes"/>
 <instance part="SUPPLY26" gate="GND" x="403.86" y="121.92"/>
 <instance part="C18" gate="G$1" x="449.58" y="149.86" smashed="yes">
 <attribute name="NAME" x="449.58" y="154.94" size="1.27" layer="95" font="vector"/>
@@ -37521,7 +37672,7 @@ available GPIO on the ARM</text>
 <attribute name="DIELECTRIC" x="101.6" y="63.5" size="1.778" layer="96" display="off"/>
 <attribute name="RATED_VOLTAGE" x="101.6" y="63.5" size="1.778" layer="96" display="off"/>
 </instance>
-<instance part="P+15" gate="VCC" x="104.14" y="166.37" smashed="yes"/>
+<instance part="P+15" gate="VCC" x="124.46" y="166.37" smashed="yes"/>
 <instance part="SUPPLY28" gate="GND" x="274.32" y="-58.42"/>
 <instance part="R10" gate="G$1" x="274.32" y="-48.26" rot="R90"/>
 <instance part="C40" gate="G$1" x="436.88" y="22.86" smashed="yes">
@@ -37536,7 +37687,7 @@ available GPIO on the ARM</text>
 <instance part="P+16" gate="VCC" x="414.02" y="53.34" smashed="yes"/>
 <instance part="FRAME3" gate="G$1" x="-53.34" y="-116.84"/>
 <instance part="FRAME3" gate="G$2" x="398.78" y="-116.84"/>
-<instance part="P+17" gate="VCC" x="274.32" y="25.4" smashed="yes"/>
+<instance part="P+17" gate="VCC" x="297.18" y="25.4" smashed="yes"/>
 <instance part="C56" gate="G$1" x="106.68" y="63.5" smashed="yes">
 <attribute name="NAME" x="111.76" y="66.04" size="1.27" layer="95" font="vector"/>
 <attribute name="DIELECTRIC" x="106.68" y="63.5" size="1.778" layer="96" display="off"/>
@@ -37576,36 +37727,39 @@ available GPIO on the ARM</text>
 <instance part="SUPPLY5" gate="GND" x="414.02" y="15.24"/>
 </instances>
 <busses>
-<bus name="FMC_D[0..31],FMC_A[0..19],FMC_NE1,FMC_NOE,FMC_NWE,FMC_NL,FMC_NWAIT">
+<bus name="FMC_D[0..31],FMC_A[0..25]">
 <segment>
-<wire x1="165.1" y1="45.72" x2="165.1" y2="-10.16" width="0.762" layer="92"/>
+<wire x1="144.78" y1="38.1" x2="144.78" y2="-35.56" width="0.762" layer="92"/>
+<wire x1="144.78" y1="38.1" x2="116.84" y2="38.1" width="0.762" layer="92"/>
+<label x="114.3" y="40.64" size="1.778" layer="95"/>
 </segment>
 <segment>
 <wire x1="165.1" y1="195.58" x2="165.1" y2="114.3" width="0.762" layer="92"/>
+<wire x1="165.1" y1="195.58" x2="134.62" y2="195.58" width="0.762" layer="92"/>
+<label x="134.62" y="198.12" size="1.778" layer="95"/>
 </segment>
 <segment>
 <wire x1="294.64" y1="195.58" x2="294.64" y2="114.3" width="0.762" layer="92"/>
-<label x="299.72" y="205.74" size="1.778" layer="95" rot="R270"/>
+<label x="294.64" y="198.12" size="1.778" layer="95"/>
+<wire x1="294.64" y1="195.58" x2="332.74" y2="195.58" width="0.762" layer="92"/>
 </segment>
 <segment>
-<wire x1="294.64" y1="43.18" x2="294.64" y2="-38.1" width="0.762" layer="92"/>
-<label x="299.72" y="55.88" size="1.778" layer="95" rot="R270"/>
+<wire x1="294.64" y1="35.56" x2="294.64" y2="20.32" width="0.762" layer="92"/>
+<label x="279.4" y="38.1" size="1.778" layer="95"/>
+<wire x1="294.64" y1="35.56" x2="317.5" y2="35.56" width="0.762" layer="92"/>
 </segment>
 <segment>
-<wire x1="-7.62" y1="185.42" x2="-7.62" y2="121.92" width="0.762" layer="92"/>
-<label x="-12.7" y="210.82" size="1.778" layer="95" rot="R270"/>
+<wire x1="-15.24" y1="187.96" x2="-15.24" y2="121.92" width="0.762" layer="92"/>
+<label x="-48.26" y="190.5" size="1.778" layer="95"/>
+<wire x1="-15.24" y1="187.96" x2="-48.26" y2="187.96" width="0.762" layer="92"/>
 </segment>
 <segment>
-<wire x1="116.84" y1="45.72" x2="116.84" y2="-35.56" width="0.762" layer="92"/>
+<wire x1="116.84" y1="38.1" x2="116.84" y2="-35.56" width="0.762" layer="92"/>
 </segment>
 <segment>
-<wire x1="-7.62" y1="45.72" x2="-7.62" y2="-35.56" width="0.762" layer="92"/>
-<label x="-12.7" y="55.88" size="1.778" layer="95" rot="R270"/>
-</segment>
-</bus>
-<bus name="FMC_A[20..21],DIGITIZED">
-<segment>
-<wire x1="7.62" y1="180.34" x2="7.62" y2="175.26" width="0.762" layer="92"/>
+<wire x1="-7.62" y1="-5.08" x2="-7.62" y2="-35.56" width="0.762" layer="92"/>
+<label x="-45.72" y="-33.02" size="1.778" layer="95"/>
+<wire x1="-7.62" y1="-35.56" x2="-45.72" y2="-35.56" width="0.762" layer="92"/>
 </segment>
 </bus>
 </busses>
@@ -37897,6 +38051,7 @@ available GPIO on the ARM</text>
 <junction x="449.58" y="139.7"/>
 <pinref part="P+11" gate="VCC" pin="VCC"/>
 <junction x="403.86" y="158.75"/>
+<label x="396.24" y="165.1" size="1.778" layer="95"/>
 </segment>
 <segment>
 <pinref part="U$1" gate="G$2" pin="VDD at 59"/>
@@ -38001,10 +38156,10 @@ available GPIO on the ARM</text>
 </segment>
 <segment>
 <pinref part="U$1" gate="G$1" pin="VREF+ at 41"/>
-<wire x1="96.52" y1="160.02" x2="104.14" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="96.52" y1="160.02" x2="124.46" y2="160.02" width="0.1524" layer="91"/>
 <pinref part="P+15" gate="VCC" pin="VCC"/>
-<wire x1="104.14" y1="163.83" x2="104.14" y2="160.02" width="0.1524" layer="91"/>
-<label x="106.68" y="165.1" size="1.778" layer="95"/>
+<wire x1="124.46" y1="163.83" x2="124.46" y2="160.02" width="0.1524" layer="91"/>
+<label x="127" y="165.1" size="1.778" layer="95"/>
 </segment>
 <segment>
 <pinref part="C16" gate="G$1" pin="1"/>
@@ -38030,17 +38185,17 @@ available GPIO on the ARM</text>
 </segment>
 <segment>
 <pinref part="U$1" gate="G$4" pin="PDR_ON at 203"/>
-<wire x1="269.24" y1="17.78" x2="274.32" y2="17.78" width="0.1524" layer="91"/>
-<wire x1="274.32" y1="17.78" x2="274.32" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="269.24" y1="17.78" x2="297.18" y2="17.78" width="0.1524" layer="91"/>
+<wire x1="297.18" y1="17.78" x2="297.18" y2="22.86" width="0.1524" layer="91"/>
 <pinref part="P+17" gate="VCC" pin="VCC"/>
-<label x="276.86" y="22.86" size="1.778" layer="95"/>
+<label x="299.72" y="22.86" size="1.778" layer="95"/>
 </segment>
 </net>
-<net name="FPGA_FMC_CLK" class="0">
+<net name="FMC_CLK" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD3/FMC_CLK"/>
-<wire x1="187.96" y1="10.16" x2="161.29" y2="10.16" width="0.1524" layer="91"/>
-<label x="161.29" y="10.16" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="10.16" x2="180.34" y2="10.16" width="0.1524" layer="91"/>
+<label x="180.34" y="10.16" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_D0" class="2">
@@ -38142,7 +38297,8 @@ available GPIO on the ARM</text>
 <net name="FMC_NL" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="FMC_NL/PB7"/>
-<wire x1="294.64" y1="0" x2="266.7" y2="0" width="0.1524" layer="91"/>
+<wire x1="274.32" y1="0" x2="266.7" y2="0" width="0.1524" layer="91"/>
+<label x="274.32" y="0" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_D28" class="2">
@@ -38160,97 +38316,88 @@ available GPIO on the ARM</text>
 <net name="FMC_D27" class="2">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PI3/FMC_D27"/>
-<wire x1="187.96" y1="35.56" x2="165.1" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="35.56" x2="144.78" y2="35.56" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_D3" class="2">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD1/FMC_D3"/>
-<wire x1="187.96" y1="15.24" x2="165.1" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="15.24" x2="144.78" y2="15.24" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_NOE" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD4/FMC_NOE"/>
-<wire x1="187.96" y1="7.62" x2="165.1" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="7.62" x2="180.34" y2="7.62" width="0.1524" layer="91"/>
+<label x="180.34" y="7.62" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NWE" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD5/FMC_NWE"/>
-<wire x1="187.96" y1="5.08" x2="165.1" y2="5.08" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="5.08" x2="180.34" y2="5.08" width="0.1524" layer="91"/>
+<label x="180.34" y="5.08" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NWAIT" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD6/FMC_NWAIT"/>
-<wire x1="187.96" y1="-2.54" x2="165.1" y2="-2.54" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="-2.54" x2="180.34" y2="-2.54" width="0.1524" layer="91"/>
+<label x="180.34" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_A19" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PE3/FMC_A19"/>
-<wire x1="15.24" y1="182.88" x2="-7.62" y2="182.88" width="0.1524" layer="91"/>
-</segment>
-</net>
-<net name="FMC_A20" class="0">
-<segment>
-<pinref part="U$1" gate="G$1" pin="PE4/FMC_A20"/>
-<wire x1="15.24" y1="180.34" x2="7.62" y2="180.34" width="0.1524" layer="91"/>
-</segment>
-</net>
-<net name="FMC_A21" class="0">
-<segment>
-<pinref part="U$1" gate="G$1" pin="PE5/FMC_A21"/>
-<wire x1="15.24" y1="177.8" x2="7.62" y2="177.8" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="182.88" x2="-15.24" y2="182.88" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_D30" class="2">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PI9/FMC_D30"/>
-<wire x1="15.24" y1="160.02" x2="-7.62" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="160.02" x2="-15.24" y2="160.02" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_D31" class="2">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PI10/FMC_D31"/>
-<wire x1="15.24" y1="157.48" x2="-7.62" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="157.48" x2="-15.24" y2="157.48" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A0" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF0/FMC_A0"/>
-<wire x1="15.24" y1="147.32" x2="-7.62" y2="147.32" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="147.32" x2="-15.24" y2="147.32" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A1" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF1/FMC_A1"/>
-<wire x1="15.24" y1="144.78" x2="-7.62" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="144.78" x2="-15.24" y2="144.78" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A2" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF2/FMC_A2"/>
-<wire x1="15.24" y1="142.24" x2="-7.62" y2="142.24" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="142.24" x2="-15.24" y2="142.24" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A3" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF3/FMC_A3"/>
-<wire x1="15.24" y1="132.08" x2="-7.62" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="132.08" x2="-15.24" y2="132.08" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A4" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF4/FMC_A4"/>
-<wire x1="15.24" y1="129.54" x2="-7.62" y2="129.54" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="129.54" x2="-15.24" y2="129.54" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A5" class="3">
 <segment>
 <pinref part="U$1" gate="G$1" pin="PF5/FMC_A5"/>
-<wire x1="15.24" y1="127" x2="-7.62" y2="127" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="127" x2="-15.24" y2="127" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_A6" class="3">
@@ -38388,13 +38535,14 @@ available GPIO on the ARM</text>
 <net name="FMC_D2" class="2">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD0/FMC_D2"/>
-<wire x1="187.96" y1="17.78" x2="165.1" y2="17.78" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="17.78" x2="144.78" y2="17.78" width="0.1524" layer="91"/>
 </segment>
 </net>
 <net name="FMC_NE1" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD7/FMC_NE1/FMC_NCE2"/>
-<wire x1="187.96" y1="-5.08" x2="165.1" y2="-5.08" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="-5.08" x2="180.34" y2="-5.08" width="0.1524" layer="91"/>
+<label x="180.34" y="-5.08" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="OSC_OUT" class="0">
@@ -38410,14 +38558,14 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$1" pin="OSC_OUT/PH1"/>
 <wire x1="93.98" y1="137.16" x2="104.14" y2="137.16" width="0.1524" layer="91"/>
-<label x="105.41" y="137.16" size="1.27" layer="95"/>
+<label x="97.79" y="137.16" size="1.27" layer="95"/>
 </segment>
 </net>
 <net name="OSC_IN" class="0">
 <segment>
 <pinref part="U$1" gate="G$1" pin="OSC_IN/PH0"/>
 <wire x1="93.98" y1="134.62" x2="104.14" y2="134.62" width="0.1524" layer="91"/>
-<label x="105.41" y="134.62" size="1.27" layer="95"/>
+<label x="97.79" y="134.62" size="1.27" layer="95"/>
 </segment>
 <segment>
 <pinref part="R12" gate="G$1" pin="1"/>
@@ -38445,8 +38593,8 @@ available GPIO on the ARM</text>
 </segment>
 <segment>
 <pinref part="U$1" gate="G$4" pin="PA14/JTCK-SWCLK"/>
-<wire x1="187.96" y1="30.48" x2="161.29" y2="30.48" width="0.1524" layer="91"/>
-<label x="160.02" y="30.48" size="1.27" layer="95" rot="R180"/>
+<wire x1="187.96" y1="30.48" x2="180.34" y2="30.48" width="0.1524" layer="91"/>
+<label x="180.34" y="30.48" size="1.27" layer="95" rot="R180"/>
 </segment>
 </net>
 <net name="NRST" class="0">
@@ -38461,7 +38609,7 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$1" pin="NRST at 34"/>
 <wire x1="96.52" y1="139.7" x2="104.14" y2="139.7" width="0.1524" layer="91"/>
-<label x="105.41" y="139.7" size="1.27" layer="95"/>
+<label x="100.33" y="139.7" size="1.27" layer="95"/>
 </segment>
 </net>
 <net name="VCAP2" class="0">
@@ -38526,7 +38674,7 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$2" pin="PJ4"/>
 <wire x1="15.24" y1="-2.54" x2="10.16" y2="-2.54" width="0.1524" layer="91"/>
-<label x="10.16" y="-2.54" size="1.27" layer="95" rot="R180"/>
+<label x="2.54" y="-2.54" size="1.27" layer="95"/>
 </segment>
 <segment>
 <wire x1="403.86" y1="-20.32" x2="398.78" y2="-20.32" width="0.1524" layer="91"/>
@@ -38538,7 +38686,7 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$2" pin="PJ3"/>
 <wire x1="15.24" y1="0" x2="10.16" y2="0" width="0.1524" layer="91"/>
-<label x="10.16" y="0" size="1.27" layer="95" rot="R180"/>
+<label x="2.54" y="0" size="1.27" layer="95"/>
 </segment>
 <segment>
 <wire x1="403.86" y1="-22.86" x2="398.78" y2="-22.86" width="0.1524" layer="91"/>
@@ -38550,7 +38698,7 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$2" pin="PJ2"/>
 <wire x1="15.24" y1="2.54" x2="10.16" y2="2.54" width="0.1524" layer="91"/>
-<label x="10.16" y="2.54" size="1.27" layer="95" rot="R180"/>
+<label x="2.54" y="2.54" size="1.27" layer="95"/>
 </segment>
 <segment>
 <wire x1="403.86" y1="-25.4" x2="398.78" y2="-25.4" width="0.1524" layer="91"/>
@@ -38562,7 +38710,7 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="U$1" gate="G$2" pin="PJ1"/>
 <wire x1="15.24" y1="5.08" x2="10.16" y2="5.08" width="0.1524" layer="91"/>
-<label x="10.16" y="5.08" size="1.27" layer="95" rot="R180"/>
+<label x="2.54" y="5.08" size="1.27" layer="95"/>
 </segment>
 <segment>
 <wire x1="403.86" y1="-27.94" x2="398.78" y2="-27.94" width="0.1524" layer="91"/>
@@ -38642,72 +38790,171 @@ available GPIO on the ARM</text>
 </net>
 <net name="FPGA_IRQ_N_0" class="0">
 <segment>
-<wire x1="187.96" y1="-25.4" x2="162.56" y2="-25.4" width="0.1524" layer="91"/>
-<label x="162.56" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-25.4" x2="180.34" y2="-25.4" width="0.1524" layer="91"/>
+<label x="180.34" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/>
 <pinref part="U$1" gate="G$4" pin="PG12/FMC_NE4"/>
 </segment>
 </net>
 <net name="FPGA_IRQ_N_1" class="0">
 <segment>
-<wire x1="187.96" y1="-22.86" x2="162.56" y2="-22.86" width="0.1524" layer="91"/>
-<label x="162.56" y="-22.86" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-22.86" x2="180.34" y2="-22.86" width="0.1524" layer="91"/>
+<label x="180.34" y="-22.86" size="1.27" layer="95" rot="R180" xref="yes"/>
 <pinref part="U$1" gate="G$4" pin="PG11/FMC_NCE4_2"/>
 </segment>
 </net>
 <net name="FPGA_IRQ_N_2" class="0">
 <segment>
-<wire x1="187.96" y1="-20.32" x2="162.56" y2="-20.32" width="0.1524" layer="91"/>
-<label x="162.56" y="-20.32" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-20.32" x2="180.34" y2="-20.32" width="0.1524" layer="91"/>
+<label x="180.34" y="-20.32" size="1.27" layer="95" rot="R180" xref="yes"/>
 <pinref part="U$1" gate="G$4" pin="PG10/FMC_NCE4_1/FMC_NE3"/>
 </segment>
 </net>
 <net name="FPGA_IRQ_N_3" class="0">
 <segment>
-<wire x1="187.96" y1="-17.78" x2="162.56" y2="-17.78" width="0.1524" layer="91"/>
-<label x="162.56" y="-17.78" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-17.78" x2="180.34" y2="-17.78" width="0.1524" layer="91"/>
+<label x="180.34" y="-17.78" size="1.27" layer="95" rot="R180" xref="yes"/>
 <pinref part="U$1" gate="G$4" pin="PG9/FMC_NE2/FMC_NCE3"/>
 </segment>
 </net>
 <net name="FPGA_PROGRAM_B" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PJ15"/>
-<wire x1="187.96" y1="-15.24" x2="162.56" y2="-15.24" width="0.1524" layer="91"/>
-<label x="162.56" y="-15.24" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-15.24" x2="180.34" y2="-15.24" width="0.1524" layer="91"/>
+<label x="180.34" y="-15.24" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="FPGA_INIT_B" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PJ14"/>
-<wire x1="187.96" y1="-12.7" x2="162.56" y2="-12.7" width="0.1524" layer="91"/>
-<label x="162.56" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="-12.7" x2="180.34" y2="-12.7" width="0.1524" layer="91"/>
+<label x="180.34" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="ARM_FPGA_CFG_SCLK" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PC10/SPI3_SCK"/>
-<wire x1="187.96" y1="25.4" x2="162.56" y2="25.4" width="0.1524" layer="91"/>
-<label x="162.56" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="25.4" x2="180.34" y2="25.4" width="0.1524" layer="91"/>
+<label x="180.34" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="ARM_FPGA_CFG_MISO" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PC11/SPI3_MISO"/>
-<wire x1="187.96" y1="22.86" x2="162.56" y2="22.86" width="0.1524" layer="91"/>
-<label x="162.56" y="22.86" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="22.86" x2="180.34" y2="22.86" width="0.1524" layer="91"/>
+<label x="180.34" y="22.86" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="ARM_FPGA_CFG_MOSI" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PC12/SPI3_MOSI"/>
-<wire x1="187.96" y1="20.32" x2="162.56" y2="20.32" width="0.1524" layer="91"/>
-<label x="162.56" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="20.32" x2="180.34" y2="20.32" width="0.1524" layer="91"/>
+<label x="180.34" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/>
 </segment>
 </net>
 <net name="ARM_FPGA_CFG_CONTROL" class="0">
 <segment>
 <pinref part="U$1" gate="G$4" pin="PD2"/>
-<wire x1="187.96" y1="12.7" x2="162.56" y2="12.7" width="0.1524" layer="91"/>
-<label x="162.56" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="187.96" y1="12.7" x2="180.34" y2="12.7" width="0.1524" layer="91"/>
+<label x="180.34" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_A20" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="PE4/FMC_A20"/>
+<wire x1="-15.24" y1="180.34" x2="15.24" y2="180.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A21" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="PE5/FMC_A21"/>
+<wire x1="-15.24" y1="177.8" x2="15.24" y2="177.8" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A22" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="PE6/FMC_A22"/>
+<wire x1="-15.24" y1="175.26" x2="15.24" y2="175.26" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A23" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="PE2/FMC_A23"/>
+<wire x1="-15.24" y1="185.42" x2="15.24" y2="185.42" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A24" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="PG13/FMC_A24"/>
+<wire x1="144.78" y1="-27.94" x2="187.96" y2="-27.94" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A25" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="PG14/FMC_A25"/>
+<wire x1="144.78" y1="-30.48" x2="187.96" y2="-30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_SDCKE0" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FMC_SDCKE0/PC3"/>
+<wire x1="93.98" y1="149.86" x2="104.14" y2="149.86" width="0.1524" layer="91"/>
+<label x="104.14" y="149.86" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNE0" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FMC_SDNE0/PC2"/>
+<wire x1="93.98" y1="147.32" x2="104.14" y2="147.32" width="0.1524" layer="91"/>
+<label x="104.14" y="147.32" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNWE" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FMC_SDNWE/PC0"/>
+<wire x1="93.98" y1="142.24" x2="104.14" y2="142.24" width="0.1524" layer="91"/>
+<label x="104.14" y="142.24" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNCAS" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="FMC_SDNCAS/PG15"/>
+<wire x1="266.7" y1="-12.7" x2="274.32" y2="-12.7" width="0.1524" layer="91"/>
+<label x="274.32" y="-12.7" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNRAS" class="0">
+<segment>
+<pinref part="U$1" gate="G$2" pin="PF11/FMC_SDNRAS"/>
+<wire x1="15.24" y1="-5.08" x2="10.16" y2="-5.08" width="0.1524" layer="91"/>
+<label x="10.16" y="-5.08" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL0" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="FMC_NBL0/PE0"/>
+<wire x1="266.7" y1="10.16" x2="274.32" y2="10.16" width="0.1524" layer="91"/>
+<label x="274.32" y="10.16" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL1" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="FMC_NBL1/PE1"/>
+<wire x1="266.7" y1="12.7" x2="274.32" y2="12.7" width="0.1524" layer="91"/>
+<label x="274.32" y="12.7" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL2" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="FMC_NBL2/PI4"/>
+<wire x1="266.7" y1="22.86" x2="274.32" y2="22.86" width="0.1524" layer="91"/>
+<label x="274.32" y="22.86" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL3" class="0">
+<segment>
+<pinref part="U$1" gate="G$4" pin="FMC_NBL3/PI5"/>
+<wire x1="266.7" y1="25.4" x2="274.32" y2="25.4" width="0.1524" layer="91"/>
+<label x="274.32" y="25.4" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 </nets>
@@ -38716,25 +38963,332 @@ available GPIO on the ARM</text>
 <description>SDRAM</description>
 <plain>
 <text x="58.42" y="15.24" size="2.54" layer="91">Another identical SRAM chip goes here</text>
+<text x="-167.64" y="-43.18" size="1.27" layer="91">XXX this shared for all FMC?</text>
 </plain>
 <instances>
 <instance part="FRAME22" gate="G$1" x="-193.04" y="-129.54"/>
 <instance part="IC1" gate="G$1" x="-96.52" y="10.16"/>
+<instance part="P+58" gate="VCC" x="-124.46" y="-72.39" smashed="yes"/>
+<instance part="SUPPLY214" gate="GND" x="-124.46" y="-111.76"/>
+<instance part="C194" gate="G$1" x="-99.06" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-99.06" y="-78.74" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C195" gate="G$1" x="-104.14" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-104.14" y="-78.74" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C196" gate="G$1" x="-109.22" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-109.22" y="-78.74" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C197" gate="G$1" x="-114.3" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-114.3" y="-78.74" size="1.27" layer="95" font="vector"/>
+<attribute name="DIELECTRIC" x="-114.3" y="-83.82" size="1.6764" layer="96" display="off"/>
+<attribute name="RATED_VOLTAGE" x="-114.3" y="-83.82" size="1.6764" layer="96" display="off"/>
+</instance>
+<instance part="C198" gate="G$1" x="-114.3" y="-96.52" smashed="yes">
+<attribute name="NAME" x="-116.84" y="-104.14" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C199" gate="G$1" x="-119.38" y="-96.52" smashed="yes">
+<attribute name="NAME" x="-121.92" y="-104.14" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C200" gate="G$1" x="-119.38" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-119.38" y="-78.74" size="1.27" layer="95" font="vector"/>
+<attribute name="RATED_VOLTAGE" x="-119.38" y="-83.82" size="1.6764" layer="96" display="off"/>
+</instance>
+<instance part="C201" gate="G$1" x="-124.46" y="-83.82" smashed="yes">
+<attribute name="NAME" x="-124.46" y="-78.74" size="1.27" layer="95" font="vector"/>
+<attribute name="DIELECTRIC" x="-124.46" y="-83.82" size="1.6764" layer="96" display="off"/>
+<attribute name="RATED_VOLTAGE" x="-124.46" y="-83.82" size="1.6764" layer="96" display="off"/>
+</instance>
+<instance part="C206" gate="G$1" x="-99.06" y="-96.52" smashed="yes">
+<attribute name="NAME" x="-101.6" y="-104.14" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C207" gate="G$1" x="-104.14" y="-96.52" smashed="yes">
+<attribute name="NAME" x="-106.68" y="-104.14" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="C208" gate="G$1" x="-109.22" y="-96.52" smashed="yes">
+<attribute name="NAME" x="-111.76" y="-104.14" size="1.27" layer="95" font="vector"/>
+</instance>
+<instance part="P+59" gate="VCC" x="-111.76" y="77.47" smashed="yes"/>
+<instance part="P+60" gate="VCC" x="-99.06" y="77.47" smashed="yes"/>
+<instance part="SUPPLY215" gate="GND" x="-96.52" y="-58.42"/>
 </instances>
 <busses>
-<bus name="FMC_D[0..31],FMC_A[0..19],FMC_NE1,FMC_NOE,FMC_NWE,FMC_NL,FMC_NWAIT">
+<bus name="FMC_A[0..25]">
 <segment>
-<wire x1="-50.8" y1="63.5" x2="-50.8" y2="-20.32" width="0.762" layer="92"/>
-<label x="-45.72" y="-12.7" size="1.27" layer="95" rot="R90"/>
+<wire x1="-142.24" y1="66.04" x2="-156.21" y2="66.04" width="0.762" layer="92"/>
+<wire x1="-142.24" y1="66.04" x2="-142.24" y2="17.78" width="0.762" layer="92"/>
+<label x="-158.75" y="68.58" size="1.778" layer="95"/>
+</segment>
+</bus>
+<bus name="FMC_D[0..31]">
+<segment>
+<wire x1="-50.8" y1="-17.78" x2="-50.8" y2="66.04" width="0.762" layer="92"/>
+<wire x1="-50.8" y1="66.04" x2="-35.56" y2="66.04" width="0.762" layer="92"/>
+<label x="-50.8" y="66.04" size="1.778" layer="95"/>
 </segment>
 </bus>
 </busses>
 <nets>
+<net name="GND" class="1">
+<segment>
+<pinref part="C201" gate="G$1" pin="2"/>
+<pinref part="SUPPLY214" gate="GND" pin="GND"/>
+<wire x1="-99.06" y1="-88.9" x2="-104.14" y2="-88.9" width="0.1524" layer="91"/>
+<wire x1="-104.14" y1="-88.9" x2="-109.22" y2="-88.9" width="0.1524" layer="91"/>
+<wire x1="-109.22" y1="-88.9" x2="-114.3" y2="-88.9" width="0.1524" layer="91"/>
+<wire x1="-114.3" y1="-88.9" x2="-119.38" y2="-88.9" width="0.1524" layer="91"/>
+<wire x1="-119.38" y1="-88.9" x2="-124.46" y2="-88.9" width="0.1524" layer="91"/>
+<wire x1="-124.46" y1="-88.9" x2="-124.46" y2="-101.6" width="0.1524" layer="91"/>
+<junction x="-124.46" y="-88.9"/>
+<wire x1="-124.46" y1="-101.6" x2="-124.46" y2="-109.22" width="0.1524" layer="91"/>
+<junction x="-124.46" y="-101.6"/>
+<pinref part="C194" gate="G$1" pin="2"/>
+<pinref part="C195" gate="G$1" pin="2"/>
+<junction x="-104.14" y="-88.9"/>
+<pinref part="C196" gate="G$1" pin="2"/>
+<junction x="-109.22" y="-88.9"/>
+<pinref part="C197" gate="G$1" pin="2"/>
+<junction x="-114.3" y="-88.9"/>
+<pinref part="C200" gate="G$1" pin="2"/>
+<junction x="-119.38" y="-88.9"/>
+<pinref part="C206" gate="G$1" pin="2"/>
+<wire x1="-99.06" y1="-101.6" x2="-104.14" y2="-101.6" width="0.1524" layer="91"/>
+<pinref part="C207" gate="G$1" pin="2"/>
+<junction x="-104.14" y="-101.6"/>
+<wire x1="-104.14" y1="-101.6" x2="-109.22" y2="-101.6" width="0.1524" layer="91"/>
+<pinref part="C208" gate="G$1" pin="2"/>
+<junction x="-109.22" y="-101.6"/>
+<wire x1="-109.22" y1="-101.6" x2="-114.3" y2="-101.6" width="0.1524" layer="91"/>
+<pinref part="C198" gate="G$1" pin="2"/>
+<junction x="-114.3" y="-101.6"/>
+<wire x1="-114.3" y1="-101.6" x2="-119.38" y2="-101.6" width="0.1524" layer="91"/>
+<pinref part="C199" gate="G$1" pin="2"/>
+<junction x="-119.38" y="-101.6"/>
+<wire x1="-119.38" y1="-101.6" x2="-124.46" y2="-101.6" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="VSS at 86"/>
+<wire x1="-81.28" y1="-48.26" x2="-81.28" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-81.28" y1="-53.34" x2="-83.82" y2="-53.34" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 6"/>
+<wire x1="-83.82" y1="-53.34" x2="-86.36" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-86.36" y1="-53.34" x2="-88.9" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-88.9" y1="-53.34" x2="-93.98" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-93.98" y1="-53.34" x2="-96.52" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-96.52" y1="-53.34" x2="-99.06" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-99.06" y1="-53.34" x2="-101.6" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-101.6" y1="-53.34" x2="-104.14" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-104.14" y1="-53.34" x2="-106.68" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-106.68" y1="-53.34" x2="-109.22" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-109.22" y1="-53.34" x2="-111.76" y2="-53.34" width="0.1524" layer="91"/>
+<wire x1="-111.76" y1="-53.34" x2="-111.76" y2="-48.26" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 12"/>
+<wire x1="-109.22" y1="-48.26" x2="-109.22" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-109.22" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 32"/>
+<wire x1="-106.68" y1="-48.26" x2="-106.68" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-106.68" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 38"/>
+<wire x1="-104.14" y1="-48.26" x2="-104.14" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-104.14" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 46"/>
+<wire x1="-101.6" y1="-48.26" x2="-101.6" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-101.6" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 52"/>
+<wire x1="-99.06" y1="-48.26" x2="-99.06" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-99.06" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 78"/>
+<wire x1="-96.52" y1="-48.26" x2="-96.52" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-96.52" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSSQ at 84"/>
+<wire x1="-93.98" y1="-48.26" x2="-93.98" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-93.98" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSS at 44"/>
+<wire x1="-88.9" y1="-48.26" x2="-88.9" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-88.9" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSS at 58"/>
+<wire x1="-86.36" y1="-48.26" x2="-86.36" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-86.36" y="-53.34"/>
+<pinref part="IC1" gate="G$1" pin="VSS at 72"/>
+<wire x1="-83.82" y1="-48.26" x2="-83.82" y2="-53.34" width="0.1524" layer="91"/>
+<junction x="-83.82" y="-53.34"/>
+<pinref part="SUPPLY215" gate="GND" pin="GND"/>
+<wire x1="-96.52" y1="-55.88" x2="-96.52" y2="-53.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="VCCO_3V3" class="0">
+<segment>
+<pinref part="C201" gate="G$1" pin="1"/>
+<wire x1="-124.46" y1="-76.2" x2="-124.46" y2="-74.93" width="0.1524" layer="91"/>
+<pinref part="P+58" gate="VCC" pin="VCC"/>
+<wire x1="-124.46" y1="-74.93" x2="-124.46" y2="-81.28" width="0.1524" layer="91"/>
+<junction x="-124.46" y="-81.28"/>
+<wire x1="-124.46" y1="-81.28" x2="-119.38" y2="-81.28" width="0.1524" layer="91"/>
+<pinref part="C200" gate="G$1" pin="1"/>
+<junction x="-119.38" y="-81.28"/>
+<wire x1="-119.38" y1="-81.28" x2="-114.3" y2="-81.28" width="0.1524" layer="91"/>
+<pinref part="C197" gate="G$1" pin="1"/>
+<junction x="-114.3" y="-81.28"/>
+<wire x1="-114.3" y1="-81.28" x2="-109.22" y2="-81.28" width="0.1524" layer="91"/>
+<pinref part="C196" gate="G$1" pin="1"/>
+<junction x="-109.22" y="-81.28"/>
+<wire x1="-109.22" y1="-81.28" x2="-104.14" y2="-81.28" width="0.1524" layer="91"/>
+<pinref part="C195" gate="G$1" pin="1"/>
+<junction x="-104.14" y="-81.28"/>
+<wire x1="-104.14" y1="-81.28" x2="-99.06" y2="-81.28" width="0.1524" layer="91"/>
+<pinref part="C194" gate="G$1" pin="1"/>
+<wire x1="-99.06" y1="-81.28" x2="-93.98" y2="-81.28" width="0.1524" layer="91"/>
+<wire x1="-93.98" y1="-81.28" x2="-93.98" y2="-93.98" width="0.1524" layer="91"/>
+<junction x="-99.06" y="-81.28"/>
+<pinref part="C199" gate="G$1" pin="1"/>
+<pinref part="C198" gate="G$1" pin="1"/>
+<junction x="-114.3" y="-93.98"/>
+<wire x1="-99.06" y1="-93.98" x2="-104.14" y2="-93.98" width="0.1524" layer="91"/>
+<wire x1="-104.14" y1="-93.98" x2="-109.22" y2="-93.98" width="0.1524" layer="91"/>
+<wire x1="-109.22" y1="-93.98" x2="-114.3" y2="-93.98" width="0.1524" layer="91"/>
+<wire x1="-114.3" y1="-93.98" x2="-119.38" y2="-93.98" width="0.1524" layer="91"/>
+<pinref part="C208" gate="G$1" pin="1"/>
+<junction x="-109.22" y="-93.98"/>
+<pinref part="C207" gate="G$1" pin="1"/>
+<junction x="-104.14" y="-93.98"/>
+<pinref part="C206" gate="G$1" pin="1"/>
+<wire x1="-93.98" y1="-93.98" x2="-99.06" y2="-93.98" width="0.1524" layer="91"/>
+<junction x="-99.06" y="-93.98"/>
+<label x="-139.7" y="-76.2" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="-111.76" y1="73.66" x2="-111.76" y2="74.93" width="0.1524" layer="91"/>
+<pinref part="P+59" gate="VCC" pin="VCC"/>
+<wire x1="-111.76" y1="74.93" x2="-111.76" y2="71.12" width="0.1524" layer="91"/>
+<label x="-127" y="73.66" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="VDD at 43"/>
+<wire x1="-111.76" y1="71.12" x2="-111.76" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="-111.76" y1="71.12" x2="-109.22" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-109.22" y1="71.12" x2="-106.68" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-106.68" y1="71.12" x2="-104.14" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-104.14" y1="71.12" x2="-104.14" y2="68.58" width="0.1524" layer="91"/>
+<junction x="-111.76" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDD at 29"/>
+<wire x1="-106.68" y1="68.58" x2="-106.68" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-106.68" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDD at 15"/>
+<wire x1="-109.22" y1="68.58" x2="-109.22" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-109.22" y="71.12"/>
+</segment>
+<segment>
+<wire x1="-99.06" y1="73.66" x2="-99.06" y2="74.93" width="0.1524" layer="91"/>
+<pinref part="P+60" gate="VCC" pin="VCC"/>
+<wire x1="-99.06" y1="74.93" x2="-99.06" y2="71.12" width="0.1524" layer="91"/>
+<label x="-96.52" y="73.66" size="1.778" layer="95"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 81"/>
+<wire x1="-99.06" y1="71.12" x2="-99.06" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="-99.06" y1="71.12" x2="-96.52" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-96.52" y1="71.12" x2="-93.98" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-93.98" y1="71.12" x2="-91.44" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-91.44" y1="71.12" x2="-88.9" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-88.9" y1="71.12" x2="-86.36" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-86.36" y1="71.12" x2="-83.82" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="-83.82" y1="71.12" x2="-83.82" y2="68.58" width="0.1524" layer="91"/>
+<junction x="-99.06" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 75"/>
+<wire x1="-86.36" y1="68.58" x2="-86.36" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-86.36" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 55"/>
+<wire x1="-88.9" y1="68.58" x2="-88.9" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-88.9" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 49"/>
+<wire x1="-91.44" y1="68.58" x2="-91.44" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-91.44" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 41"/>
+<wire x1="-93.98" y1="68.58" x2="-93.98" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-93.98" y="71.12"/>
+<pinref part="IC1" gate="G$1" pin="VDDQ at 35"/>
+<wire x1="-96.52" y1="68.58" x2="-96.52" y2="71.12" width="0.1524" layer="91"/>
+<junction x="-96.52" y="71.12"/>
+</segment>
+</net>
+<net name="FMC_A0" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A0"/>
+<wire x1="-142.24" y1="60.96" x2="-127" y2="60.96" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A1" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A1"/>
+<wire x1="-142.24" y1="58.42" x2="-127" y2="58.42" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A2" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A2"/>
+<wire x1="-142.24" y1="55.88" x2="-127" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A3" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A3"/>
+<wire x1="-142.24" y1="53.34" x2="-127" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A4" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A4"/>
+<wire x1="-142.24" y1="50.8" x2="-127" y2="50.8" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A5" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A5"/>
+<wire x1="-142.24" y1="48.26" x2="-127" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A6" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A6"/>
+<wire x1="-142.24" y1="45.72" x2="-127" y2="45.72" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A7" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A7"/>
+<wire x1="-142.24" y1="43.18" x2="-127" y2="43.18" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A8" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A8"/>
+<wire x1="-142.24" y1="40.64" x2="-127" y2="40.64" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A9" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A9"/>
+<wire x1="-142.24" y1="38.1" x2="-127" y2="38.1" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A10" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A10"/>
+<wire x1="-142.24" y1="35.56" x2="-127" y2="35.56" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A11" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A11"/>
+<wire x1="-142.24" y1="33.02" x2="-127" y2="33.02" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FMC_A12" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A12"/>
+<wire x1="-142.24" y1="30.48" x2="-127" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
 <net name="FMC_D0" class="2">
 <segment>
 <pinref part="IC1" gate="G$1" pin="DQ0"/>
 <wire x1="-50.8" y1="60.96" x2="-66.04" y2="60.96" width="0.1524" layer="91"/>
-<label x="-48.26" y="60.96" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_D1" class="2">
@@ -38785,13 +39339,11 @@ available GPIO on the ARM</text>
 <wire x1="-50.8" y1="40.64" x2="-66.04" y2="40.64" width="0.1524" layer="91"/>
 </segment>
 </net>
-<net name="FMC_D9" class="2">
+<net name="FMC_D10" class="2">
 <segment>
 <pinref part="IC1" gate="G$1" pin="DQ9"/>
 <wire x1="-50.8" y1="38.1" x2="-66.04" y2="38.1" width="0.1524" layer="91"/>
 </segment>
-</net>
-<net name="FMC_D10" class="2">
 <segment>
 <pinref part="IC1" gate="G$1" pin="DQ10"/>
 <wire x1="-50.8" y1="35.56" x2="-66.04" y2="35.56" width="0.1524" layer="91"/>
@@ -38844,6 +39396,8 @@ available GPIO on the ARM</text>
 <pinref part="IC1" gate="G$1" pin="DQ18"/>
 <wire x1="-50.8" y1="15.24" x2="-66.04" y2="15.24" width="0.1524" layer="91"/>
 </segment>
+</net>
+<net name="FMC_D19" class="2">
 <segment>
 <pinref part="IC1" gate="G$1" pin="DQ19"/>
 <wire x1="-50.8" y1="12.7" x2="-66.04" y2="12.7" width="0.1524" layer="91"/>
@@ -38919,7 +39473,90 @@ available GPIO on the ARM</text>
 <segment>
 <pinref part="IC1" gate="G$1" pin="DQ31"/>
 <wire x1="-50.8" y1="-17.78" x2="-66.04" y2="-17.78" width="0.1524" layer="91"/>
-<label x="-48.26" y="-17.78" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDCKE0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="CKE"/>
+<wire x1="-127" y1="-12.7" x2="-142.24" y2="-12.7" width="0.1524" layer="91"/>
+<label x="-142.24" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_CLK" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="CLK"/>
+<wire x1="-127" y1="0" x2="-142.24" y2="0" width="0.1524" layer="91"/>
+<label x="-142.24" y="0" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNE0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!CS"/>
+<wire x1="-127" y1="-25.4" x2="-142.24" y2="-25.4" width="0.1524" layer="91"/>
+<label x="-142.24" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNWE" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!WE"/>
+<wire x1="-127" y1="-38.1" x2="-142.24" y2="-38.1" width="0.1524" layer="91"/>
+<label x="-142.24" y="-38.1" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNCAS" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!CAS"/>
+<wire x1="-127" y1="15.24" x2="-142.24" y2="15.24" width="0.1524" layer="91"/>
+<label x="-142.24" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_SDNRAS" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!RAS"/>
+<wire x1="-127" y1="12.7" x2="-142.24" y2="12.7" width="0.1524" layer="91"/>
+<label x="-142.24" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_A14" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="BA0"/>
+<wire x1="-142.24" y1="22.86" x2="-127" y2="22.86" width="0.1524" layer="91"/>
+<label x="-139.7" y="22.86" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="FMC_A15" class="3">
+<segment>
+<pinref part="IC1" gate="G$1" pin="BA1"/>
+<wire x1="-142.24" y1="20.32" x2="-127" y2="20.32" width="0.1524" layer="91"/>
+<label x="-139.7" y="20.32" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="FMC_NBL0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="DQM0"/>
+<wire x1="-66.04" y1="-22.86" x2="-50.8" y2="-22.86" width="0.1524" layer="91"/>
+<label x="-50.8" y="-22.86" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL1" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="DQM1"/>
+<wire x1="-66.04" y1="-25.4" x2="-50.8" y2="-25.4" width="0.1524" layer="91"/>
+<label x="-50.8" y="-25.4" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL2" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="DQM2"/>
+<wire x1="-66.04" y1="-27.94" x2="-50.8" y2="-27.94" width="0.1524" layer="91"/>
+<label x="-50.8" y="-27.94" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FMC_NBL3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="DQM3"/>
+<wire x1="-66.04" y1="-30.48" x2="-50.8" y2="-30.48" width="0.1524" layer="91"/>
+<label x="-50.8" y="-30.48" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 </nets>
@@ -39664,6 +40301,566 @@ This requirement also applies to using our own USB VID/PID.
 </nets>
 </sheet>
 <sheet>
+<description>MGMT USB-UART interface</description>
+<plain>
+<text x="-73.66" y="68.58" size="1.778" layer="91">DS_FT232H.pdf
+6.1 USB Bus Powered Configuration
+copy of reference circuit</text>
+<text x="-3.81" y="-46.99" size="1.27" layer="91">Place close to FT232</text>
+<text x="-45.72" y="2.54" size="1.778" layer="91">CL 10pF</text>
+</plain>
+<instances>
+<instance part="U$10" gate="G$1" x="12.7" y="22.86"/>
+<instance part="R69" gate="G$1" x="-22.86" y="30.48" rot="R180"/>
+<instance part="C9" gate="G$1" x="-43.18" y="35.56" smashed="yes">
+<attribute name="NAME" x="-50.8" y="40.64" size="1.6764" layer="95" rot="R180"/>
+</instance>
+<instance part="C10" gate="G$1" x="-48.26" y="35.56" smashed="yes">
+<attribute name="NAME" x="-50.8" y="38.1" size="1.6764" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-50.8" y="35.56" size="1.6764" layer="96" rot="R180"/>
+</instance>
+<instance part="SUPPLY15" gate="GND" x="-45.72" y="20.32"/>
+<instance part="SUPPLY16" gate="GND" x="15.24" y="-20.32"/>
+<instance part="R70" gate="G$1" x="-33.02" y="25.4" smashed="yes" rot="R180">
+<attribute name="NAME" x="-36.83" y="20.5486" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-38.1" y="17.78" size="1.778" layer="96"/>
+<attribute name="TOLERANCE" x="-30.48" y="17.78" size="1.6764" layer="96"/>
+</instance>
+<instance part="R71" gate="G$1" x="50.8" y="22.86" smashed="yes" rot="R180">
+<attribute name="NAME" x="53.34" y="17.78" size="1.778" layer="95" rot="R180"/>
+<attribute name="VALUE" x="53.34" y="12.7" size="1.778" layer="96" rot="R180"/>
+</instance>
+<instance part="R72" gate="G$1" x="50.8" y="20.32" smashed="yes" rot="R180">
+<attribute name="NAME" x="53.34" y="15.24" size="1.778" layer="95" rot="R180"/>
+</instance>
+<instance part="LED17" gate="G$1" x="71.12" y="30.48" smashed="yes" rot="MR0">
+<attribute name="NAME" x="63.5" y="27.94" size="1.778" layer="95" rot="MR90"/>
+<attribute name="VALUE" x="66.04" y="27.94" size="1.778" layer="96" rot="MR90"/>
+</instance>
+<instance part="LED18" gate="G$1" x="76.2" y="30.48" smashed="yes" rot="MR0">
+<attribute name="NAME" x="81.28" y="27.94" size="1.778" layer="95" rot="MR90"/>
+<attribute name="VALUE" x="83.82" y="27.94" size="1.778" layer="96" rot="MR90"/>
+</instance>
+<instance part="SUPPLY17" gate="GND" x="-15.24" y="-20.32"/>
+<instance part="C11" gate="G$1" x="-33.02" y="-10.16" smashed="yes" rot="R180">
+<attribute name="NAME" x="-43.18" y="-15.24" size="1.778" layer="95"/>
+<attribute name="DIELECTRIC" x="-33.02" y="-10.16" size="1.778" layer="96" rot="R180" display="off"/>
+<attribute name="RATED_VOLTAGE" x="-33.02" y="-10.16" size="1.778" layer="96" rot="R180" display="off"/>
+</instance>
+<instance part="C12" gate="G$1" x="-48.26" y="-10.16" smashed="yes" rot="R180">
+<attribute name="NAME" x="-43.18" y="-12.7" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-43.18" y="-17.78" size="1.778" layer="96"/>
+<attribute name="DIELECTRIC" x="-43.18" y="-20.32" size="1.778" layer="96"/>
+<attribute name="RATED_VOLTAGE" x="-48.26" y="-10.16" size="1.778" layer="96" rot="R180" display="off"/>
+</instance>
+<instance part="SUPPLY32" gate="GND" x="-48.26" y="-20.32"/>
+<instance part="SUPPLY58" gate="GND" x="-33.02" y="-20.32"/>
+<instance part="FT_VCC3V1" gate="VCC" x="15.24" y="78.74" smashed="yes"/>
+<instance part="FT_VCC3V3_10" gate="VCC" x="73.66" y="45.72" smashed="yes"/>
+<instance part="C179" gate="G$1" x="-83.82" y="-63.5" smashed="yes">
+<attribute name="NAME" x="-86.36" y="-59.69" size="1.6764" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-86.36" y="-62.23" size="1.6764" layer="96" rot="R180"/>
+<attribute name="DIELECTRIC" x="-83.82" y="-63.5" size="1.6764" layer="96" display="off"/>
+<attribute name="RATED_VOLTAGE" x="-83.82" y="-63.5" size="1.6764" layer="96" display="off"/>
+</instance>
+<instance part="C180" gate="G$1" x="-76.2" y="-63.5" smashed="yes">
+<attribute name="NAME" x="-73.66" y="-60.96" size="1.6764" layer="95"/>
+<attribute name="VALUE" x="-73.66" y="-63.5" size="1.6764" layer="96"/>
+<attribute name="DIELECTRIC" x="-76.2" y="-63.5" size="1.6764" layer="96" display="off"/>
+<attribute name="RATED_VOLTAGE" x="-76.2" y="-63.5" size="1.6764" layer="96" display="off"/>
+</instance>
+<instance part="SUPPLY186" gate="GND" x="-76.2" y="-76.2"/>
+<instance part="C181" gate="G$1" x="48.26" y="-63.5" smashed="yes">
+<attribute name="NAME" x="45.72" y="-59.69" size="1.6764" layer="95" rot="R180"/>
+<attribute name="VALUE" x="45.72" y="-62.23" size="1.6764" layer="96" rot="R180"/>
+</instance>
+<instance part="C182" gate="G$1" x="55.88" y="-63.5" smashed="yes">
+<attribute name="NAME" x="58.42" y="-60.96" size="1.6764" layer="95"/>
+<attribute name="VALUE" x="58.42" y="-63.5" size="1.6764" layer="96"/>
+</instance>
+<instance part="SUPPLY187" gate="GND" x="55.88" y="-76.2"/>
+<instance part="C183" gate="G$1" x="-25.4" y="-63.5" smashed="yes">
+<attribute name="NAME" x="-22.86" y="-66.04" size="1.6764" layer="95"/>
+<attribute name="VALUE" x="-22.86" y="-68.58" size="1.6764" layer="96"/>
+</instance>
+<instance part="C184" gate="G$1" x="-38.1" y="-63.5" smashed="yes">
+<attribute name="NAME" x="-40.64" y="-64.77" size="1.6764" layer="95" rot="R180"/>
+<attribute name="VALUE" x="-40.64" y="-67.31" size="1.6764" layer="96" rot="R180"/>
+</instance>
+<instance part="SUPPLY188" gate="GND" x="-25.4" y="-76.2"/>
+<instance part="C185" gate="G$1" x="20.32" y="-63.5" smashed="yes">
+<attribute name="NAME" x="22.86" y="-66.04" size="1.6764" layer="95"/>
+<attribute name="VALUE" x="22.86" y="-68.58" size="1.6764" layer="96"/>
+</instance>
+<instance part="C186" gate="G$1" x="7.62" y="-63.5" smashed="yes">
+<attribute name="NAME" x="5.08" y="-63.5" size="1.6764" layer="95" rot="R180"/>
+<attribute name="VALUE" x="5.08" y="-66.04" size="1.6764" layer="96" rot="R180"/>
+</instance>
+<instance part="SUPPLY199" gate="GND" x="20.32" y="-76.2"/>
+<instance part="C187" gate="G$1" x="76.2" y="-63.5" smashed="yes">
+<attribute name="NAME" x="91.44" y="-60.96" size="1.6764" layer="95"/>
+</instance>
+<instance part="C188" gate="G$1" x="81.28" y="-63.5" smashed="yes">
+<attribute name="NAME" x="91.44" y="-63.5" size="1.6764" layer="95"/>
+</instance>
+<instance part="C189" gate="G$1" x="86.36" y="-63.5" smashed="yes">
+<attribute name="NAME" x="91.44" y="-66.04" size="1.6764" layer="95"/>
+<attribute name="VALUE" x="91.44" y="-68.58" size="1.6764" layer="96"/>
+</instance>
+<instance part="SUPPLY212" gate="GND" x="81.28" y="-76.2"/>
+<instance part="FT_VCC3V3_11" gate="VCC" x="81.28" y="-43.18" smashed="yes"/>
+<instance part="FB3" gate="G$1" x="0" y="-55.88"/>
+<instance part="FB4" gate="G$1" x="-45.72" y="-55.88"/>
+<instance part="CN2" gate="G$1" x="-100.33" y="50.8"/>
+<instance part="SUPPLY213" gate="GND" x="-87.63" y="39.37"/>
+<instance part="Y2" gate="G$1" x="-40.64" y="-2.54" smashed="yes">
+<attribute name="NAME" x="-41.91" y="0" size="1.778" layer="95"/>
+<attribute name="VALUE" x="-44.45" y="-6.35" size="1.27" layer="96"/>
+<attribute name="TOLERANCE" x="-44.45" y="-8.89" size="1.27" layer="96" display="off"/>
+<attribute name="MPN" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/>
+<attribute name="OC_FARNELL" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/>
+<attribute name="SUPPLIER" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/>
+</instance>
+<instance part="FRAME24" gate="G$1" x="-193.04" y="-129.54"/>
+<instance part="FT_VCC3V3_12" gate="VCC" x="48.26" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_13" gate="VCC" x="48.26" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_14" gate="VCC" x="-83.82" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_15" gate="VCC" x="-50.8" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_16" gate="VCC" x="-25.4" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_17" gate="VCC" x="-5.08" y="-43.18" smashed="yes"/>
+<instance part="FT_VCC3V3_18" gate="VCC" x="20.32" y="-43.18" smashed="yes"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="GND" class="1">
+<segment>
+<pinref part="C9" gate="G$1" pin="2"/>
+<pinref part="SUPPLY15" gate="GND" pin="GND"/>
+<wire x1="-43.18" y1="30.48" x2="-43.18" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="-43.18" y1="25.4" x2="-43.18" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="-43.18" y1="22.86" x2="-45.72" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="-45.72" y1="22.86" x2="-48.26" y2="22.86" width="0.1524" layer="91"/>
+<junction x="-45.72" y="22.86"/>
+<pinref part="C10" gate="G$1" pin="2"/>
+<wire x1="-48.26" y1="22.86" x2="-48.26" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="R70" gate="G$1" pin="2"/>
+<wire x1="-38.1" y1="25.4" x2="-43.18" y2="25.4" width="0.1524" layer="91"/>
+<junction x="-43.18" y="25.4"/>
+</segment>
+<segment>
+<pinref part="U$10" gate="G$1" pin="GND at 48"/>
+<wire x1="27.94" y1="-15.24" x2="27.94" y2="-17.78" width="0.1524" layer="91"/>
+<pinref part="SUPPLY16" gate="GND" pin="GND"/>
+<wire x1="27.94" y1="-17.78" x2="25.4" y2="-17.78" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="AGND at 4"/>
+<wire x1="25.4" y1="-17.78" x2="22.86" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="-17.78" x2="20.32" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="-17.78" x2="17.78" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="-17.78" x2="15.24" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="2.54" y1="-15.24" x2="2.54" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="2.54" y1="-17.78" x2="5.08" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="15.24" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="AGND at 9"/>
+<wire x1="5.08" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="-17.78" x2="10.16" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="10.16" y1="-17.78" x2="12.7" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="12.7" y1="-17.78" x2="15.24" y2="-17.78" width="0.1524" layer="91"/>
+<wire x1="5.08" y1="-15.24" x2="5.08" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="5.08" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="AGND at 41"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="7.62" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 10"/>
+<wire x1="10.16" y1="-15.24" x2="10.16" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="10.16" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 11"/>
+<wire x1="12.7" y1="-15.24" x2="12.7" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="12.7" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 22"/>
+<wire x1="15.24" y1="-15.24" x2="15.24" y2="-17.78" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="GND at 23"/>
+<wire x1="17.78" y1="-15.24" x2="17.78" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="17.78" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 35"/>
+<wire x1="20.32" y1="-15.24" x2="20.32" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="20.32" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 36"/>
+<wire x1="22.86" y1="-15.24" x2="22.86" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="22.86" y="-17.78"/>
+<pinref part="U$10" gate="G$1" pin="GND at 47"/>
+<wire x1="25.4" y1="-15.24" x2="25.4" y2="-17.78" width="0.1524" layer="91"/>
+<junction x="25.4" y="-17.78"/>
+</segment>
+<segment>
+<pinref part="U$10" gate="G$1" pin="TEST"/>
+<pinref part="SUPPLY17" gate="GND" pin="GND"/>
+<wire x1="-15.24" y1="-7.62" x2="-15.24" y2="-17.78" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C12" gate="G$1" pin="1"/>
+<wire x1="-48.26" y1="-12.7" x2="-48.26" y2="-17.78" width="0.1524" layer="91"/>
+<pinref part="SUPPLY32" gate="GND" pin="GND"/>
+</segment>
+<segment>
+<wire x1="-33.02" y1="-12.7" x2="-33.02" y2="-17.78" width="0.1524" layer="91"/>
+<pinref part="SUPPLY58" gate="GND" pin="GND"/>
+<pinref part="C11" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="SUPPLY186" gate="GND" pin="GND"/>
+<pinref part="C180" gate="G$1" pin="2"/>
+<wire x1="-76.2" y1="-68.58" x2="-76.2" y2="-71.12" width="0.1524" layer="91"/>
+<pinref part="C179" gate="G$1" pin="2"/>
+<wire x1="-76.2" y1="-71.12" x2="-76.2" y2="-73.66" width="0.1524" layer="91"/>
+<wire x1="-83.82" y1="-68.58" x2="-83.82" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="-83.82" y1="-71.12" x2="-76.2" y2="-71.12" width="0.1524" layer="91"/>
+<junction x="-76.2" y="-71.12"/>
+</segment>
+<segment>
+<pinref part="SUPPLY187" gate="GND" pin="GND"/>
+<pinref part="C182" gate="G$1" pin="2"/>
+<wire x1="55.88" y1="-68.58" x2="55.88" y2="-71.12" width="0.1524" layer="91"/>
+<pinref part="C181" gate="G$1" pin="2"/>
+<wire x1="55.88" y1="-71.12" x2="55.88" y2="-73.66" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="-68.58" x2="48.26" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="48.26" y1="-71.12" x2="55.88" y2="-71.12" width="0.1524" layer="91"/>
+<junction x="55.88" y="-71.12"/>
+</segment>
+<segment>
+<pinref part="C183" gate="G$1" pin="2"/>
+<pinref part="SUPPLY188" gate="GND" pin="GND"/>
+<wire x1="-25.4" y1="-68.58" x2="-25.4" y2="-71.12" width="0.1524" layer="91"/>
+<pinref part="C184" gate="G$1" pin="2"/>
+<wire x1="-25.4" y1="-71.12" x2="-25.4" y2="-73.66" width="0.1524" layer="91"/>
+<wire x1="-38.1" y1="-68.58" x2="-38.1" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="-38.1" y1="-71.12" x2="-25.4" y2="-71.12" width="0.1524" layer="91"/>
+<junction x="-25.4" y="-71.12"/>
+</segment>
+<segment>
+<pinref part="C185" gate="G$1" pin="2"/>
+<pinref part="SUPPLY199" gate="GND" pin="GND"/>
+<wire x1="20.32" y1="-73.66" x2="20.32" y2="-71.12" width="0.1524" layer="91"/>
+<pinref part="C186" gate="G$1" pin="2"/>
+<wire x1="20.32" y1="-71.12" x2="20.32" y2="-68.58" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="-68.58" x2="7.62" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="-71.12" x2="20.32" y2="-71.12" width="0.1524" layer="91"/>
+<junction x="20.32" y="-71.12"/>
+</segment>
+<segment>
+<pinref part="C187" gate="G$1" pin="2"/>
+<wire x1="76.2" y1="-68.58" x2="76.2" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="-71.12" x2="81.28" y2="-71.12" width="0.1524" layer="91"/>
+<pinref part="C189" gate="G$1" pin="2"/>
+<wire x1="81.28" y1="-71.12" x2="86.36" y2="-71.12" width="0.1524" layer="91"/>
+<wire x1="86.36" y1="-71.12" x2="86.36" y2="-68.58" width="0.1524" layer="91"/>
+<pinref part="C188" gate="G$1" pin="2"/>
+<wire x1="81.28" y1="-68.58" x2="81.28" y2="-71.12" width="0.1524" layer="91"/>
+<junction x="81.28" y="-71.12"/>
+<pinref part="SUPPLY212" gate="GND" pin="GND"/>
+<wire x1="81.28" y1="-71.12" x2="81.28" y2="-73.66" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="-90.17" y1="45.72" x2="-87.63" y2="45.72" width="0.1524" layer="91"/>
+<pinref part="CN2" gate="G$1" pin="GND"/>
+<pinref part="SUPPLY213" gate="GND" pin="GND"/>
+<wire x1="-87.63" y1="45.72" x2="-87.63" y2="41.91" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FT_RESET1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="!RESET"/>
+<pinref part="R69" gate="G$1" pin="1"/>
+<wire x1="-15.24" y1="30.48" x2="-17.78" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FT_VCCA1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VCCA"/>
+<wire x1="-15.24" y1="43.18" x2="-43.18" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="-43.18" y1="43.18" x2="-43.18" y2="38.1" width="0.1524" layer="91"/>
+<pinref part="C9" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="FT_VCCORE1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VCCORE"/>
+<wire x1="-15.24" y1="45.72" x2="-48.26" y2="45.72" width="0.1524" layer="91"/>
+<wire x1="-48.26" y1="45.72" x2="-48.26" y2="38.1" width="0.1524" layer="91"/>
+<pinref part="C10" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="USB_MGMT_DM" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="DM"/>
+<wire x1="-15.24" y1="38.1" x2="-17.78" y2="38.1" width="0.1524" layer="91"/>
+<label x="-17.78" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<wire x1="-90.17" y1="50.8" x2="-80.01" y2="50.8" width="0.1524" layer="91"/>
+<label x="-80.01" y="50.8" size="1.016" layer="95" xref="yes"/>
+<pinref part="CN2" gate="G$1" pin="D-"/>
+</segment>
+</net>
+<net name="FT_MGMT_VREGIN" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VREGIN"/>
+<wire x1="-15.24" y1="53.34" x2="-17.78" y2="53.34" width="0.1524" layer="91"/>
+<label x="-17.78" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<label x="-80.01" y="55.88" size="1.27" layer="95" xref="yes"/>
+<pinref part="CN2" gate="G$1" pin="VBUS"/>
+<wire x1="-90.17" y1="55.88" x2="-80.01" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="C180" gate="G$1" pin="1"/>
+<wire x1="-76.2" y1="-60.96" x2="-76.2" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="-76.2" y1="-55.88" x2="-83.82" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="C179" gate="G$1" pin="1"/>
+<wire x1="-83.82" y1="-55.88" x2="-83.82" y2="-60.96" width="0.1524" layer="91"/>
+<wire x1="-83.82" y1="-55.88" x2="-83.82" y2="-45.72" width="0.1524" layer="91"/>
+<junction x="-83.82" y="-55.88"/>
+<label x="-88.9" y="-40.64" size="1.778" layer="95"/>
+<pinref part="FT_VCC3V3_14" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+<net name="FT_REF1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="REF"/>
+<wire x1="-15.24" y1="25.4" x2="-27.94" y2="25.4" width="0.1524" layer="91"/>
+<pinref part="R70" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="N$6" class="0">
+<segment>
+<pinref part="R71" gate="G$1" pin="1"/>
+<wire x1="55.88" y1="22.86" x2="71.12" y2="22.86" width="0.1524" layer="91"/>
+<pinref part="LED17" gate="G$1" pin="C"/>
+<wire x1="71.12" y1="22.86" x2="71.12" y2="25.4" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$7" class="0">
+<segment>
+<pinref part="R72" gate="G$1" pin="1"/>
+<wire x1="55.88" y1="20.32" x2="76.2" y2="20.32" width="0.1524" layer="91"/>
+<pinref part="LED18" gate="G$1" pin="C"/>
+<wire x1="76.2" y1="25.4" x2="76.2" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FT_RXLED1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="RXLED#"/>
+<pinref part="R71" gate="G$1" pin="2"/>
+<wire x1="40.64" y1="22.86" x2="45.72" y2="22.86" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FT_TXLED1" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="TXLED#"/>
+<pinref part="R72" gate="G$1" pin="2"/>
+<wire x1="40.64" y1="20.32" x2="45.72" y2="20.32" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="FT_MGMT_VCC3V3" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VCCD"/>
+<wire x1="-15.24" y1="48.26" x2="-33.02" y2="48.26" width="0.1524" layer="91"/>
+<label x="-48.26" y="48.26" size="1.778" layer="95"/>
+<pinref part="R69" gate="G$1" pin="2"/>
+<wire x1="-33.02" y1="48.26" x2="-48.26" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="-27.94" y1="30.48" x2="-33.02" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="-33.02" y1="30.48" x2="-33.02" y2="48.26" width="0.1524" layer="91"/>
+<junction x="-33.02" y="48.26"/>
+</segment>
+<segment>
+<pinref part="FT_VCC3V3_10" gate="VCC" pin="VCC"/>
+<wire x1="73.66" y1="43.18" x2="73.66" y2="38.1" width="0.1524" layer="91"/>
+<pinref part="LED17" gate="G$1" pin="A"/>
+<wire x1="71.12" y1="33.02" x2="71.12" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="71.12" y1="38.1" x2="73.66" y2="38.1" width="0.1524" layer="91"/>
+<pinref part="LED18" gate="G$1" pin="A"/>
+<wire x1="73.66" y1="38.1" x2="76.2" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="38.1" x2="76.2" y2="33.02" width="0.1524" layer="91"/>
+<junction x="73.66" y="38.1"/>
+<label x="76.2" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="C181" gate="G$1" pin="1"/>
+<wire x1="48.26" y1="-60.96" x2="48.26" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="C182" gate="G$1" pin="1"/>
+<wire x1="48.26" y1="-55.88" x2="48.26" y2="-45.72" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="-60.96" x2="55.88" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="55.88" y1="-55.88" x2="48.26" y2="-55.88" width="0.1524" layer="91"/>
+<junction x="48.26" y="-55.88"/>
+<label x="40.64" y="-40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="FT_VCC3V1" gate="VCC" pin="VCC"/>
+<wire x1="15.24" y1="76.2" x2="15.24" y2="68.58" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="VCCIO at 46"/>
+<wire x1="17.78" y1="60.96" x2="17.78" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="68.58" x2="15.24" y2="68.58" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="VCCIO at 24"/>
+<wire x1="15.24" y1="68.58" x2="15.24" y2="60.96" width="0.1524" layer="91"/>
+<junction x="15.24" y="68.58"/>
+<pinref part="U$10" gate="G$1" pin="VCCIO at 12"/>
+<wire x1="12.7" y1="60.96" x2="12.7" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="12.7" y1="68.58" x2="15.24" y2="68.58" width="0.1524" layer="91"/>
+<label x="17.78" y="76.2" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="FT_VCC3V3_11" gate="VCC" pin="VCC"/>
+<wire x1="81.28" y1="-45.72" x2="81.28" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="C187" gate="G$1" pin="1"/>
+<wire x1="76.2" y1="-60.96" x2="76.2" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="-55.88" x2="81.28" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="C188" gate="G$1" pin="1"/>
+<wire x1="81.28" y1="-55.88" x2="81.28" y2="-60.96" width="0.1524" layer="91"/>
+<junction x="81.28" y="-55.88"/>
+<pinref part="C189" gate="G$1" pin="1"/>
+<wire x1="86.36" y1="-60.96" x2="86.36" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="86.36" y1="-55.88" x2="81.28" y2="-55.88" width="0.1524" layer="91"/>
+<label x="76.2" y="-40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="FT_VCC3V3_12" gate="VCC" pin="VCC"/>
+<pinref part="FT_VCC3V3_13" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<wire x1="-50.8" y1="-55.88" x2="-50.8" y2="-45.72" width="0.1524" layer="91"/>
+<label x="-55.88" y="-40.64" size="1.778" layer="95"/>
+<pinref part="FB4" gate="G$1" pin="P$1"/>
+<wire x1="-48.26" y1="-55.88" x2="-50.8" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="FT_VCC3V3_15" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<wire x1="-5.08" y1="-55.88" x2="-5.08" y2="-45.72" width="0.1524" layer="91"/>
+<label x="-10.16" y="-40.64" size="1.778" layer="95"/>
+<pinref part="FB3" gate="G$1" pin="P$1"/>
+<wire x1="-2.54" y1="-55.88" x2="-5.08" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="FT_VCC3V3_17" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+<net name="N$8" class="0">
+<segment>
+<pinref part="C11" gate="G$1" pin="2"/>
+<wire x1="-38.1" y1="-2.54" x2="-33.02" y2="-2.54" width="0.1524" layer="91"/>
+<wire x1="-33.02" y1="-2.54" x2="-33.02" y2="-5.08" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="XCSO"/>
+<wire x1="-15.24" y1="-2.54" x2="-33.02" y2="-2.54" width="0.1524" layer="91"/>
+<junction x="-33.02" y="-2.54"/>
+<pinref part="Y2" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$9" class="0">
+<segment>
+<pinref part="C12" gate="G$1" pin="2"/>
+<wire x1="-43.18" y1="-2.54" x2="-48.26" y2="-2.54" width="0.1524" layer="91"/>
+<wire x1="-48.26" y1="-2.54" x2="-48.26" y2="-5.08" width="0.1524" layer="91"/>
+<pinref part="U$10" gate="G$1" pin="XCSI"/>
+<wire x1="-15.24" y1="5.08" x2="-48.26" y2="5.08" width="0.1524" layer="91"/>
+<wire x1="-48.26" y1="5.08" x2="-48.26" y2="-2.54" width="0.1524" layer="91"/>
+<junction x="-48.26" y="-2.54"/>
+<pinref part="Y2" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="FT_VPHY" class="0">
+<segment>
+<pinref part="C183" gate="G$1" pin="1"/>
+<wire x1="-38.1" y1="-55.88" x2="-25.4" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-60.96" width="0.1524" layer="91"/>
+<pinref part="C184" gate="G$1" pin="1"/>
+<wire x1="-38.1" y1="-60.96" x2="-38.1" y2="-55.88" width="0.1524" layer="91"/>
+<junction x="-38.1" y="-55.88"/>
+<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-45.72" width="0.1524" layer="91"/>
+<junction x="-25.4" y="-55.88"/>
+<label x="-27.94" y="-40.64" size="1.778" layer="95"/>
+<pinref part="FB4" gate="G$1" pin="P$2"/>
+<wire x1="-38.1" y1="-55.88" x2="-43.18" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="FT_VCC3V3_16" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+<net name="FT_MGMT_VPLL" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VPLL"/>
+<wire x1="10.16" y1="60.96" x2="10.16" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="10.16" y1="73.66" x2="-8.89" y2="73.66" width="0.1524" layer="91"/>
+<label x="-8.89" y="73.66" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="C185" gate="G$1" pin="1"/>
+<wire x1="7.62" y1="-55.88" x2="20.32" y2="-55.88" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="-55.88" x2="20.32" y2="-60.96" width="0.1524" layer="91"/>
+<pinref part="C186" gate="G$1" pin="1"/>
+<wire x1="7.62" y1="-60.96" x2="7.62" y2="-55.88" width="0.1524" layer="91"/>
+<junction x="7.62" y="-55.88"/>
+<wire x1="20.32" y1="-55.88" x2="20.32" y2="-45.72" width="0.1524" layer="91"/>
+<junction x="20.32" y="-55.88"/>
+<label x="15.24" y="-40.64" size="1.778" layer="95"/>
+<pinref part="FB3" gate="G$1" pin="P$2"/>
+<wire x1="7.62" y1="-55.88" x2="2.54" y2="-55.88" width="0.1524" layer="91"/>
+<pinref part="FT_VCC3V3_18" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+<net name="USB_MGMT_DP" class="0">
+<segment>
+<label x="-80.01" y="53.34" size="1.016" layer="95" xref="yes"/>
+<pinref part="CN2" gate="G$1" pin="D+"/>
+<wire x1="-80.01" y1="53.34" x2="-90.17" y2="53.34" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="U$10" gate="G$1" pin="DP"/>
+<wire x1="-15.24" y1="35.56" x2="-17.78" y2="35.56" width="0.1524" layer="91"/>
+<label x="-17.78" y="35.56" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="FT_MGMT_VPHY" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="VPHY"/>
+<wire x1="7.62" y1="60.96" x2="7.62" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="7.62" y1="68.58" x2="-8.89" y2="68.58" width="0.1524" layer="91"/>
+<label x="-8.89" y="68.58" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="FT_MGMT_TXD" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="TXD"/>
+<wire x1="40.64" y1="53.34" x2="45.72" y2="53.34" width="0.1524" layer="91"/>
+<label x="45.72" y="53.34" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FT_MGMT_RXD" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="RXD"/>
+<wire x1="40.64" y1="50.8" x2="45.72" y2="50.8" width="0.1524" layer="91"/>
+<label x="45.72" y="50.8" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FT_MGMT_RTS" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="RTS#"/>
+<wire x1="40.64" y1="48.26" x2="45.72" y2="48.26" width="0.1524" layer="91"/>
+<label x="45.72" y="48.26" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FT_MGMT_CTS" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="CTS#"/>
+<wire x1="40.64" y1="45.72" x2="45.72" y2="45.72" width="0.1524" layer="91"/>
+<label x="45.72" y="45.72" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="FT_MGMT_DTR" class="0">
+<segment>
+<pinref part="U$10" gate="G$1" pin="DTR#"/>
+<wire x1="40.64" y1="43.18" x2="45.72" y2="43.18" width="0.1524" layer="91"/>
+<label x="45.72" y="43.18" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+</nets>
+</sheet>
+<sheet>
 <description>Tamper circuit
 Master Key Memory</description>
 <plain>
@@ -40873,7 +42070,10 @@ jumper must be inserted</text>
 <text x="22.86" y="55.88" size="2.54" layer="91">FPGA config memory</text>
 <text x="-134.62" y="-12.7" size="1.27" layer="91">Pull-down CONTROL to
 enable 0 (PROM) by default</text>
-<text x="-149.86" y="81.28" size="2.54" layer="91">Analog switch to boot FPGA from config memory, or from ARM</text>
+<text x="-149.86" y="81.28" size="2.54" layer="91">Analog switch to boot FPGA from config memory, or from ARM
+
+XXX this probably needs more HW support. FPGA is SPI master when booting from config memory,
+but should be SPI slave when being fed a bitstream from the ARM.</text>
 <text x="-152.4" y="-2.54" size="1.27" layer="91">Install this jumper to allow
 ARM to configure the FPGA</text>
 <text x="-160.02" y="27.94" size="1.27" layer="91">XXX are jumpers on the ARM SPI
@@ -41058,8 +42258,8 @@ defaults to the PROM?</text>
 <net name="FPGA_PROM_MISO" class="0">
 <segment>
 <pinref part="IC3" gate="A" pin="DQ1"/>
-<wire x1="33.02" y1="17.78" x2="12.7" y2="17.78" width="0.1524" layer="91"/>
-<label x="12.7" y="17.78" size="1.27" layer="95" rot="R180"/>
+<wire x1="33.02" y1="17.78" x2="0" y2="17.78" width="0.1524" layer="91"/>
+<label x="0" y="17.78" size="1.27" layer="95"/>
 </segment>
 <segment>
 <wire x1="-99.06" y1="20.32" x2="-119.38" y2="20.32" width="0.1524" layer="91"/>
@@ -41071,9 +42271,7 @@ defaults to the PROM?</text>
 <segment>
 <pinref part="IC3" gate="A" pin="!W!/VPP/DQ2"/>
 <wire x1="33.02" y1="15.24" x2="17.78" y2="15.24" width="0.1524" layer="91"/>
-<label x="15.24" y="15.24" size="1.27" layer="95" rot="R180"/>
 <pinref part="R20" gate="G$1" pin="2"/>
-<wire x1="17.78" y1="15.24" x2="0" y2="15.24" width="0.1524" layer="91"/>
 <wire x1="17.78" y1="10.16" x2="17.78" y2="15.24" width="0.1524" layer="91"/>
 <junction x="17.78" y="15.24"/>
 <pinref part="JP7" gate="A" pin="1"/>
@@ -41275,8 +42473,10 @@ one of the two positive (master)
 sides of the two available
 MRCC differential pairs)</text>
 <text x="-53.34" y="45.72" size="1.778" layer="91"><-- FMC_D[...] signals can be swapped</text>
-<text x="-50.8" y="-40.64" size="1.778" layer="91"><-- FMC_* control signals
+<text x="-58.42" y="-43.18" size="1.778" layer="91"><-- FMC_* control signals
       can be swapped</text>
+<text x="73.66" y="-12.7" size="1.778" layer="91">XXX with the addition of the two SDRAM chips,
+do we need an CKE signal to the FPGA?</text>
 </plain>
 <instances>
 <instance part="U7" gate="B13" x="34.29" y="2.54"/>
@@ -41300,12 +42500,6 @@ MRCC differential pairs)</text>
 <label x="-55.88" y="50.8" size="1.778" layer="95"/>
 </segment>
 </bus>
-<bus name="FMC_NE1,FMC_NOE,FMC_NWE,FMC_NL,FMC_NWAIT">
-<segment>
-<wire x1="-53.34" y1="-33.02" x2="-53.34" y2="-48.26" width="0.762" layer="92"/>
-<label x="-78.74" y="-53.34" size="1.778" layer="95"/>
-</segment>
-</bus>
 </busses>
 <nets>
 <net name="VCCO_3V3" class="0">
@@ -41360,7 +42554,7 @@ MRCC differential pairs)</text>
 <pinref part="P+39" gate="VCC" pin="VCC"/>
 </segment>
 </net>
-<net name="FPGA_FMC_CLK" class="0">
+<net name="FMC_CLK" class="0">
 <segment>
 <pinref part="U7" gate="B13" pin="IO_L12P_T1_MRCC_13"/>
 <wire x1="39.37" y1="-20.32" x2="73.66" y2="-20.32" width="0.1524" layer="91"/>
@@ -41594,36 +42788,36 @@ MRCC differential pairs)</text>
 <net name="FMC_NE1" class="0">
 <segment>
 <pinref part="U7" gate="B34" pin="IO_L16N_T2_34"/>
-<wire x1="-53.34" y1="-35.56" x2="-86.36" y2="-35.56" width="0.1524" layer="91"/>
-<label x="-73.66" y="-35.56" size="1.778" layer="95"/>
+<wire x1="-81.28" y1="-35.56" x2="-86.36" y2="-35.56" width="0.1524" layer="91"/>
+<label x="-81.28" y="-35.56" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NL" class="0">
 <segment>
 <pinref part="U7" gate="B34" pin="IO_L17P_T2_34"/>
-<wire x1="-53.34" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/>
-<label x="-73.66" y="-38.1" size="1.778" layer="95"/>
+<wire x1="-81.28" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/>
+<label x="-81.28" y="-38.1" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NOE" class="0">
 <segment>
 <pinref part="U7" gate="B34" pin="IO_L17N_T2_34"/>
-<wire x1="-53.34" y1="-40.64" x2="-86.36" y2="-40.64" width="0.1524" layer="91"/>
-<label x="-73.66" y="-40.64" size="1.778" layer="95"/>
+<wire x1="-81.28" y1="-40.64" x2="-86.36" y2="-40.64" width="0.1524" layer="91"/>
+<label x="-81.28" y="-40.64" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NWAIT" class="0">
 <segment>
 <pinref part="U7" gate="B34" pin="IO_L18P_T2_34"/>
-<wire x1="-53.34" y1="-43.18" x2="-86.36" y2="-43.18" width="0.1524" layer="91"/>
-<label x="-73.66" y="-43.18" size="1.778" layer="95"/>
+<wire x1="-81.28" y1="-43.18" x2="-86.36" y2="-43.18" width="0.1524" layer="91"/>
+<label x="-81.28" y="-43.18" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_NWE" class="0">
 <segment>
 <pinref part="U7" gate="B34" pin="IO_L18N_T2_34"/>
-<wire x1="-53.34" y1="-45.72" x2="-86.36" y2="-45.72" width="0.1524" layer="91"/>
-<label x="-73.66" y="-45.72" size="1.778" layer="95"/>
+<wire x1="-81.28" y1="-45.72" x2="-86.36" y2="-45.72" width="0.1524" layer="91"/>
+<label x="-81.28" y="-45.72" size="1.27" layer="95" xref="yes"/>
 </segment>
 </net>
 <net name="FMC_A0" class="3">
diff --git a/eagle/lbr/Alpha-IC.lbr b/eagle/lbr/Alpha-IC.lbr
index 2bc44a7..6486c84 100644
--- a/eagle/lbr/Alpha-IC.lbr
+++ b/eagle/lbr/Alpha-IC.lbr
@@ -337,9 +337,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i>
 </symbols>
 <devicesets>
 <deviceset name="IS45S32160F" prefix="IC">
-<description><b></b> <font color="red">edit this description</font><p>
-Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i><br>
-Source:</description>
+<description>16Mx32, 512Mb SDRAM
+Clock frequency: 166, 143 MHz</description>
 <gates>
 <gate name="G$1" symbol="IS45S32160F-TSOP86L" x="0" y="0"/>
 </gates>
@@ -428,7 +427,10 @@ Source:</description>
 <connect gate="G$1" pin="VSSQ at 84" pad="84"/>
 </connects>
 <technologies>
-<technology name=""/>
+<technology name="">
+<attribute name="MPN" value="IS45S32160F" constant="no"/>
+<attribute name="SUPPLIER" value="ISSI" constant="no"/>
+</technology>
 </technologies>
 </device>
 </devices>

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