[Cryptech-Commits] [core/comm/i2c] 01/01: Don't delay register reads in i2c_regs.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository core/comm/i2c.

commit f94ca1a732c7f350372bb872741c25b3e6b1bbad
Author: Paul Selkirk <paul at psgd.org>
Date:   Tue Mar 31 16:25:31 2015 -0400

    Don't delay register reads in i2c_regs.
---
 src/rtl/i2c_regs.v | 72 ++++++++++++++++++++++++++----------------------------
 1 file changed, 35 insertions(+), 37 deletions(-)

diff --git a/src/rtl/i2c_regs.v b/src/rtl/i2c_regs.v
index e5ddb34..ec1c186 100644
--- a/src/rtl/i2c_regs.v
+++ b/src/rtl/i2c_regs.v
@@ -70,7 +70,7 @@ module comm_regs
    reg [31: 0]          tmp_read_data;
 
    // dummy register to check that you can actually write something
-   reg [31: 0] 		reg_dummy;
+   reg [31: 0]          reg_dummy;
 
 
    //----------------------------------------------------------------
@@ -80,44 +80,42 @@ module comm_regs
    
 
    //----------------------------------------------------------------
-   // Access Handler
+   // storage registers for mapping memory to core interface
    //----------------------------------------------------------------
-   always @(posedge clk)
-     //
-     if (rst) begin
-	reg_dummy <= {32{1'b0}};
+   always @ (posedge clk or posedge rst)
+     begin
+        if (rst)
+          begin
+             reg_dummy <= {32{1'b0}};
+          end
+        else if (cs && we)
+          begin
+             // write operations
+             case (address)
+               ADDR_DUMMY_REG:
+                 reg_dummy <= write_data;
+             endcase
+          end
      end
-     else if (cs) begin
-        //
-        if (we) begin
-           //
-           // WRITE handler
-           //
-           case (address)
-             ADDR_DUMMY_REG:
-               reg_dummy <= write_data;
-           endcase
-           //
-        end else begin
-           //
-           // READ handler
-           //
-           case (address)
-             ADDR_CORE_NAME0:
-               tmp_read_data <= CORE_NAME0;
-             ADDR_CORE_NAME1:
-               tmp_read_data <= CORE_NAME1;
-             ADDR_CORE_VERSION:
-               tmp_read_data <= CORE_VERSION;
-             ADDR_DUMMY_REG:
-               tmp_read_data <= reg_dummy;
-             //
-             default:
-               tmp_read_data <= {32{1'b0}};  // read non-existent locations as zeroes
-           endcase
-           //
-        end
-        //
+
+   always @*
+     begin
+        tmp_read_data = 32'h00000000;
+
+        if (cs && !we)
+          begin
+             // read operations
+             case (address)
+               ADDR_CORE_NAME0:
+                 tmp_read_data = CORE_NAME0;
+               ADDR_CORE_NAME1:
+                 tmp_read_data = CORE_NAME1;
+               ADDR_CORE_VERSION:
+                 tmp_read_data = CORE_VERSION;
+               ADDR_DUMMY_REG:
+                 tmp_read_data = reg_dummy;
+             endcase
+          end
      end
 
 endmodule