[Cryptech-Commits] [core/math/modexp] branch master updated (502f0f4 -> a315223)

[git at cryptech.is]

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joachim at secworks.se pushed a change to branch master
in repository core/math/modexp.

      from  502f0f4   (1) Adding auto generated testbench for verilog. (2) Update of the test generator. (3) Update of the Makefile to run test generator.
       new  a315223   Updating modexp core to v 0.50. This version contains a working core that can perform sign and verify with big keys/values. The core builds ok in Altera and Xilinx FPGA tools. This commit also includes a new testgenerator capable of generating testbench for modexp with autgenerated test data of different lengths. The README has been updated with status and implementation results in for different FPGA devices.

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Summary of changes:
 .gitignore                                         |    2 +
 README.md                                          |   88 +-
 src/model/c/src/autogenerated_tests.c              |  154 ++
 src/model/c/src/montgomery_array.c                 |   23 +-
 src/model/c/src/montgomery_array.h                 |    2 +-
 src/model/python/modexp.py                         |  203 ++
 src/rtl/modexp.v                                   |  348 ++-
 src/rtl/montprod.v                                 |   12 +-
 src/tb/tb_modexp.v                                 |  466 +++-
 src/tb/tb_modexp_autogenerated.v                   | 2289 +++++++++++++++-----
 src/tb/tb_modexp_autogenerated_template.v          |   54 +-
 src/tb/tb_montprod.v                               |    6 +-
 src/tb/tb_residue.v                                |    8 +-
 .../modexp/testgenerator/TestGeneratorBasic.java   |   13 +-
 .../testgenerator/format/GeneratorVerilog.java     |  109 +-
 .../testgenerator/format/ModExpTestFormater.java   |    1 +
 toolruns/Makefile                                  |   15 +-
 17 files changed, 3058 insertions(+), 735 deletions(-)
 create mode 100755 src/model/python/modexp.py