[Cryptech-Commits] [core/math/modexp] 06/06: Adding testbench for the residue calculator.
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Mon Apr 20 07:58:14 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository core/math/modexp.
commit b8e6a576f11a0f91d31413e4249505d053030403
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Mon Apr 20 09:49:56 2015 +0200
Adding testbench for the residue calculator.
---
src/tb/tb_residue.v | 379 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 379 insertions(+)
diff --git a/src/tb/tb_residue.v b/src/tb/tb_residue.v
new file mode 100644
index 0000000..4978bf9
--- /dev/null
+++ b/src/tb/tb_residue.v
@@ -0,0 +1,379 @@
+//======================================================================
+//
+// tb_residue.v
+// ------------
+// Testbench: Modulus 2**2N residue calculator for montgomery calculations.
+//
+// m_residue_2_2N_array( N, M, Nr)
+// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
+// for (int i = 0; i < 2 * N; i++)
+// Nr = Nr shift left 1
+// if (Nr less than M) continue;
+// Nr = Nr - M
+// return Nr
+//
+//
+//
+// Author: Peter Magnusson
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+//------------------------------------------------------------------
+// Simulator directives.
+//------------------------------------------------------------------
+`timescale 1ns/100ps
+
+//------------------------------------------------------------------
+// Test module.
+//------------------------------------------------------------------
+
+module tb_residue();
+
+
+//----------------------------------------------------------------
+// Internal constant and parameter definitions.
+//----------------------------------------------------------------
+ parameter SHOW_INIT = 0;
+
+ parameter DUMP_MEM = 0;
+ parameter DEBUG = 0;
+ parameter CLK_HALF_PERIOD = 2;
+ parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+
+//----------------------------------------------------------------
+// Register and Wire declarations.
+//----------------------------------------------------------------
+
+reg tb_clk;
+reg tb_reset_n;
+reg tb_calculate;
+wire tb_ready;
+reg [14 : 0] tb_nn;
+reg [ 7 : 0] tb_length;
+wire [ 7 : 0] tb_opa_rd_addr;
+wire [31 : 0] tb_opa_rd_data;
+wire [ 7 : 0] tb_opa_wr_addr;
+wire [31 : 0] tb_opa_wr_data;
+wire tb_opa_wr_we;
+wire [ 7 : 0] tb_opm_addr;
+wire [31 : 0] tb_opm_data;
+wire [ 7 : 0] tb_result_addr;
+wire [31 : 0] tb_result_data;
+wire tb_result_we;
+
+integer test_residue_success;
+integer test_residue_fail;
+
+//----------------------------------------------------------------
+// Device Under Test
+//----------------------------------------------------------------
+
+residue dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+ .calculate(tb_calculate),
+ .ready(tb_ready),
+
+ .nn(tb_nn), //MAX(2*N)=8192*2 (14 bit)
+ .length(tb_length),
+
+ .opa_rd_addr(tb_opa_rd_addr),
+ .opa_rd_data(tb_opa_rd_data),
+ .opa_wr_addr(tb_opa_wr_addr),
+ .opa_wr_data(tb_opa_wr_data),
+ .opa_wr_we(tb_opa_wr_we),
+
+ .opm_addr(tb_opm_addr),
+ .opm_data(tb_opm_data)
+);
+
+//----------------------------------------------------------------
+// Memory
+//----------------------------------------------------------------
+
+blockmem1r1w mem_a( //Memory to be loaded with 2**N modulus N
+ .clk(tb_clk),
+ .read_addr(tb_opa_rd_addr),
+ .read_data(tb_opa_rd_data),
+ .wr(tb_opa_wr_we),
+ .write_addr(tb_opa_wr_addr),
+ .write_data(tb_opa_wr_data)
+);
+
+blockmem1r1w mem_m( // Modulus M memory
+ .clk(tb_clk),
+ .read_addr(tb_opm_addr),
+ .read_data(tb_opm_data),
+ .wr(1'b0),
+ .write_addr(8'h0),
+ .write_data(32'h0)
+);
+
+//----------------------------------------------------------------
+// clk_gen
+//
+// Clock generator process.
+//----------------------------------------------------------------
+always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+//----------------------------------------------------------------
+// Debug monitor the FSM
+//----------------------------------------------------------------
+//always @ (posedge tb_clk)
+// begin : fsm_debug
+// if (dut.residue_ctrl_we)
+// case (dut.residue_ctrl_new)
+// dut.CTRL_IDLE:
+// $display("FSM: IDLE");
+// default:
+// $display("FSM: %x", dut.residue_ctrl_new);
+// endcase
+// end
+
+//----------------------------------------------------------------
+// Debug monitor the loop counter
+//----------------------------------------------------------------
+//always @*
+// $display("*** loop counter: %x, nn: %x ", dut.loop_counter_1_to_nn_reg, dut.nn_reg);
+
+//----------------------------------------------------------------
+// Debug monitor writes
+//----------------------------------------------------------------
+//always @*
+// if (tb_opa_wr_we === 1'b1)
+// $display("*** write mem[%x] = [%x] ", tb_opa_wr_addr, tb_opa_wr_data);
+
+//----------------------------------------------------------------
+// Debug monitor one
+//----------------------------------------------------------------
+always @*
+ $display("*** one = [%x] ", dut.one_data);
+
+//----------------------------------------------------------------
+// Debug monitor comparision
+//----------------------------------------------------------------
+//always @*
+// if (dut.residue_ctrl_reg == dut.CTRL_COMPARE_STALL)
+// $display("*** CF = [%x] ", dut.sub_carry_in_reg);
+//always @*
+// $display("*** CFnew = [%x] ", dut.sub_carry_in_new);
+//always @*
+// $display("*** CFreg = [%x] ", dut.sub_carry_in_reg);
+//always @*
+// if (dut.residue_ctrl_reg == dut.CTRL_COMPARE)
+// $display("*** COMPARE (CFin=%x) A-M: %x - %x = %x (CFout=%x) addr: %x %x", dut.sub_carry_in_reg, dut.opa_rd_data, dut.opm_data, dut.sub_data, dut.sub_carry_out, dut.opa_rd_addr, dut.opm_addr);
+
+
+//----------------------------------------------------------------
+// reset_dut()
+//
+// Toggles reset to force the DUT into a well defined state.
+//----------------------------------------------------------------
+task reset_dut();
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(4 * CLK_HALF_PERIOD);
+ tb_reset_n = 1;
+ end
+endtask // reset_dut
+
+//----------------------------------------------------------------
+// init_sim()
+//
+// Initialize all counters and testbed functionality as well
+// as setting the DUT inputs to defined values.
+//----------------------------------------------------------------
+task init_sim();
+ begin
+ $display("*** init_sim");
+ tb_clk = 0;
+ tb_reset_n = 0;
+ tb_length = 0;
+ tb_calculate = 0;
+ test_residue_success = 0;
+ test_residue_fail = 0;
+ end
+endtask // init_dut
+
+//----------------------------------------------------------------
+// wait_ready()
+//
+// Wait for the ready flag in the dut to be set.
+//
+// Note: It is the callers responsibility to call the function
+// when the dut is actively processing and will in fact at some
+// point set the flag.
+//----------------------------------------------------------------
+task wait_ready();
+ begin
+ $display("*** wait_ready");
+ begin: wait_loop
+ integer i;
+ for (i=0; i<100000000; i=i+1)
+ if (tb_ready == 0)
+ #(2 * CLK_HALF_PERIOD);
+ else if (tb_ready === 1)
+ i = 100000000000000000000;
+ end
+ if (tb_ready == 0)
+ begin
+ $display("*** wait_ready failed, never became ready!");
+ $finish;
+ end
+ else
+ $display("*** wait_ready: done");
+ end
+endtask // wait_ready
+
+//----------------------------------------------------------------
+// Tells the DUT to start doing its magic!
+//----------------------------------------------------------------
+task signal_calculate();
+ begin
+ $display("*** signal_calculate");
+ tb_calculate = 1;
+ #(2 * CLK_HALF_PERIOD);
+ tb_calculate = 0;
+ end
+endtask // signal_calculate
+
+//----------------------------------------------------------------
+// Tests the residue calculator
+//----------------------------------------------------------------
+task test_residue(
+ input [7 : 0] length,
+ input [14 : 0] nn,
+ input [0 : 8192-1] m,
+ input [0 : 8192-1] expected
+ );
+ begin
+ $display("*** test started");
+ begin: copy_test_vectors
+ integer i;
+ integer j;
+ reg [31 : 0] aa;
+ reg [31 : 0] mm;
+
+ $display("*** Initializing...");
+ for (i=32'h0; i<256; i=i+1)
+ begin
+ j = {i, 5'h0};
+ mm = m[j +: 32];
+ mem_m.mem[i] = mm;
+ if (SHOW_INIT)
+ $display("*** init %0x: m: %x", i, mm);
+ end
+ end
+
+ $display("*** Test vector copied");
+ wait_ready();
+ tb_length = length;
+ tb_nn = nn;
+ signal_calculate();
+ wait_ready();
+ begin: verify_test_vectors
+ integer i;
+ integer j;
+ integer success;
+ integer fail;
+ success = 1;
+ fail = 0;
+ for (i=0; i<length; i=i+1)
+ begin
+ j = i * 32;
+ $display("offset: %02d expected 0x%08x actual 0x%08x", i, expected[j +: 32], mem_a.mem[i]);
+ if (expected[j +: 32] !== mem_a.mem[i])
+ begin
+ success = 0;
+ fail = 1;
+ end
+ end
+ test_residue_success = test_residue_success + success;
+ test_residue_fail = test_residue_fail + fail;
+ end
+
+ $display("*** test stopped");
+ end
+endtask
+
+//----------------------------------------------------------------
+// The main test functionality.
+//----------------------------------------------------------------
+initial
+ begin : modulus_residue_tests
+ $display(" -- Testbench for residue started --");
+ init_sim();
+ reset_dut();
+
+
+ //Verify that 1**(2*32) mod 8 == 0; i.e. does the compare pick up 8==8 => SUB work?
+ test_residue( 1, 32, { 32'h08, 8160'h0 }, { 32'h0, 8160'h0 } );
+
+//m_residue_2_2N_array N: 96
+//m_residue_2_2N_array M: 1ffffff ffffffff ffffffff
+//m_residue_2_2N_array Nr: 0 0 4000
+
+ test_residue( 3, 96+96, { 96'h1ffffffffffffffffffffff, 8096'h0 }, { 96'h4000, 8096'h0 } );
+
+
+//test_modExp_4096bit_e65537
+//m_residue_2_2N_array N: 4128
+//m_residue_2_2N_array M: 00000000 ecc9307c 57a39970 7e9e2569 872cd790 0d4dddcc 704fd131 9395388d 07e63a16 37ea6fae 3873a01e 0df4a57b b90bc708 a05ade61 91ef3868 58db06db 893e2d41 c75bb93d 0c7f3be8 8f57c9f9 477efa62 f509e077 568d59aa 28552ee8 a042f88d f776a12d 19f3685b 1205c3f7 fb7db6c5 354908b1 099640c0 709ab3e8 e76149de 6bc111d2 95210730 bab8e493 95168d09 5242aba5 4b98da8a b755eb64 246c6732 c8fd54f4 f6ed5686 6ca61ceb 239f1133 1abdc477 24a35c02 baef93b4 6b856235 b34318c6 420da1a7 a94a7 [...]
+//m_residue_2_2N_array Nr: 00000000 d41b628b a651c4d2 f697e11a 71d9b46b eb909ee1 ba9f2866 247ec50c 5a0eefbf 370da146 50adff1b b1b2c306 9f099d33 bc5caced 6825cee8 c69854a9 3448e0ea e5309441 d1ff98fa a71e5f87 8bc1b1f0 db05a40d 11985c39 0be193ef 0ccdc291 114ea54c 876ca7ef 0594a93b c424f13a d76a0868 cae2f8fd c1b44a38 5c612274 cd29a45f 4f182e90 eb43bcba 9a000a0c deb6d313 52ce2c6e f12ee479 299ce548 34ff35a5 2b4ab09c 3bfa7f84 0d616f5b 5457cb5b 15aaab76 fb904268 5088c2a6 bcbe1468 38f7dc3d 70133 [...]
+
+
+test_residue(129,4128+4128,{4128'h00000000ecc9307c57a399707e9e2569872cd7900d4dddcc704fd1319395388d07e63a1637ea6fae3873a01e0df4a57bb90bc708a05ade6191ef386858db06db893e2d41c75bb93d0c7f3be88f57c9f9477efa62f509e077568d59aa28552ee8a042f88df776a12d19f3685b1205c3f7fb7db6c5354908b1099640c0709ab3e8e76149de6bc111d295210730bab8e49395168d095242aba54b98da8ab755eb64246c6732c8fd54f4f6ed56866ca61ceb239f11331abdc47724a35c02baef93b46b856235b34318c6420da1a7a94a7298531416620bfb5c3d183fa12c5c4b3e4a6cd2f7cdc5 [...]
+{4128'h00000000d41b628ba651c4d2f697e11a71d9b46beb909ee1ba9f2866247ec50c5a0eefbf370da14650adff1bb1b2c3069f099d33bc5caced6825cee8c69854a93448e0eae5309441d1ff98faa71e5f878bc1b1f0db05a40d11985c390be193ef0ccdc291114ea54c876ca7ef0594a93bc424f13ad76a0868cae2f8fdc1b44a385c612274cd29a45f4f182e90eb43bcba9a000a0cdeb6d31352ce2c6ef12ee479299ce54834ff35a52b4ab09c3bfa7f840d616f5b5457cb5b15aaab76fb9042685088c2a6bcbe146838f7dc3d701330dfc4f40fcd0638af148692e4b7767954fda68934785a91b1401b1e485a8adc96a207e75 [...]
+
+// ----- test_modExp_8192_e65537 -----
+//m_residue_2_2N_array N: 8224
+//m_residue_2_2N_array M: 0 9985a7f5 b471b248 d13838a3 75e22fc7 e0d72b0 6ea72eb3 958b1b8e 431cb10d 72421e7e b0e33fa3 c5b6d437 b7c1ce28 e4960b94 7c36159e c98580a1 2c98a45e 8c0a5d37 65bdbb62 707d3cec 3d2d25e d8e420e8 ec24c78b ec2f2dbe 97572117 5933fa87 1440858 cf4e5a64 e6a0f624 59c0e042 83d52d2c 6c4144c0 112769f5 86b85e44 434015d2 b4473787 1f33a844 c717bf3 ea8228f0 7b46cbc4 28c15ea0 a4bdda03 27314b2f 6ea6856e ec9cbd40 40cfea29 f5fab20a 3726bdc0 74eb6930 52cf502a f77f8d47 f27ac [...]
+//m_residue_2_2N_array Nr: 0 72f3903e 3f18548d e26585c2 af1e07a7 702224df dff934d eb67d0b4 6a045abf e862d07d 91fed83c d48a17a4 31e44448 fad86891 dd6a0ab6 1abd8580 738a05d4 60dc5bad f114312c c41a1222 2ef5a5fa be62f6fd 57a3b9bf e10a1884 eeef8d4e 4f98d513 fbea6fb7 23ff8744 531b8f85 779afc60 966d8b3e 9e276968 5ccd04dd 24b0f4b0 2199d76d 59ec5b9f 3d9d1456 dc07107 a56596ee 3afe5ae5 59261595 e8c132bb 8c94c31f 201b4b66 4bb2be56 f66b7146 19e51695 eac7b76 68e7c8b0 10649618 24dea4b2 8e12c [...]
+
+//=== test_modExp_8192bit ===
+//m_residue_2_2N_array N: 8224
+//m_residue_2_2N_array M: 0 86ad85ba 6b9fa483 25cb106f cf6cc989 911b28f0 1ffd3ef8 30a310db 8851dea4 b16eba5 7cb2e8a5 86729373 37af6f23 81fd1e6c 3372378b f96a2650 42e123b5 8bd46899 279f2de 86af6d84 fbb68d9c 5eba0c14 d07f668d 540bb4e3 fc6fe1ef e7200b10 3e83851d 840bc907 b02a53e4 2ce98544 f1c2ed89 393d845 8798af50 b643566f b883f180 1bc13e4c 65313872 14407175 97edfde2 9cae23ed 6c191326 60ca5eef 8a20b205 36d3ae1b 2829a6a1 441eb400 1a64097f 7827120d d5aee730 b9e4db3e 8f37694 dd13a [...]
+//m_residue_2_2N_array Nr: 0 7a208e1a 4b3b8298 e46a15e8 3c4f7945 e53db84e 7ff2678e 76e07a85 d68923d3 f8107779 3d1e2643 4a401c50 112a26f8 8c8c1996 fc4bd3b0 8710f5d8 56e29679 8fa51b8d 78e880ba de954d37 d09dc1bf eb192991 2d51f26f acfb883d db975349 13166f21 ca4549da 9dd09b10 77c2458b 1b2e3b20 20fe824b 9052c645 2f154e74 b1e0151f ec9735b2 1991c577 a446a7d3 3ba6a681 ea980129 9e4ed27d 2b7ac25e b028278c 10d6f810 eec56ad5 a83f99ed 1e3ff9fb fa9bf439 276f1b91 5c68e785 986da263 d35f98ef 632e1 [...]
+
+
+ $display(" -- Testbench for residue done. --");
+ $display(" tests success: %d", test_residue_success);
+ $display(" tests failed: %d", test_residue_fail);
+ $finish;
+ end // residue tests
+endmodule // tb_residue
+
+//======================================================================
+// EOF tb_residue.v
+//======================================================================
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