[Cryptech-Commits] [core/rng/trng] 01/01: Adding target for csprng output simulation target.

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joachim at secworks.se pushed a commit to branch master
in repository core/rng/trng.

commit 92653b79b5ae2942783e09c702794e8f3b4ba931
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed Apr 1 13:49:14 2015 +0200

    Adding target for csprng output simulation target.
---
 toolruns/Makefile | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/toolruns/Makefile b/toolruns/Makefile
index 930e182..423f795 100644
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -41,8 +41,12 @@ CHACHA_SRC=$(CHACHA_SRC_DIR)chacha_core.v $(CHACHA_SRC_DIR)chacha_qr.v
 CSPRNG_SRC=../src/rtl/trng_csprng.v ../src/rtl/trng_csprng_fifo.v
 TB_CSPRNG_SRC=../src/tb/tb_csprng.v
 
+CSPRNG_FIFO_SRC=../src/rtl/trng_csprng_fifo.v
+TB_CSPRNG_FIFO_SRC=../src/tb/tb_csprng_fifo.v
+
 SHA512_SRC_DIR=../../../hash/sha512/src/rtl/
 SHA512_SRC=$(SHA512_SRC_DIR)sha512_core.v $(SHA512_SRC_DIR)sha512_h_constants.v $(SHA512_SRC_DIR)sha512_k_constants.v $(SHA512_SRC_DIR)sha512_w_mem.v
+
 MIXER_SRC=../src/rtl/trng_mixer.v
 TB_MIXER_SRC=../src/tb/tb_mixer.v
 
@@ -53,13 +57,17 @@ FAKE_ENTROPY_SRC=../src/tb/fake_modules/avalanche_entropy.v ../src/tb/fake_modul
 CC=iverilog
 
 
-all: trng.sim mixer.sim csprng.sim
+all: trng.sim mixer.sim csprng.sim csprng_fifo.sim
 
 
 csprng.sim: $(TB_CSPRNG_SRC) $(CSPRNG_SRC) $(CHACHA_SRC)
 	$(CC) -o csprng.sim $(TB_CSPRNG_SRC) $(CSPRNG_SRC) $(CHACHA_SRC)
 
 
+csprng_fifo.sim: $(TB_CSPRNG_FIFO_SRC) $(CSPRNG_FIFO_SRC)
+	$(CC) -o csprng_fifo.sim $(TB_CSPRNG_FIFO_SRC) $(CSPRNG_FIFO_SRC)
+
+
 mixer.sim: $(TB_MIXER_SRC) $(MIXER_SRC) $(SHA512_SRC)
 	$(CC) -o mixer.sim $(TB_MIXER_SRC) $(MIXER_SRC) $(SHA512_SRC)