[Cryptech-Commits] [core/avalanche_entropy] 01/01: Refactor code to have the main entropy functionality in the core and api in the wrapper.
git at cryptech.is
git at cryptech.is
Sat Sep 27 12:35:17 UTC 2014
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joachim at secworks.se pushed a commit to branch master
in repository core/avalanche_entropy.
commit ca53c8ca329ced2c983e7ffba4b41fd8da1de022
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Sat Sep 27 14:35:11 2014 +0200
Refactor code to have the main entropy functionality in the core and api in the wrapper.
---
src/rtl/avalanche_entropy.v | 228 ++++++---------------------------------
src/rtl/avalanche_entropy_core.v | 122 +++++++--------------
2 files changed, 74 insertions(+), 276 deletions(-)
diff --git a/src/rtl/avalanche_entropy.v b/src/rtl/avalanche_entropy.v
index bc3a815..bbaa770 100644
--- a/src/rtl/avalanche_entropy.v
+++ b/src/rtl/avalanche_entropy.v
@@ -72,62 +72,29 @@ module avalanche_entropy(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter ADDR_CTRL = 8'h10;
- parameter CTRL_ENABLE_BIT = 0;
+ parameter ADDR_CTRL = 8'h10;
+ parameter CTRL_ENABLE_BIT = 0;
- parameter ADDR_STATUS = 8'h11;
- parameter ADDR_ENTROPY = 8'h20;
- parameter ADDR_DELTA = 8'h30;
+ parameter ADDR_STATUS = 8'h11;
+ parameter STATUS_ENABLE_VALID_BIT = 0;
- parameter DEBUG_DELAY = 32'h002c4b40;
+ parameter ADDR_ENTROPY = 8'h20;
+ parameter ADDR_DELTA = 8'h30;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
- reg noise_sample0_reg;
- reg noise_sample_reg;
-
- reg flank0_reg;
- reg flank1_reg;
-
- reg entropy_bit_reg;
-
- reg [31 : 0] entropy_reg;
- reg [31 : 0] entropy_new;
- reg entropy_we;
-
- reg entropy_syn_reg;
- reg entropy_syn_new;
-
- reg [5 : 0] bit_ctr_reg;
- reg [5 : 0] bit_ctr_new;
- reg bit_ctr_inc;
- reg bit_ctr_we;
-
- reg [31 : 0] cycle_ctr_reg;
- reg [31 : 0] cycle_ctr_new;
-
- reg [31 : 0] delta_reg;
- reg delta_we;
-
reg enable_reg;
reg enable_new;
reg enable_we;
- reg [31 : 0] debug_delay_ctr_reg;
- reg [31 : 0] debug_delay_ctr_new;
- reg debug_delay_ctr_we;
-
- reg [7 : 0] debug_reg;
- reg debug_we;
-
- reg debug_update_reg;
-
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
+ wire [31 : 0] delta;
+
reg [31 : 0] tmp_read_data;
reg tmp_error;
@@ -139,11 +106,29 @@ module avalanche_entropy(
assign error = tmp_error;
assign security_error = 0;
- assign entropy_valid = entropy_syn_reg;
- assign entropy_data = entropy_reg;
assign entropy_enabled = enable_reg;
- assign debug = debug_reg;
+
+ //----------------------------------------------------------------
+ // Core instantiation.
+ //----------------------------------------------------------------
+ avalanche_entropy_core core(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .noise(noise),
+
+ .enable(enable_reg),
+
+ .entropy_data(entropy_data),
+ .entropy_valid(entropy_valid),
+ .entropy_ack(entropy_ack),
+
+ .delta(delta),
+
+ .debug(debug),
+ .debug_update(debug_update)
+ );
//----------------------------------------------------------------
@@ -153,166 +138,19 @@ module avalanche_entropy(
begin
if (!reset_n)
begin
- noise_sample0_reg <= 1'b0;
- noise_sample_reg <= 1'b0;
- flank0_reg <= 1'b0;
- flank1_reg <= 1'b0;
- entropy_syn_reg <= 1'b0;
- entropy_reg <= 32'h00000000;
- entropy_bit_reg <= 1'b0;
- bit_ctr_reg <= 6'h00;
- cycle_ctr_reg <= 32'h00000000;
- delta_reg <= 32'h00000000;
- enable_reg <= 1;
- debug_delay_ctr_reg <= 32'h00000000;
- debug_reg <= 8'h00;
- debug_update_reg <= 0;
+ enable_reg <= 1;
end
else
begin
- noise_sample0_reg <= noise;
- noise_sample_reg <= noise_sample0_reg;
-
- flank0_reg <= noise_sample_reg;
- flank1_reg <= flank0_reg;
-
- entropy_syn_reg <= entropy_syn_new;
- entropy_bit_reg <= ~entropy_bit_reg;
- cycle_ctr_reg <= cycle_ctr_new;
-
- debug_update_reg <= debug_update;
-
if (enable_we)
begin
enable_reg <= enable_new;
end
-
- if (delta_we)
- begin
- delta_reg <= cycle_ctr_reg;
- end
-
- if (bit_ctr_we)
- begin
- bit_ctr_reg <= bit_ctr_new;
- end
-
- if (entropy_we)
- begin
- entropy_reg <= entropy_new;
- end
-
- if (debug_delay_ctr_we)
- begin
- debug_delay_ctr_reg <= debug_delay_ctr_new;
- end
-
- if (debug_we)
- begin
- debug_reg <= entropy_reg[7 : 0];
- end
end
end // reg_update
//----------------------------------------------------------------
- // debug_out
- //
- // Logic that updates the debug port.
- //----------------------------------------------------------------
- always @*
- begin : debug_out
- debug_delay_ctr_new = 8'h00000000;
- debug_delay_ctr_we = 0;
- debug_we = 0;
-
- if (debug_update_reg)
- begin
- debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
- debug_delay_ctr_we = 1;
- end
-
- if (debug_delay_ctr_reg == DEBUG_DELAY)
- begin
- debug_delay_ctr_new = 8'h00000000;
- debug_delay_ctr_we = 1;
- debug_we = 1;
- end
- end
-
-
- //----------------------------------------------------------------
- // entropy_collect
- //
- // We collect entropy by adding the current state of the
- // entropy bit register the entropy shift register every time
- // we detect a positive flank in the noise source.
- //----------------------------------------------------------------
- always @*
- begin : entropy_collect
- entropy_new = 32'h00000000;
- entropy_we = 1'b0;
- bit_ctr_inc = 1'b0;
-
- if ((flank0_reg) && (!flank1_reg))
- begin
- entropy_new = {entropy_reg[30 : 0], entropy_bit_reg};
- entropy_we = 1'b1;
- bit_ctr_inc = 1'b1;
- end
- end // entropy_collect
-
-
- //----------------------------------------------------------------
- // delta_logic
- //
- // The logic implements the delta time measuerment system.
- //----------------------------------------------------------------
- always @*
- begin : delta_logic
- cycle_ctr_new = cycle_ctr_reg + 1'b1;
- delta_we = 1'b0;
-
- if ((flank0_reg) && (!flank1_reg))
- begin
- cycle_ctr_new = 32'h00000000;
- delta_we = 1'b1;
- end
- end // delta_logic
-
-
- //----------------------------------------------------------------
- // entropy_ack_logic
- //
- // The logic needed to handle detection that entropy has been
- // read and ensure that we collect more than 32 entropy
- // bits beforeproviding more entropy.
- //----------------------------------------------------------------
- always @*
- begin : entropy_ack_logic
- bit_ctr_new = 6'h00;
- bit_ctr_we = 1'b0;
- entropy_syn_new = 1'b0;
-
- if (bit_ctr_reg == 6'h20)
- begin
- entropy_syn_new = 1'b1;
- end
-
- if ((bit_ctr_inc) && (bit_ctr_reg < 6'h20))
- begin
- bit_ctr_new = bit_ctr_reg + 1'b1;
- bit_ctr_we = 1'b1;
- end
- else if (entropy_ack)
- begin
- bit_ctr_new = 6'h00;
- bit_ctr_we = 1'b1;
- end
- end // entropy_ack_logic
-
-
- //----------------------------------------------------------------
// api_logic
//----------------------------------------------------------------
always @*
@@ -351,17 +189,17 @@ module avalanche_entropy(
ADDR_STATUS:
begin
- tmp_read_data = {31'h00000000, entropy_syn_reg};
+ tmp_read_data = {31'h00000000, entropy_valid};
end
ADDR_ENTROPY:
begin
- tmp_read_data = entropy_reg;
+ tmp_read_data = entropy_data;
end
ADDR_DELTA:
begin
- tmp_read_data = delta_reg;
+ tmp_read_data = delta;
end
default:
diff --git a/src/rtl/avalanche_entropy_core.v b/src/rtl/avalanche_entropy_core.v
index 5f217af..582b4b6 100644
--- a/src/rtl/avalanche_entropy_core.v
+++ b/src/rtl/avalanche_entropy_core.v
@@ -2,13 +2,20 @@
//
// avalanche_entropy_core.v
// ------------------------
-// Entropy provider core for an external entropy source based on
-// avalanche noise. (or any other source that ca toggle a single
-// bit input).
+// Core functionality for the entropy provider core based on
+// an external avalanche noise based source. (or any other source that
+// can toggle a single bit input).
//
-// Currently the design consists of a free running counter. At every
-// positive flank detected the LSB of the counter is pushed into
-// a 32bit shift register.
+// Currently the design consists of a counter running at clock speeed.
+// When a positive flank event is detected in the noise source the
+// current LSB value of the counter is pushed into a 32bit
+// entropy collection shift register.
+//
+// The core provides functionality to measure the time betwee
+// positive flank events counted as number of clock cycles. There
+// is also access ports for the collected entropy.
+//
+// No post-processing is currently performed done on the entropy.
//
//
// Author: Joachim Strombergson
@@ -47,30 +54,26 @@ module avalanche_entropy_core(
input wire reset_n,
input wire noise,
- output wire sampled_noise,
- output wire entropy,
- input wire entropy_ack,
- output wire entropy_syn,
+ input wire enable,
+
+ output wire entropy_enabled,
output wire [31 : 0] entropy_data,
+ output wire entropy_valid,
+ input wire entropy_ack,
- output wire [7 : 0] led,
- output wire [7 : 0] debug_data,
- output wire debug_clk,
+ output wire [31 : 0] delta,
- output wire [31 : 0] delta_data,
- output wire delta_clk
+ output wire [7 : 0] debug,
+ input wire debug_update
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter ADDR_STATUS = 8'h00;
- parameter ADDR_ENTROPY = 8'h10;
- parameter ADDR_DELTA = 8'h20;
-
- parameter DEBUG_DELAY = 32'h002c4b40;
+ parameter DEBUG_DELAY = 32'h002c4b40;
+ parameter MIN_ENTROPY_BITS = 6'h20;
//----------------------------------------------------------------
@@ -88,23 +91,22 @@ module avalanche_entropy_core(
reg [31 : 0] entropy_new;
reg entropy_we;
- reg entropy_syn_reg;
- reg entropy_syn_new;
+ reg entropy_valid_reg;
+ reg entropy_valid_new;
reg [5 : 0] bit_ctr_reg;
reg [5 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_we;
+ reg enable_reg;
+
reg [31 : 0] cycle_ctr_reg;
reg [31 : 0] cycle_ctr_new;
reg [31 : 0] delta_reg;
reg delta_we;
- reg delta_clk_reg;
- reg delta_clk_new;
-
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
@@ -123,16 +125,12 @@ module avalanche_entropy_core(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
- assign entropy_syn = entropy_syn_reg;
- assign entropy_data = entropy_reg;
-
- assign sampled_noise = noise_sample_reg;
- assign entropy = entropy_reg[0];
+ assign entropy_valid = entropy_valid_reg;
+ assign entropy_data = entropy_reg;
- assign delta_data = delta_reg;
- assign delta_clk = delta_clk_reg;
-
- assign debug = debug_reg;
+ assign delta = delta_reg;
+ assign debug = debug_reg;
+ assign entropy_enabled = enable_reg;
//----------------------------------------------------------------
@@ -146,18 +144,16 @@ module avalanche_entropy_core(
noise_sample_reg <= 1'b0;
flank0_reg <= 1'b0;
flank1_reg <= 1'b0;
- entropy_syn_reg <= 1'b0;
+ entropy_valid_reg <= 1'b0;
entropy_reg <= 32'h00000000;
entropy_bit_reg <= 1'b0;
bit_ctr_reg <= 6'h00;
- debug_ctr_reg <= 4'h0;
- debug_clk_reg <= 1'b0;
cycle_ctr_reg <= 32'h00000000;
delta_reg <= 32'h00000000;
- delta_clk_reg <= 1'b0;
debug_delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
debug_update_reg <= 0;
+ enable_reg <= 0;
end
else
begin
@@ -167,15 +163,14 @@ module avalanche_entropy_core(
flank0_reg <= noise_sample_reg;
flank1_reg <= flank0_reg;
- entropy_syn_reg <= entropy_syn_new;
-
+ entropy_valid_reg <= entropy_valid_new;
entropy_bit_reg <= ~entropy_bit_reg;
-
- delta_clk_reg <= delta_clk_new;
cycle_ctr_reg <= cycle_ctr_new;
debug_update_reg <= debug_update;
+ enable_reg <= enable;
+
if (delta_we)
begin
delta_reg <= cycle_ctr_reg;
@@ -186,11 +181,6 @@ module avalanche_entropy_core(
bit_ctr_reg <= bit_ctr_new;
end
- if (debug_ctr_we)
- begin
- debug_ctr_reg <= debug_ctr_new;
- end
-
if (entropy_we)
begin
entropy_reg <= entropy_new;
@@ -203,7 +193,7 @@ module avalanche_entropy_core(
if (debug_we)
begin
- debug_reg <= ent_shift_reg[7 : 0];
+ debug_reg <= entropy_reg[7 : 0];
end
end
end // reg_update
@@ -247,14 +237,12 @@ module avalanche_entropy_core(
entropy_new = 32'h00000000;
entropy_we = 1'b0;
bit_ctr_inc = 1'b0;
- debug_ctr_inc = 1'b0;
if ((flank0_reg) && (!flank1_reg))
begin
entropy_new = {entropy_reg[30 : 0], entropy_bit_reg};
entropy_we = 1'b1;
bit_ctr_inc = 1'b1;
- debug_ctr_inc = 1'b1;
end
end // entropy_collect
@@ -267,45 +255,17 @@ module avalanche_entropy_core(
always @*
begin : delta_logic
cycle_ctr_new = cycle_ctr_reg + 1'b1;
- delta_clk_new = 1'b0;
delta_we = 1'b0;
if ((flank0_reg) && (!flank1_reg))
begin
cycle_ctr_new = 32'h00000000;
- delta_clk_new = 1'b1;
delta_we = 1'b1;
end
end // delta_logic
//----------------------------------------------------------------
- // debug_ctr_logic
- //
- // The logic implements the counter needed to handle detection
- // that enough bis has been generated to output debug values.
- //----------------------------------------------------------------
- always @*
- begin : debug_ctr_logic
- debug_ctr_new = 4'h0;
- debug_ctr_we = 0;
- debug_clk_new = 0;
-
- if (debug_ctr_reg == 4'h8)
- begin
- debug_ctr_new = 4'h0;
- debug_ctr_we = 1;
- debug_clk_new = 1;
- end
- else if (debug_ctr_inc)
- begin
- debug_ctr_new = debug_ctr_reg + 1'b1;
- debug_ctr_we = 1;
- end
- end // debug_ctr_logic
-
-
- //----------------------------------------------------------------
// entropy_ack_logic
//
// The logic needed to handle detection that entropy has been
@@ -316,11 +276,11 @@ module avalanche_entropy_core(
begin : entropy_ack_logic
bit_ctr_new = 6'h00;
bit_ctr_we = 1'b0;
- entropy_syn_new = 1'b0;
+ entropy_valid_new = 1'b0;
- if (bit_ctr_reg == 6'h20)
+ if (bit_ctr_reg == MIN_ENTROPY_BITS)
begin
- entropy_syn_new = 1'b1;
+ entropy_valid_new = 1'b1;
end
if ((bit_ctr_inc) && (bit_ctr_reg < 6'h20))
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