[Cryptech-Commits] [core/chacha] 01/01: Update of ChaCha with fixes found during synthesis.
git at cryptech.is
git at cryptech.is
Fri Sep 26 13:02:43 UTC 2014
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joachim at secworks.se pushed a commit to branch master
in repository core/chacha.
commit 18e102cddcad3932c6e46ef0b294312799eee6b8
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri Sep 26 15:02:33 2014 +0200
Update of ChaCha with fixes found during synthesis.
---
src/rtl/chacha.v | 6 ++---
src/rtl/chacha_core.v | 62 +++++++++++++++++++++++++++++++++++++--------------
2 files changed, 48 insertions(+), 20 deletions(-)
diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v
index c83710d..8fd58f4 100644
--- a/src/rtl/chacha.v
+++ b/src/rtl/chacha.v
@@ -295,10 +295,10 @@ module chacha(
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
- // active low reset. All registers have write enable.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index 891ee55..c46b5b1 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -7,7 +7,7 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
@@ -63,8 +63,8 @@ module chacha_core(
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Datapath quartterround states names.
- parameter QR0 = 1'b0;
- parameter QR1 = 1'b1;
+ parameter STATE_QR0 = 1'b0;
+ parameter STATE_QR1 = 1'b1;
parameter NUM_ROUNDS = 4'h8;
@@ -225,6 +225,10 @@ module chacha_core(
reg data_out_valid_new;
reg data_out_valid_we;
+ reg ready_reg;
+ reg ready_new;
+ reg ready_we;
+
reg qr_ctr_reg;
reg qr_ctr_new;
reg qr_ctr_we;
@@ -295,8 +299,6 @@ module chacha_core(
wire [31 : 0] qr3_c_prim;
wire [31 : 0] qr3_d_prim;
- reg ready_wire;
-
//----------------------------------------------------------------
// Instantiation of the qr modules.
@@ -357,17 +359,18 @@ module chacha_core(
assign data_out_valid = data_out_valid_reg;
- assign ready = ready_wire;
+ assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
+ //
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
+ // All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
@@ -416,8 +419,9 @@ module chacha_core(
data_in_reg <= 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
data_out_reg <= 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
rounds_reg <= 4'h0;
+ ready_reg <= 1;
data_out_valid_reg <= 0;
- qr_ctr_reg <= QR0;
+ qr_ctr_reg <= STATE_QR0;
dr_ctr_reg <= 0;
block0_ctr_reg <= 32'h00000000;
block1_ctr_reg <= 32'h00000000;
@@ -551,6 +555,11 @@ module chacha_core(
data_out_reg <= data_out_new;
end
+ if (ready_we)
+ begin
+ ready_reg <= ready_new;
+ end
+
if (data_out_valid_we)
begin
data_out_valid_reg <= data_out_valid_new;
@@ -984,7 +993,7 @@ module chacha_core(
else if (update_state)
begin
case (qr_ctr_reg)
- QR0:
+ STATE_QR0:
begin
x0_new = qr0_a_prim;
x4_new = qr0_b_prim;
@@ -1023,7 +1032,7 @@ module chacha_core(
x15_we = 1;
end
- QR1:
+ STATE_QR1:
begin
x0_new = qr0_a_prim;
x5_new = qr0_b_prim;
@@ -1073,7 +1082,7 @@ module chacha_core(
always @*
begin : quarterround_mux
case (qr_ctr_reg)
- QR0:
+ STATE_QR0:
begin
qr0_a = x0_reg;
qr0_b = x4_reg;
@@ -1096,7 +1105,7 @@ module chacha_core(
qr3_d = x15_reg;
end
- QR1:
+ STATE_QR1:
begin
qr0_a = x0_reg;
qr0_b = x5_reg;
@@ -1216,25 +1225,35 @@ module chacha_core(
update_state = 0;
sample_params = 0;
update_output = 0;
+
qr_ctr_inc = 0;
qr_ctr_rst = 0;
+
dr_ctr_inc = 0;
dr_ctr_rst = 0;
+
block_ctr_inc = 0;
block_ctr_rst = 0;
+
data_in_we = 0;
- ready_wire = 0;
+
+ ready_new = 0;
+ ready_we = 0;
+
data_out_valid_new = 0;
data_out_valid_we = 0;
+
chacha_ctrl_new = CTRL_IDLE;
chacha_ctrl_we = 0;
+
case (chacha_ctrl_reg)
CTRL_IDLE:
begin
- ready_wire = 1;
if (init)
begin
+ ready_new = 0;
+ ready_we = 1;
data_in_we = 1;
sample_params = 1;
block_ctr_rst = 1;
@@ -1243,6 +1262,7 @@ module chacha_core(
end
end
+
CTRL_INIT:
begin
init_state = 1;
@@ -1252,11 +1272,12 @@ module chacha_core(
chacha_ctrl_we = 1;
end
+
CTRL_ROUNDS:
begin
update_state = 1;
qr_ctr_inc = 1;
- if (qr_ctr_reg == QR1)
+ if (qr_ctr_reg == STATE_QR1)
begin
dr_ctr_inc = 1;
if (dr_ctr_reg == (rounds_reg - 1))
@@ -1267,8 +1288,11 @@ module chacha_core(
end
end
+
CTRL_FINALIZE:
begin
+ ready_new = 1;
+ ready_we = 1;
update_output = 1;
data_out_valid_new = 1;
data_out_valid_we = 1;
@@ -1276,11 +1300,13 @@ module chacha_core(
chacha_ctrl_we = 1;
end
+
CTRL_DONE:
begin
- ready_wire = 1;
if (init)
begin
+ ready_new = 0;
+ ready_we = 1;
data_out_valid_new = 0;
data_out_valid_we = 1;
data_in_we = 1;
@@ -1291,6 +1317,8 @@ module chacha_core(
end
else if (next)
begin
+ ready_new = 0;
+ ready_we = 1;
data_out_valid_new = 0;
data_out_valid_we = 1;
data_in_we = 1;
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