[Cryptech-Commits] [core/uart] 01/01: Changed to asynch reset.
git at cryptech.is
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Fri Nov 7 11:02:06 UTC 2014
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joachim at secworks.se pushed a commit to branch master
in repository core/uart.
commit 149ffe9ade5492cc70f153788aa9ab063a46de8a
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri Nov 7 12:02:01 2014 +0100
Changed to asynch reset.
---
src/rtl/uart.v | 104 ++++++++++++++++++------------------
src/rtl/uart_core.v | 148 ++++++++++++++++++++++++++--------------------------
2 files changed, 126 insertions(+), 126 deletions(-)
diff --git a/src/rtl/uart.v b/src/rtl/uart.v
index 40a3f69..2a8de70 100644
--- a/src/rtl/uart.v
+++ b/src/rtl/uart.v
@@ -5,9 +5,9 @@
// Top level wrapper for the uart core.
//
// A simple universal asynchronous receiver/transmitter (UART)
-// interface. The interface contains 16 byte wide transmit and
-// receivea buffers and can handle start and stop bits. But in
-// general is rather simple. The primary purpose is as host
+// interface. The interface contains 16 byte wide transmit and
+// receivea buffers and can handle start and stop bits. But in
+// general is rather simple. The primary purpose is as host
// interface for the coretest design. The core also has a
// loopback mode to allow testing of a serial link.
//
@@ -19,30 +19,30 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -64,7 +64,7 @@ module uart(
input wire txd_syn,
input wire [7 : 0] txd_data,
output wire txd_ack,
-
+
// API interface.
input wire cs,
input wire we,
@@ -77,7 +77,7 @@ module uart(
output wire [7 : 0] debug
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -90,7 +90,7 @@ module uart(
parameter ADDR_BIT_RATE = 8'h10;
parameter ADDR_DATA_BITS = 8'h11;
parameter ADDR_STOP_BITS = 8'h12;
-
+
// Core ID constants.
parameter CORE_NAME0 = 32'h75617274; // "uart"
parameter CORE_NAME1 = 32'h20202020; // " "
@@ -105,8 +105,8 @@ module uart(
parameter DEFAULT_BIT_RATE = 16'd5208;
parameter DEFAULT_DATA_BITS = 4'h8;
parameter DEFAULT_STOP_BITS = 2'h1;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -121,8 +121,8 @@ module uart(
reg [1 : 0] stop_bits_reg;
reg [1 : 0] stop_bits_new;
reg stop_bits_we;
-
-
+
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
@@ -131,7 +131,7 @@ module uart(
wire core_rxd;
wire core_txd;
-
+
wire core_rxd_syn;
wire [7 : 0] core_rxd_data;
wire core_rxd_ack;
@@ -143,7 +143,7 @@ module uart(
reg [31 : 0] tmp_read_data;
reg tmp_error;
-
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
@@ -153,16 +153,16 @@ module uart(
assign rxd_syn = core_rxd_syn;
assign rxd_data = core_rxd_data;
assign core_rxd_ack = rxd_ack;
-
+
assign core_txd_syn = txd_syn;
assign core_txd_data = txd_data;
assign txd_ack = core_txd_ack;
-
+
assign read_data = tmp_read_data;
assign error = tmp_error;
assign debug = core_rxd_data;
-
+
//----------------------------------------------------------------
// core
@@ -177,7 +177,7 @@ module uart(
.bit_rate(bit_rate_reg),
.data_bits(data_bits_reg),
.stop_bits(stop_bits_reg),
-
+
// External data interface
.rxd(core_rxd),
.txd(core_txd),
@@ -186,22 +186,22 @@ module uart(
.rxd_syn(core_rxd_syn),
.rxd_data(core_rxd_data),
.rxd_ack(core_rxd_ack),
-
+
// Internal transmit interface.
.txd_syn(core_txd_syn),
.txd_data(core_txd_data),
.txd_ack(core_txd_ack)
);
-
+
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
- // active low reset. All registers have write enable.
+ // All registers are positive edge triggered with
+ // asynchronous active low reset.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
@@ -215,12 +215,12 @@ module uart(
begin
bit_rate_reg <= bit_rate_new;
end
-
+
if (data_bits_we)
begin
data_bits_reg <= data_bits_new;
end
-
+
if (stop_bits_we)
begin
stop_bits_reg <= stop_bits_new;
@@ -229,7 +229,7 @@ module uart(
end
end // reg_update
-
+
//----------------------------------------------------------------
// api
//
@@ -247,7 +247,7 @@ module uart(
stop_bits_we = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
-
+
if (cs)
begin
if (we)
@@ -271,7 +271,7 @@ module uart(
stop_bits_new = write_data[1 : 0];
stop_bits_we = 1;
end
-
+
default:
begin
tmp_error = 1;
@@ -301,7 +301,7 @@ module uart(
begin
tmp_read_data = CORE_VERSION;
end
-
+
ADDR_BIT_RATE:
begin
tmp_read_data = {16'h0000, bit_rate_reg};
@@ -316,7 +316,7 @@ module uart(
begin
tmp_read_data = {30'h0000000, stop_bits_reg};
end
-
+
default:
begin
tmp_error = 1;
@@ -325,7 +325,7 @@ module uart(
end
end
end
-
+
endmodule // uart
//======================================================================
diff --git a/src/rtl/uart_core.v b/src/rtl/uart_core.v
index 14a7ef7..eb62b17 100644
--- a/src/rtl/uart_core.v
+++ b/src/rtl/uart_core.v
@@ -3,9 +3,9 @@
// uart_core.v
// -----------
// A simple universal asynchronous receiver/transmitter (UART)
-// interface. The interface contains 16 byte wide transmit and
-// receivea buffers and can handle start and stop bits. But in
-// general is rather simple. The primary purpose is as host
+// interface. The interface contains 16 byte wide transmit and
+// receivea buffers and can handle start and stop bits. But in
+// general is rather simple. The primary purpose is as host
// interface for the coretest design. The core also has a
// loopback mode to allow testing of a serial link.
//
@@ -17,30 +17,30 @@
//
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -53,7 +53,7 @@ module uart_core(
input wire [15 : 0] bit_rate,
input wire [3 : 0] data_bits,
input wire [1 : 0] stop_bits,
-
+
// External data interface
input wire rxd,
output wire txd,
@@ -62,30 +62,30 @@ module uart_core(
output wire rxd_syn,
output [7 : 0] rxd_data,
input wire rxd_ack,
-
+
// Internal transmit interface.
input wire txd_syn,
input wire [7 : 0] txd_data,
output wire txd_ack
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter ERX_IDLE = 0;
+ parameter ERX_IDLE = 0;
parameter ERX_START = 1;
parameter ERX_BITS = 2;
parameter ERX_STOP = 3;
parameter ERX_SYN = 4;
- parameter ETX_IDLE = 0;
+ parameter ETX_IDLE = 0;
parameter ETX_ACK = 1;
parameter ETX_START = 2;
parameter ETX_BITS = 3;
parameter ETX_STOP = 4;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -109,15 +109,15 @@ module uart_core(
reg rxd_syn_reg;
reg rxd_syn_new;
reg rxd_syn_we;
-
+
reg [2 : 0] erx_ctrl_reg;
reg [2 : 0] erx_ctrl_new;
reg erx_ctrl_we;
-
+
reg txd_reg;
reg txd_new;
reg txd_we;
-
+
reg [7 : 0] txd_byte_reg;
reg [7 : 0] txd_byte_new;
reg txd_byte_we;
@@ -137,18 +137,18 @@ module uart_core(
reg txd_ack_reg;
reg txd_ack_new;
reg txd_ack_we;
-
+
reg [2 : 0] etx_ctrl_reg;
reg [2 : 0] etx_ctrl_new;
reg etx_ctrl_we;
-
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [15 : 0] half_bit_rate;
-
-
+
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
@@ -158,16 +158,16 @@ module uart_core(
assign txd_ack = txd_ack_reg;
assign half_bit_rate = {1'b0, bit_rate[15 : 1]};
-
-
+
+
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
- // active low reset. All registers have write enable.
+ // All registers are positive edge triggered with
+ // asynchronous active low reset.
//----------------------------------------------------------------
- always @ (posedge clk)
+ always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
@@ -177,7 +177,7 @@ module uart_core(
rxd_bitrate_ctr_reg <= 16'h0000;
rxd_syn_reg <= 0;
erx_ctrl_reg <= ERX_IDLE;
-
+
txd_reg <= 1;
txd_byte_reg <= 8'h00;
txd_bit_ctr_reg <= 4'h0;
@@ -205,22 +205,22 @@ module uart_core(
begin
rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
end
-
+
if (rxd_syn_we)
begin
rxd_syn_reg <= rxd_syn_new;
end
-
+
if (erx_ctrl_we)
begin
erx_ctrl_reg <= erx_ctrl_new;
end
-
+
if (txd_we)
begin
txd_reg <= txd_new;
end
-
+
if (txd_byte_we)
begin
txd_byte_reg <= txd_byte_new;
@@ -235,12 +235,12 @@ module uart_core(
begin
txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
end
-
+
if (txd_ack_we)
begin
txd_ack_reg <= txd_ack_new;
end
-
+
if (etx_ctrl_we)
begin
etx_ctrl_reg <= etx_ctrl_new;
@@ -252,7 +252,7 @@ module uart_core(
//----------------------------------------------------------------
// rxd_bit_ctr
//
- // Bit counter for receiving data on the external
+ // Bit counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
@@ -277,7 +277,7 @@ module uart_core(
//----------------------------------------------------------------
// rxd_bitrate_ctr
//
- // Bitrate counter for receiving data on the external
+ // Bitrate counter for receiving data on the external
// serial interface.
//----------------------------------------------------------------
always @*
@@ -303,7 +303,7 @@ module uart_core(
//----------------------------------------------------------------
// txd_bit_ctr
//
- // Bit counter for transmitting data on the external
+ // Bit counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
@@ -328,7 +328,7 @@ module uart_core(
//----------------------------------------------------------------
// txd_bitrate_ctr
//
- // Bitrate counter for transmitting data on the external
+ // Bitrate counter for transmitting data on the external
// serial interface.
//----------------------------------------------------------------
always @*
@@ -348,14 +348,14 @@ module uart_core(
txd_bitrate_ctr_we = 1;
end
end // txd_bitrate_ctr
-
+
//----------------------------------------------------------------
// external_rx_engine
//
- // Logic that implements the receive engine towards
- // the external interface. Detects incoming data, collects it,
- // if required checks parity and store correct data into
+ // Logic that implements the receive engine towards
+ // the external interface. Detects incoming data, collects it,
+ // if required checks parity and store correct data into
// the rx buffer.
//----------------------------------------------------------------
always @*
@@ -369,7 +369,7 @@ module uart_core(
rxd_syn_we = 0;
erx_ctrl_new = ERX_IDLE;
erx_ctrl_we = 0;
-
+
case (erx_ctrl_reg)
ERX_IDLE:
begin
@@ -405,7 +405,7 @@ module uart_core(
end
end
-
+
ERX_BITS:
begin
if (rxd_bitrate_ctr_reg < bit_rate)
@@ -425,7 +425,7 @@ module uart_core(
end
end
-
+
ERX_STOP:
begin
rxd_bitrate_ctr_inc = 1;
@@ -438,7 +438,7 @@ module uart_core(
end
end
-
+
ERX_SYN:
begin
if (rxd_ack)
@@ -450,7 +450,7 @@ module uart_core(
end
end
-
+
default:
begin
@@ -462,7 +462,7 @@ module uart_core(
//----------------------------------------------------------------
// external_tx_engine
//
- // Logic that implements the transmit engine towards
+ // Logic that implements the transmit engine towards
// the external interface.
//----------------------------------------------------------------
always @*
@@ -497,7 +497,7 @@ module uart_core(
end
end
-
+
ETX_ACK:
begin
if (!txd_syn)
@@ -510,7 +510,7 @@ module uart_core(
etx_ctrl_we = 1;
end
end
-
+
ETX_START:
begin
if (txd_bitrate_ctr_reg == bit_rate)
@@ -525,7 +525,7 @@ module uart_core(
end
end
-
+
ETX_BITS:
begin
if (txd_bitrate_ctr_reg < bit_rate)
@@ -535,7 +535,7 @@ module uart_core(
else
begin
txd_bitrate_ctr_rst = 1;
-
+
if (txd_bit_ctr_reg == data_bits)
begin
txd_new = 1;
@@ -551,8 +551,8 @@ module uart_core(
end
end
end
-
-
+
+
ETX_STOP:
begin
txd_bitrate_ctr_inc = 1;
@@ -563,14 +563,14 @@ module uart_core(
end
end
-
+
default:
begin
end
endcase // case (etx_ctrl_reg)
end // external_tx_engine
-
+
endmodule // uart
//======================================================================
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