[Cryptech-Commits] [core/novena_eim] 01/01: Mostly working.
git at cryptech.is
git at cryptech.is
Tue Nov 4 21:51:38 UTC 2014
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch master
in repository core/novena_eim.
commit f74993fa69ae17fdbdf3963c399295a4d305d5bd
Author: Paul Selkirk <paul at psgd.org>
Date: Tue Nov 4 16:50:48 2014 -0500
Mostly working.
Rebased on novena-gpbbp-fpga (verilog) and novena-gpbb-example (c).
Integrated with hash cores and coretest framework
Added Makefile and pre-built bitfile.
Ported hash_tester.c.
---
README.md | 19 +-
build/Makefile | 28 +
build/novena_eim.bit | Bin 0 -> 1484504 bytes
build/novena_eim.bmm | 0
build/{novena.ucf => novena_eim.ucf} | 547 ++++++-----
build/novena_eim.xise | 881 ++++++++---------
build/xilinx.mk | 176 ++++
build/xilinx.opt | 42 +
src/rtl/coretest_hashes.v | 319 ++++++
.../ddr3_clkgen.v => clk_dll/clk_dll.v} | 320 +++---
src/rtl/ip/eimram/eimram.v | 186 ----
src/rtl/ip/eimram/eimram.xci | 146 ---
src/rtl/ip/eimram/eimram.xco | 108 --
src/rtl/ip/eimram/eimram.xise | 73 --
src/rtl/ip/nandadr_fifo/nandadr_fifo.v | 491 ----------
src/rtl/ip/nandadr_fifo/nandadr_fifo.xci | 378 -------
src/rtl/ip/nandadr_fifo/nandadr_fifo.xco | 213 ----
src/rtl/ip/nandadr_fifo/nandadr_fifo.xise | 73 --
src/rtl/ip/uk_fifo/uk_fifo.v | 491 ----------
src/rtl/ip/uk_fifo/uk_fifo.xci | 378 -------
src/rtl/ip/uk_fifo/uk_fifo.xco | 213 ----
src/rtl/ip/uk_fifo/uk_fifo.xise | 73 --
src/rtl/nand_log_tb.v | 225 -----
src/rtl/novena_fpga.v | 826 +++++++---------
src/rtl/romulator_ddr3_tb.v | 802 ---------------
src/rtl/romulator_tb.v | 370 -------
src/rtl/spi_eeprom.v | 255 -----
src/rtl/spi_eeprom_tb.v | 317 ------
src/sw/Makefile | 2 +-
src/sw/eim.c | 285 ------
src/sw/eim.h | 46 -
src/sw/gpio.c | 163 ----
src/sw/gpio.h | 21 -
src/sw/hash_tester.c | 962 ++++++++++++++++++
src/sw/novena-fpga.c | 1031 --------------------
35 files changed, 2802 insertions(+), 7658 deletions(-)
diff --git a/README.md b/README.md
index eeb0748..88ba501 100644
--- a/README.md
+++ b/README.md
@@ -5,12 +5,19 @@ The coretest system for the Novena PVT1, over EIM.
## Introduction ##
-src/rtl is a fork of https://github.com/bunnie/novena-spi-romulator.git
-with coregen files from https://github.com/bunnie/novena-sd-fpga.git
+src/rtl is a fork of https://github.com/bunnie/novena-gpbb-fpga.git
-src/sw is a fork of https://github.com/bunnie/novena-fpga-drivers.git
+Out of perversity, I support both command-line and ISE builds.
+To build, do one of the following:
+1) Go to build/ and run 'make'. (Depending on your Xilinx install, you
+may need to change the 'isedir' line in Makefile.)
+2) Load novena_eim.xise in ISE.
+
+src/sw is based on https://github.com/bunnie/novena-gpbb-example.git
+
+To build, go to src/sw/ and run 'make'. Or just run gcc at hash_tester.c
## Status ##
-***(2014-09-30)***
-Builds, but fails tests with novena-fpga.
-No coretest integration as yet.
+***(2014-11-04)***
+Mostly works with the hash cores at 25MHz.
+Investigating failures at higher clock speeds.
diff --git a/build/Makefile b/build/Makefile
new file mode 100644
index 0000000..081333d
--- /dev/null
+++ b/build/Makefile
@@ -0,0 +1,28 @@
+project = novena_eim
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_fpga
+isedir = /opt/Xilinx/14.3/ISE_DS
+xil_env = . $(isedir)/settings64.sh
+
+vfiles = ../../sha1/src/rtl/sha1.v \
+ ../../sha1/src/rtl/sha1_core.v \
+ ../../sha1/src/rtl/sha1_w_mem.v \
+ ../../sha256/src/rtl/sha256.v \
+ ../../sha256/src/rtl/sha256_core.v \
+ ../../sha256/src/rtl/sha256_k_constants.v \
+ ../../sha256/src/rtl/sha256_w_mem.v \
+ ../../sha512/src/rtl/sha512.v \
+ ../../sha512/src/rtl/sha512_core.v \
+ ../../sha512/src/rtl/sha512_h_constants.v \
+ ../../sha512/src/rtl/sha512_k_constants.v \
+ ../../sha512/src/rtl/sha512_w_mem.v \
+ ../src/rtl/common/sync_reset.v \
+ ../src/rtl/coretest_hashes.v \
+ ../src/rtl/ip/bclk_dll/bclk_dll.v \
+ ../src/rtl/ip/clk_dll/clk_dll.v \
+ ../src/rtl/ip/dcm_delay/dcm_delay.v \
+ ../src/rtl/novena_fpga.v
+
+include xilinx.mk
diff --git a/build/novena_eim.bit b/build/novena_eim.bit
new file mode 100644
index 0000000..e9db564
Binary files /dev/null and b/build/novena_eim.bit differ
diff --git a/build/novena_eim.bmm b/build/novena_eim.bmm
new file mode 100644
index 0000000..e69de29
diff --git a/build/novena.ucf b/build/novena_eim.ucf
similarity index 56%
rename from build/novena.ucf
rename to build/novena_eim.ucf
index dc2f32d..2246f61 100755
--- a/build/novena.ucf
+++ b/build/novena_eim.ucf
@@ -13,21 +13,20 @@ OFFSET = IN 4125 ps VALID 4750 ps BEFORE "bclk";
#5200 ps is the true limit
OFFSET = OUT 5100 ps AFTER "bclk";
-## 37ns / 2 = 18.5. 18.5 - 7ns c-q = 11.5ns. Give 8ns to tpd of buffers -> 3.5ns
-OFFSET = IN 18500 ps VALID 3500ps BEFORE "spiclk";
-OFFSET = OUT 3500 ps after "spiclk";
-NET "spiclk" TNM_NET = "spiclk_tnm";
-TIMESPEC TS_spiclk = PERIOD "spiclk_tnm" 37 ns;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
-#NET "u_ddr3_if/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
-#NET "u_ddr3_if/c?_pll_lock" TIG;
-#INST "u_ddr3_if/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
-# NET "ddr3_reset_local" TIG; ## removed
-
NET "eim_d_t*" TIG;
+
+#NET "reg_wo_40010/state[*]" TIG; # ignore fast timing on expansion-side GPIO
+#NET "reg_wo_40012/state[*]" TIG;
+#NET "reg_ro_41010/state[*]" TIG;
+#NET "reg_ro_41012/state[*]" TIG;
+
+##################################################################################
+# Force ODDR's to meet output timing constraint
+##################################################################################
INST "oddr2_eim0" IOB =FORCE;
INST "oddr2_eim1" IOB =FORCE;
INST "oddr2_eim2" IOB =FORCE;
@@ -45,63 +44,41 @@ INST "oddr2_eimD" IOB =FORCE;
INST "oddr2_eimE" IOB =FORCE;
INST "oddr2_eimF" IOB =FORCE;
-# eliminate false timing path of bclk to nand data output. Actual path is
-# from nand_re and has at a minimum 15ns available, typically much much more
-#NET "romulator_ddr3/nand_dout[*]" TIG;
-
-#NET "reg_wo_40102/state[*]" TIG;
-#NET "reg_wo_40100/state[*]" TIG;
-#NET "reg_ro_41010/state[*]" TIG;
-# don't sweat the R/B signal, we have tons of margin on it
-
-#Please uncomment the below TIG if used in a design which enables self-refresh mode
-#NET "u_ddr3_if/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
-
-
-############################################################################
-## Memory Controller 1
-## Memory Device: DDR3_SDRAM->MT41J128M16XX-125
-## Frequency: 400 MHz
-## Time Period: 2500 ps
-## Supported Part Numbers: MT41J128M16HA-125
-############################################################################
+#INST "bclk_o_fbk" LOC="REG_T_X43Y140";
+#INST "bclk_o_fbk" LOC="BUFIO2_X2Y29";
############################################################################
## Clock constraints
############################################################################
-#NET "u_ddr3_if/memc1_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK1";
-############################################################################
-
NET "clk" TNM_NET = "clk_tnm";
NET "bclk" TNM_NET = "bclk_tnm";
TIMESPEC TS_clk = PERIOD "clk_tnm" 50 MHz;
TIMESPEC TS_bclk = PERIOD "bclk_tnm" 133 MHz;
-### a failed experiment to make timing close using DCM explicit phase shifts
-#NET "bclk_early" TNM_NET = "bclkp90_tnm";
-#TIMESPEC TS_bclkp90 = PERIOD "bclkp90_tnm" TS_bclk PHASE + 1870 ps; # spec in the phase shift manually
-#OFFSET = OUT 6870 ps AFTER "bclk_early"; # add in the phase shift manually for this clock
NET "APOPTOSIS" LOC = K1;
NET "APOPTOSIS" IOSTANDARD = LVCMOS33;
-NET "AUD6_TFS" LOC = A4;
-NET "AUD6_TFS" IOSTANDARD = LVCMOS33;
-NET "AUD6_TXC" LOC = B4;
-NET "AUD6_TXC" IOSTANDARD = LVCMOS33;
-NET "AUD6_TXD" LOC = A6;
-NET "AUD6_TXD" IOSTANDARD = LVCMOS33;
-NET "AUD_MCLK" LOC = H6;
-NET "AUD_MCLK" IOSTANDARD = LVCMOS33;
-NET "AUD_MIC_CLK" LOC = G3;
-NET "AUD_MIC_CLK" IOSTANDARD = LVCMOS33;
-NET "AUD_MIC_DAT" LOC = C5;
-NET "AUD_MIC_DAT" IOSTANDARD = LVCMOS33;
-
-NET "BATT_NRST" LOC = N1;
-NET "BATT_NRST" IOSTANDARD = LVCMOS33;
-NET "BATT_REFLASH_ALRT" LOC = N2;
-NET "BATT_REFLASH_ALRT" IOSTANDARD = LVCMOS33;
+# AUD6_TFS
+# NET "DEL_CONT" LOC = A4;
+# NET "DEL_CONT" IOSTANDARD = LVCMOS33;
+# AUD6_TXC
+# NET "DEL_RST_L" LOC = B4;
+# NET "DEL_RST_L" IOSTANDARD = LVCMOS33;
+# NET "AUD6_TXD" LOC = A6;
+# NET "AUD6_TXD" IOSTANDARD = LVCMOS33;
+# NET "AUD_MCLK" LOC = H6;
+# NET "AUD_MCLK" IOSTANDARD = LVCMOS33;
+# AUD_MIC_CLK
+#NET "ZEROVEN" LOC = G3;
+#NET "ZEROVEN" IOSTANDARD = LVCMOS33;
+# NET "AUD_MIC_DAT" LOC = C5;
+# NET "AUD_MIC_DAT" IOSTANDARD = LVCMOS33;
+
+# NET "BATT_NRST" LOC = N1;
+# NET "BATT_NRST" IOSTANDARD = LVCMOS33;
+# NET "BATT_REFLASH_ALRT" LOC = N2;
+# NET "BATT_REFLASH_ALRT" IOSTANDARD = LVCMOS33;
NET "CLK2_N" LOC = H1;
NET "CLK2_N" IOSTANDARD = LVDS_33;
@@ -110,23 +87,28 @@ NET "CLK2_P" LOC = H2;
NET "CLK2_P" IOSTANDARD = LVDS_33;
NET "CLK2_P" DIFF_TERM = "TRUE";
-NET "DDC_SCL" LOC = J6;
-NET "DDC_SCL" IOSTANDARD = LVCMOS33;
-NET "DDC_SDA" LOC = F2;
-NET "DDC_SDA" IOSTANDARD = LVCMOS33;
-
-NET "ECSPI3_MISO" LOC = A3;
-NET "ECSPI3_MISO" IOSTANDARD = LVCMOS33;
-# R13
-NET "ECSPI3_MOSI" LOC = A2;
-NET "ECSPI3_MOSI" IOSTANDARD = LVCMOS33;
-NET "ECSPI3_RDY" LOC = A5;
-NET "ECSPI3_RDY" IOSTANDARD = LVCMOS33;
-# R15
-NET "ECSPI3_SCLK" LOC = D9;
-NET "ECSPI3_SCLK" IOSTANDARD = LVCMOS33;
-NET "ECSPI3_SS2" LOC = B3;
-NET "ECSPI3_SS2" IOSTANDARD = LVCMOS33;
+# NET "DDC_SCL" LOC = J6;
+# NET "DDC_SCL" IOSTANDARD = LVCMOS33;
+# NET "DDC_SDA" LOC = F2;
+# NET "DDC_SDA" IOSTANDARD = LVCMOS33;
+
+# ECSPI3_MISO
+#NET "SPI1_MISO" LOC = A3;
+#NET "SPI1_MISO" IOSTANDARD = LVCMOS33;
+# # R13
+# ECSPI3_MOSI
+#NET "SPI1_MOSI" LOC = A2;
+#NET "SPI1_MOSI" IOSTANDARD = LVCMOS33;
+# ECSPI3_RDY
+#NET "SPI1_DELI_SEL" LOC = A5;
+#NET "SPI1_DELI_SEL" IOSTANDARD = LVCMOS33;
+# # R15
+# ECSPI3_SCLK
+#NET "SPI1_SCLK" LOC = D9;
+#NET "SPI1_SCLK" IOSTANDARD = LVCMOS33;
+# ECSPI3_SS2
+#NET "SAMPEN" LOC = B3;
+#NET "SAMPEN" IOSTANDARD = LVCMOS33;
NET "EIM_BCLK" LOC = C9;
NET "EIM_BCLK" IOSTANDARD = LVCMOS33;
@@ -137,150 +119,171 @@ NET "EIM_CS[1]" IOSTANDARD = LVCMOS33;
NET "EIM_DA[0]" LOC = G9;
NET "EIM_DA[0]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[0]" SLEW = FAST;
+NET "EIM_DA[0]" SLEW = SLOW;
NET "EIM_DA[1]" LOC = A10;
NET "EIM_DA[1]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[1]" SLEW = FAST;
+NET "EIM_DA[1]" SLEW = SLOW;
NET "EIM_DA[2]" LOC = F9;
NET "EIM_DA[2]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[2]" SLEW = FAST;
+NET "EIM_DA[2]" SLEW = SLOW;
NET "EIM_DA[3]" LOC = B9;
NET "EIM_DA[3]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[3]" SLEW = FAST;
+NET "EIM_DA[3]" SLEW = SLOW;
NET "EIM_DA[4]" LOC = E13;
NET "EIM_DA[4]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[4]" SLEW = FAST;
+NET "EIM_DA[4]" SLEW = SLOW;
NET "EIM_DA[5]" LOC = F13;
NET "EIM_DA[5]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[5]" SLEW = FAST;
+NET "EIM_DA[5]" SLEW = SLOW;
NET "EIM_DA[6]" LOC = A9;
NET "EIM_DA[6]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[6]" SLEW = FAST;
+NET "EIM_DA[6]" SLEW = SLOW;
NET "EIM_DA[7]" LOC = A8;
NET "EIM_DA[7]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[7]" SLEW = FAST;
+NET "EIM_DA[7]" SLEW = SLOW;
NET "EIM_DA[8]" LOC = B8;
NET "EIM_DA[8]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[8]" SLEW = FAST;
+NET "EIM_DA[8]" SLEW = SLOW;
NET "EIM_DA[9]" LOC = D8;
NET "EIM_DA[9]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[9]" SLEW = FAST;
+NET "EIM_DA[9]" SLEW = SLOW;
NET "EIM_DA[10]" LOC = D11;
NET "EIM_DA[10]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[10]" SLEW = FAST;
+NET "EIM_DA[10]" SLEW = SLOW;
NET "EIM_DA[11]" LOC = C8;
NET "EIM_DA[11]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[11]" SLEW = FAST;
+NET "EIM_DA[11]" SLEW = SLOW;
NET "EIM_DA[12]" LOC = C7;
NET "EIM_DA[12]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[12]" SLEW = FAST;
+NET "EIM_DA[12]" SLEW = SLOW;
+
NET "EIM_DA[13]" LOC = C11;
NET "EIM_DA[13]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[13]" SLEW = FAST;
+NET "EIM_DA[13]" SLEW = SLOW;
+
NET "EIM_DA[14]" LOC = C4;
NET "EIM_DA[14]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[14]" SLEW = FAST;
+NET "EIM_DA[14]" SLEW = SLOW;
NET "EIM_DA[15]" LOC = B6;
NET "EIM_DA[15]" IOSTANDARD = LVCMOS33;
-NET "EIM_DA[15]" SLEW = FAST;
+NET "EIM_DA[15]" SLEW = SLOW;
+# EIM_A16
NET "EIM_A[16]" LOC = A11;
NET "EIM_A[16]" IOSTANDARD = LVCMOS33;
+NET "EIM_A[16]" SLEW = SLOW;
+
+# EIM_A17
NET "EIM_A[17]" LOC = B12;
NET "EIM_A[17]" IOSTANDARD = LVCMOS33;
+NET "EIM_A[17]" SLEW = SLOW;
+# EIM_A18
NET "EIM_A[18]" LOC = D14;
NET "EIM_A[18]" IOSTANDARD = LVCMOS33;
+NET "EIM_A[18]" SLEW = SLOW;
+# EIM_LBA
NET "EIM_LBA" LOC = B14;
NET "EIM_LBA" IOSTANDARD = LVCMOS33;
+NET "EIM_LBA" SLEW = SLOW;
NET "EIM_OE" LOC = C10;
NET "EIM_OE" IOSTANDARD = LVCMOS33;
+NET "EIM_OE" SLEW = SLOW;
NET "EIM_RW" LOC = C14;
+NET "EIM_RW" SLEW = SLOW;
NET "EIM_RW" IOSTANDARD = LVCMOS33;
-NET "EIM_WAIT" LOC = A7;
-NET "EIM_WAIT" IOSTANDARD = LVCMOS33;
-#NET "FPGA_DONE" LOC = V17;
-#NET "FPGA_DONE" IOSTANDARD = LVCMOS33;
-#NET "FPGA_HSWAPEN" LOC = D4;
-#NET "FPGA_HSWAPEN" IOSTANDARD = LVCMOS33;
-#NET "FPGA_INIT_N" LOC = U3;
-#NET "FPGA_INIT_N" IOSTANDARD = TMDS_33;
+#NET "LED3" LOC = C14;
+#NET "LED3" IOSTANDARD = LVCMOS33;
+# NET "EIM_WAIT" LOC = A7;
+# NET "EIM_WAIT" IOSTANDARD = LVCMOS33;
+
+# #NET "FPGA_DONE" LOC = V17;
+# #NET "FPGA_DONE" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_HSWAPEN" LOC = D4;
+# #NET "FPGA_HSWAPEN" IOSTANDARD = LVCMOS33;
+# FPGA_INIT_N
+#NET "LED2" LOC = U3;
+#NET "LED2" IOSTANDARD = LVCMOS33;
NET "FPGA_LED2" LOC = A16;
NET "FPGA_LED2" IOSTANDARD = LVCMOS33;
-
-NET "FPGA_LSPI_CLK" LOC = D3;
-NET "FPGA_LSPI_CLK" IOSTANDARD = LVCMOS33;
-NET "FPGA_LSPI_CS" LOC = D1;
-NET "FPGA_LSPI_CS" IOSTANDARD = LVCMOS33;
-NET "FPGA_LSPI_HOLD" LOC = E3;
-NET "FPGA_LSPI_HOLD" IOSTANDARD = LVCMOS33;
-NET "FPGA_LSPI_MISO" LOC = D2;
-NET "FPGA_LSPI_MISO" IOSTANDARD = LVCMOS33;
-NET "FPGA_LSPI_MOSI" LOC = C2;
-NET "FPGA_LSPI_MOSI" IOSTANDARD = LVCMOS33;
-NET "FPGA_LSPI_WP" LOC = C1;
-NET "FPGA_LSPI_WP" IOSTANDARD = LVCMOS33;
-
-#NET "FPGA_M0" LOC = T15;
-#NET "FPGA_M0" IOSTANDARD = LVCMOS33;
-#NET "FPGA_M1" LOC = N12;
-#NET "FPGA_M1" IOSTANDARD = LVCMOS33;
-
-#NET "FPGA_RESET_N" LOC = V2;
-#NET "FPGA_RESET_N" IOSTANDARD = TMDS_33;
-#NET "FPGA_SUSPEND" LOC = R16;
-#NET "FPGA_SUSPEND" IOSTANDARD = LVCMOS33;
-#NET "FPGA_TCK" LOC = A17;
-#NET "FPGA_TCK" IOSTANDARD = LVCMOS33;
-#NET "FPGA_TDI" LOC = D15;
-#NET "FPGA_TDI" IOSTANDARD = LVCMOS33;
-#NET "FPGA_TDO" LOC = D16;
-#NET "FPGA_TDO" IOSTANDARD = LVCMOS33;
-#NET "FPGA_TMS" LOC = B18;
-#NET "FPGA_TMS" IOSTANDARD = LVCMOS33;
-
-# NET "GND" LOC = A1;# A18 B7 B13 C3 C16 D5 D10 E15 G2 G5 G12 G17 H8 H10 J4 J9 J11 J15 K8 K10 L9 L11 M2 M6 M17 N13 R1 R4 R9 R14 R18 T16 U6 U12 V1 V18
-# NET "GND" IOSTANDARD = LVCMOS33;
-
-NET "I2C3_SCL" LOC = P4;
-NET "I2C3_SCL" IOSTANDARD = LVCMOS33;
-NET "I2C3_SDA" LOC = P3;
-NET "I2C3_SDA" IOSTANDARD = LVCMOS33;
-
-# NET "P1_2V" LOC = G7;# H9 H11 J8 J10 K9 K11 L8 L10 M7 M12
-# NET "P1_2V" IOSTANDARD = LVCMOS33;
-# NET "P3_3V_DELAYED" LOC = B1;# B5 B10 B15 B17 D7 D13 E2 E5 E9 E10 E14 E17 G4 G10 G15 J2 J5 J12 J14 J17 K7 M4 M9 M15 P5 P9 P10 P14 R2 R6 R12 R17 U4 U9 U14
-# NET "P3_3V_DELAYED" IOSTANDARD = LVCMOS33;
+NET "FPGA_LED2" SLEW = SLOW;
+
+# NET "FPGA_LSPI_CLK" LOC = D3;
+# NET "FPGA_LSPI_CLK" IOSTANDARD = LVCMOS33;
+# NET "FPGA_LSPI_CS" LOC = D1;
+# NET "FPGA_LSPI_CS" IOSTANDARD = LVCMOS33;
+# NET "FPGA_LSPI_HOLD" LOC = E3;
+# NET "FPGA_LSPI_HOLD" IOSTANDARD = LVCMOS33;
+# NET "FPGA_LSPI_MISO" LOC = D2;
+# NET "FPGA_LSPI_MISO" IOSTANDARD = LVCMOS33;
+# NET "FPGA_LSPI_MOSI" LOC = C2;
+# NET "FPGA_LSPI_MOSI" IOSTANDARD = LVCMOS33;
+# NET "FPGA_LSPI_WP" LOC = C1;
+# NET "FPGA_LSPI_WP" IOSTANDARD = LVCMOS33;
+
+# #NET "FPGA_M0" LOC = T15;
+# #NET "FPGA_M0" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_M1" LOC = N12;
+# #NET "FPGA_M1" IOSTANDARD = LVCMOS33;
+
+# #NET "FPGA_RESET_N" LOC = V2;
+# #NET "FPGA_RESET_N" IOSTANDARD = TMDS_33;
+# #NET "FPGA_SUSPEND" LOC = R16;
+# #NET "FPGA_SUSPEND" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_TCK" LOC = A17;
+# #NET "FPGA_TCK" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_TDI" LOC = D15;
+# #NET "FPGA_TDI" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_TDO" LOC = D16;
+# #NET "FPGA_TDO" IOSTANDARD = LVCMOS33;
+# #NET "FPGA_TMS" LOC = B18;
+# #NET "FPGA_TMS" IOSTANDARD = LVCMOS33;
+
+# # NET "GND" LOC = A1;# A18 B7 B13 C3 C16 D5 D10 E15 G2 G5 G12 G17 H8 H10 J4 J9 J11 J15 K8 K10 L9 L11 M2 M6 M17 N13 R1 R4 R9 R14 R18 T16 U6 U12 V1 V18
+# # NET "GND" IOSTANDARD = LVCMOS33;
+
+#NET "I2C3_SCL" LOC = P4;
+#NET "I2C3_SCL" IOSTANDARD = LVCMOS33;
+#NET "I2C3_SDA" LOC = P3;
+#NET "I2C3_SDA" IOSTANDARD = LVCMOS33;
+
+# # NET "P1_2V" LOC = G7;# H9 H11 J8 J10 K9 K11 L8 L10 M7 M12
+# # NET "P1_2V" IOSTANDARD = LVCMOS33;
+# # NET "P3_3V_DELAYED" LOC = B1;# B5 B10 B15 B17 D7 D13 E2 E5 E9 E10 E14 E17 G4 G10 G15 J2 J5 J12 J14 J17 K7 M4 M9 M15 P5 P9 P10 P14 R2 R6 R12 R17 U4 U9 U14
+# # NET "P3_3V_DELAYED" IOSTANDARD = LVCMOS33;
NET "RESETBMCU" LOC = F1;
NET "RESETBMCU" IOSTANDARD = LVCMOS33;
-NET "SMB_SCL" LOC = N3;
-NET "SMB_SCL" IOSTANDARD = LVCMOS33;
-NET "SMB_SDA" LOC = N4;
-NET "SMB_SDA" IOSTANDARD = LVCMOS33;
-
-NET "UART4_CTS" LOC = U1;
-NET "UART4_CTS" IOSTANDARD = LVCMOS33;
-NET "UART4_RTS" LOC = U2;
-NET "UART4_RTS" IOSTANDARD = LVCMOS33;
-NET "UART4_RXD" LOC = T1;
-NET "UART4_RXD" IOSTANDARD = LVCMOS33;
-NET "UART4_TXD" LOC = P1;
-NET "UART4_TXD" IOSTANDARD = LVCMOS33;
-
-#NET "UIM_CLK" LOC = B16;
-#NET "UIM_CLK" IOSTANDARD = LVCMOS33;
-#NET "UIM_DATA" LOC = A12;
-#NET "UIM_DATA" IOSTANDARD = LVCMOS33;
-#NET "UIM_PWR" LOC = C18;
-#NET "UIM_PWR" IOSTANDARD = SSTL15_II;
-#NET "UIM_PWRON" LOC = A14;
-#NET "UIM_PWRON" IOSTANDARD = LVCMOS33;
-#NET "UIM_RESET" LOC = C15;
-#NET "UIM_RESET" IOSTANDARD = LVCMOS33;
+# NET "SMB_SCL" LOC = N3;
+# NET "SMB_SCL" IOSTANDARD = LVCMOS33;
+# NET "SMB_SDA" LOC = N4;
+# NET "SMB_SDA" IOSTANDARD = LVCMOS33;
+
+# NET "UART4_CTS" LOC = U1;
+# NET "UART4_CTS" IOSTANDARD = LVCMOS33;
+# NET "UART4_RTS" LOC = U2;
+# NET "UART4_RTS" IOSTANDARD = LVCMOS33;
+# NET "UART4_RXD" LOC = T1;
+# NET "UART4_RXD" IOSTANDARD = LVCMOS33;
+# NET "UART4_TXD" LOC = P1;
+# NET "UART4_TXD" IOSTANDARD = LVCMOS33;
+
+# UIM_CLK
+#NET "MODES" LOC = B16;
+#NET "MODES" IOSTANDARD = LVCMOS33;
+# UIM_DATA
+#NET "ENC_SW" LOC = A12;
+#NET "ENC_SW" IOSTANDARD = LVCMOS33;
+# #NET "UIM_PWR" LOC = C18;
+# #NET "UIM_PWR" IOSTANDARD = SSTL15_II;
+# #NET "UIM_PWRON" LOC = A14;
+# #NET "UIM_PWRON" IOSTANDARD = LVCMOS33;
+# UIM_RESET
+#NET "SW_BACKUP" LOC = C15;
+#NET "SW_BACKUP" IOSTANDARD = LVCMOS33;
##############
# DDR3
@@ -472,46 +475,73 @@ NET "UART4_TXD" IOSTANDARD = LVCMOS33;
##############
# I/O connector
##############
-# NET "F_DX0" LOC = K6;
-# NET "F_DX0" IOSTANDARD = LVCMOS33;
-# NET "F_DX0" SLEW = SLOW;
+#NET "F_DX0" LOC = K6;
+#NET "F_DX0" IOSTANDARD = LVCMOS33;
+#NET "F_DX0" SLEW = SLOW;
+# NET "F_DX0" PULLUP;
+
#NET "F_DX1" LOC = L7;
#NET "F_DX1" IOSTANDARD = LVCMOS33;
-#NET "F_DX1" SLEW = FAST;
-# NET "F_DX2" LOC = H3;
-# NET "F_DX2" IOSTANDARD = LVCMOS33;
-# NET "F_DX2" SLEW = SLOW;
-# NET "F_DX3" LOC = H4;
-# NET "F_DX3" IOSTANDARD = LVCMOS33;
-# NET "F_DX3" SLEW = SLOW;
+#NET "F_DX1" SLEW = SLOW;
+
+#NET "F_DX2" LOC = H3;
+#NET "F_DX2" IOSTANDARD = LVCMOS33;
+#NET "F_DX2" SLEW = SLOW;
+
+#NET "F_DX3" LOC = H4;
+#NET "F_DX3" IOSTANDARD = LVCMOS33;
+#NET "F_DX3" SLEW = SLOW;
+# NET "F_DX3" PULLUP;
+
# NET "F_DX[4]" LOC = J1;
# NET "F_DX[5]" LOC = J3;
-# NET "F_DX[6]" LOC = L3;
-# NET "F_DX[7]" LOC = L4;
-# NET "F_DX[8]" LOC = K2;
-# NET "F_DX11" LOC = M1;
-# NET "F_DX11" IOSTANDARD = LVCMOS33;
-# NET "F_DX11" SLEW = SLOW;
-# NET "F_DX[12]" LOC = M3;
-# NET "F_DX[13]" LOC = P2;
-# NET "F_DX14" LOC = T2;
-# NET "F_DX14" IOSTANDARD = LVCMOS33;
-# NET "F_DX14" SLEW = SLOW;
-# NET "F_DX[15]" LOC = M5;
+#NET "F_DX6" LOC = L3;
+#NET "F_DX6" IOSTANDARD = LVCMOS33;
+#NET "F_DX6" SLEW = SLOW;
+
+#NET "F_DX7" LOC = L4;
+#NET "F_DX7" IOSTANDARD = LVCMOS33;
+#NET "F_DX7" SLEW = SLOW;
+
+# NET "F_DX8" LOC = K2;
+# NET "F_DX8" IOSTANDARD = LVCMOS33;
+# NET "F_DX8" SLEW = SLOW;
+
+#NET "F_DX11" LOC = M1;
+#NET "F_DX11" IOSTANDARD = LVCMOS33;
+#NET "F_DX11" SLEW = SLOW;
+#NET "F_DX12" LOC = M3;
+#NET "F_DX12" IOSTANDARD = LVCMOS33;
+#NET "F_DX12" SLEW = SLOW;
+
+#NET "F_DX13" LOC = P2;
+#NET "F_DX13" IOSTANDARD = LVCMOS33;
+#NET "F_DX13" SLEW = SLOW;
+
+#NET "F_DX14" LOC = T2;
+#NET "F_DX14" IOSTANDARD = LVCMOS33;
+#NET "F_DX14" SLEW = SLOW;
+
+#NET "F_DX15" LOC = M5;
+#NET "F_DX15" IOSTANDARD = LVCMOS33;
+#NET "F_DX15" SLEW = SLOW;
+
# NET "F_DX[16]" LOC = L6;
-# NET "F_DX17" LOC = G1;
-# NET "F_DX17" IOSTANDARD = LVCMOS33;
-# NET "F_DX17" SLEW = SLOW;
-NET "F_DX18" LOC = H7;
-NET "F_DX18" IOSTANDARD = LVCMOS33;
-NET "F_DX18" SLEW = SLOW;
-
-# NET "F_LVDS_N0" LOC = P6;
-# NET "F_LVDS_N0" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_N0" SLEW = SLOW;
-# NET "F_LVDS_P0" LOC = N5;
-# NET "F_LVDS_P0" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_P0" SLEW = SLOW;
+#NET "F_DX17" LOC = G1;
+#NET "F_DX17" IOSTANDARD = LVCMOS33;
+#NET "F_DX17" SLEW = SLOW;
+#NET "F_DX18" LOC = H7;
+#NET "F_DX18" IOSTANDARD = LVCMOS33;
+#NET "F_DX18" SLEW = SLOW;
+
+# NET "F_DX[*]" IOSTANDARD = LVCMOS33;
+
+#NET "F_LVDS_N0" LOC = P6;
+#NET "F_LVDS_N0" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_N0" SLEW = SLOW;
+#NET "F_LVDS_P0" LOC = N5;
+#NET "F_LVDS_P0" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P0" SLEW = SLOW;
# NET "F_LVDS_N1" LOC = V4;
# NET "F_LVDS_N1" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N1" SLEW = SLOW;
@@ -522,36 +552,54 @@ NET "F_DX18" SLEW = SLOW;
# NET "F_LVDS_N2" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N2" SLEW = SLOW;
# NET "F_LVDS_P[2]" LOC = R3;
-# NET "F_LVDS_N[3]" LOC = V5;
+
+# NET "F_LVDS_N3" LOC = V5;
+# NET "F_LVDS_N3" IOSTANDARD = LVCMOS33;
+# NET "F_LVDS_N3" SLEW = SLOW;
+
# NET "F_LVDS_P[3]" LOC = U5;
# NET "F_LVDS_N4" LOC = T5;
# NET "F_LVDS_N4" IOSTANDARD = LVCMOS33;
# NET "F_LVDS_N4" SLEW = SLOW;
-# NET "F_LVDS_P4" LOC = R5;
-# NET "F_LVDS_P4" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_P4" SLEW = SLOW;
-# NET "F_LVDS_N[5]" LOC = T7;
-# NET "F_LVDS_P[5]" LOC = R7;
+#NET "F_LVDS_P4" LOC = R5;
+#NET "F_LVDS_P4" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P4" SLEW = SLOW;
+
+# NET "F_LVDS_N5" LOC = T7;
+# NET "F_LVDS_N5" IOSTANDARD = LVCMOS33;
+# NET "F_LVDS_N5" SLEW = SLOW;
+
+# NET "F_LVDS_P5" LOC = R7;
+# NET "F_LVDS_P5" IOSTANDARD = LVCMOS33;
+# NET "F_LVDS_P5" SLEW = SLOW;
+
# NET "F_LVDS_N[6]" LOC = V6;
# NET "F_LVDS_P[6]" LOC = T6;
-NET "F_LVDS_N7" LOC = V7;
-NET "F_LVDS_N7" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_N7" SLEW = SLOW;
-NET "F_LVDS_P7" LOC = U7;
-NET "F_LVDS_P7" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_P7" SLEW = SLOW;
-# NET "F_LVDS_N[8]" LOC = V8;
+#NET "F_LVDS_N7" LOC = V7;
+#NET "F_LVDS_N7" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_N7" SLEW = SLOW;
+
+#NET "F_LVDS_P7" LOC = U7;
+#NET "F_LVDS_P7" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P7" SLEW = SLOW;
+
+# NET "F_LVDS_N8" LOC = V8;
+# NET "F_LVDS_N8" IOSTANDARD = LVCMOS33;
+# NET "F_LVDS_N8" SLEW = SLOW;
+
# NET "F_LVDS_P[8]" LOC = U8;
# NET "F_LVDS_N[9]" LOC = V9;
-# NET "F_LVDS_P[9]" LOC = T9;
+#NET "F_LVDS_P9" LOC = T9;
+#NET "F_LVDS_P9" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P9" SLEW = SLOW;
# NET "F_LVDS_N[10]" LOC = V11;
# NET "F_LVDS_P[10]" LOC = U11;
-# NET "F_LVDS_N11" LOC = T11;
-# NET "F_LVDS_N11" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_N11" SLEW = SLOW;
-NET "F_LVDS_P11" LOC = R11;
-NET "F_LVDS_P11" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_P11" SLEW = FAST;
+#NET "F_LVDS_N11" LOC = T11;
+#NET "F_LVDS_N11" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_N11" SLEW = SLOW;
+#NET "F_LVDS_P11" LOC = R11;
+#NET "F_LVDS_P11" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P11" SLEW = SLOW;
# NET "F_LVDS_N[12]" LOC = V13;
# NET "F_LVDS_P[12]" LOC = U13;
# NET "F_LVDS_N[13]" LOC = V14;
@@ -561,42 +609,45 @@ NET "F_LVDS_P11" SLEW = FAST;
#NET "F_LVDS_N15" LOC = V10;
#NET "F_LVDS_N15" IOSTANDARD = LVCMOS33;
#NET "F_LVDS_N15" SLEW = SLOW;
-NET "F_LVDS_P15" LOC = U10;
-NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
-NET "F_LVDS_P15" SLEW = SLOW;
+#NET "F_LVDS_P15" LOC = U10;
+#NET "F_LVDS_P15" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_P15" SLEW = SLOW;
# NET "F_LVDS_P[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_N[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
-# NET "F_LVDS_NA" LOC = K3;
-# NET "F_LVDS_NA" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
+#NET "F_LVDS_NA" LOC = K3;
+#NET "F_LVDS_NA" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_NA" SLEW = SLOW;
# NET "F_LVDS_PA" LOC = K4;
# NET "F_LVDS_PA" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
-# NET "F_LVDS_NB" LOC = K5;
-# NET "F_LVDS_NB" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_NB" SLEW = SLOW;
-# NET "F_LVDS_PB" LOC = L5;
-# NET "F_LVDS_PB" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_PB" SLEW = SLOW;
-# NET "F_LVDS_NC" LOC = L1;
-# NET "F_LVDS_NC" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_NC" SLEW = SLOW;
-# NET "F_LVDS_PC" LOC = L2;
-# NET "F_LVDS_PC" IOSTANDARD = LVCMOS33;
-# NET "F_LVDS_PC" SLEW = SLOW;
-
-NET "F_LVDS_CK_N0" LOC = T8;
-NET "F_LVDS_CK_N0" IOSTANDARD = LVCMOS33;
-
-NET "F_LVDS_CK_P0" LOC = R8;
-NET "F_LVDS_CK_P0" IOSTANDARD = LVCMOS33;
-
-#NET "F_LVDS_CK_N1" LOC = T10;
-#NET "F_LVDS_CK_N1" IOSTANDARD = LVCMOS33;
-#NET "F_LVDS_CK_N1" SLEW = SLOW;
-#NET "F_LVDS_CK_P1" LOC = R10;
-#NET "F_LVDS_CK_P1" IOSTANDARD = LVCMOS33;
-#NET "F_LVDS_CK_P1" SLEW = SLOW;
+#NET "F_LVDS_NB" LOC = K5;
+#NET "F_LVDS_NB" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_NB" SLEW = SLOW;
+#NET "F_LVDS_PB" LOC = L5;
+#NET "F_LVDS_PB" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_PB" SLEW = SLOW;
+#NET "F_LVDS_NC" LOC = L1;
+#NET "F_LVDS_NC" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_NC" SLEW = SLOW;
+#NET "F_LVDS_PC" LOC = L2;
+#NET "F_LVDS_PC" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_PC" SLEW = SLOW;
+
+#NET "F_LVDS_CK0_N" LOC = T8;
+#NET "F_LVDS_CK0_N" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_CK0_N" SLEW = SLOW;
+#NET "F_LVDS_CK0_P" LOC = R8;
+#NET "F_LVDS_CK0_P" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_CK0_P" SLEW = SLOW;
+
+#NET "F_LVDS_CK1_N" LOC = T10;
+#NET "F_LVDS_CK1_N" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_CK1_N" SLEW = SLOW;
+#NET "F_LVDS_CK1_P" LOC = R10;
+#NET "F_LVDS_CK1_P" IOSTANDARD = LVCMOS33;
+#NET "F_LVDS_CK1_P" SLEW = SLOW;
# NET "F_LVDS_CK_N[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
# NET "F_LVDS_CK_P[*]" IOSTANDARD = LVDS_33 | DIFF_TERM = TRUE;
+NET "CLK2_P" PERIOD = 20 ns;
diff --git a/build/novena_eim.xise b/build/novena_eim.xise
index 728f785..45f6264 100644
--- a/build/novena_eim.xise
+++ b/build/novena_eim.xise
@@ -1,448 +1,433 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="../src/rtl/nand_log_tb.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="../src/rtl/novena_fpga.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
- </file>
- <file xil_pn:name="../src/rtl/romulator_ddr3_tb.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="../src/rtl/romulator_tb.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="../src/rtl/spi_eeprom_tb.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="../src/rtl/spi_eeprom.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="../src/rtl/common/reg_ro_4burst.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- </file>
- <file xil_pn:name="../src/rtl/common/reg_ro.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
- </file>
- <file xil_pn:name="../src/rtl/common/reg_wo_4burst.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
- </file>
- <file xil_pn:name="../src/rtl/common/reg_wo.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
- </file>
- <file xil_pn:name="../src/rtl/common/rising_edge.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
- </file>
- <file xil_pn:name="../src/rtl/common/sync_reset.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/bclk_dll/bclk_dll.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/dcm_delay/dcm_delay.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/ddr3_clkgen/ddr3_clkgen.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/uk_fifo/uk_fifo.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/nandadr_fifo/nandadr_fifo.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/eimram/eimram.xco" xil_pn:type="FILE_COREGEN">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="novena.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/uk_fifo/uk_fifo.xise" xil_pn:type="FILE_COREGENISE">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/nandadr_fifo/nandadr_fifo.xise" xil_pn:type="FILE_COREGENISE">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../src/rtl/ip/eimram/eimram.xise" xil_pn:type="FILE_COREGENISE">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
- <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
- <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_fpga" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="../src/rtl/novena_fpga.v" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_fpga" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
- <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
- <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
- <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="novena_fpga" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
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+ <!-- project source files, project and process properties. This file, -->
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+ <!-- -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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+ <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
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+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|novena_fpga" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../src/rtl/novena_fpga.v" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/novena_fpga" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="novena_fpga" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="novena_fpga_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="novena_fpga_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="novena_fpga_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="novena_fpga_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+ <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/novena_fpga" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.novena_fpga" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.novena_fpga" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="novena_eim" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-30T11:08:47" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E44A4CB5E30C7EEC638159A5C0A776AC" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/build/xilinx.mk b/build/xilinx.mk
new file mode 100644
index 0000000..a3a0216
--- /dev/null
+++ b/build/xilinx.mk
@@ -0,0 +1,176 @@
+# The top level module should define the variables below then include
+# this file. The files listed should be in the same directory as the
+# Makefile.
+#
+# variable description
+# ---------- -------------
+# project project name (top level module should match this name)
+# top_module top level module of the project
+# libdir path to library directory
+# libs library modules used
+# vfiles all local .v files
+# xilinx_cores all local .xco files
+# vendor vendor of FPGA (xilinx, altera, etc.)
+# family FPGA device family (spartan3e)
+# part FPGA part name (xc4vfx12-10-sf363)
+# flashsize size of flash for mcs file (16384)
+# optfile (optional) xst extra opttions file to put in .scr
+# map_opts (optional) options to give to map
+# par_opts (optional) options to give to par
+# intstyle (optional) intstyle option to all tools
+#
+# files description
+# ---------- ------------
+# $(project).ucf ucf file
+#
+# Library modules should have a modules.mk in their root directory,
+# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
+# and xilinx_cores variable.
+#
+# all the .xco files listed in xilinx_cores will be generated with core, with
+# the resulting .v and .ngc files placed back in the same directory as
+# the .xco file.
+#
+# TODO: .xco files are device dependant, should use a template based system
+
+coregen_work_dir ?= ./coregen-tmp
+map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
+par_opts ?= -ol high
+isedir ?= /opt/Xilinx/13.3/ISE_DS
+xil_env ?= . $(isedir)/settings32.sh
+flashsize ?= 8192
+
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
+mkfiles = Makefile $(libmks) xilinx.mk
+include $(libmks)
+
+corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
+local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
+vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
+junk += $(local_corengcs)
+
+.PHONY: default xilinx_cores clean twr etwr
+default: $(project).bit $(project).mcs
+xilinx_cores: $(corengcs)
+twr: $(project).twr
+etwr: $(project)_err.twr
+
+define cp_template
+$(2): $(1)
+ cp $(1) $(2)
+endef
+$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
+
+%.ngc %.v: %.xco
+ @echo "=== rebuilding $@"
+ if [ -d $(coregen_work_dir) ]; then \
+ rm -rf $(coregen_work_dir)/*; \
+ else \
+ mkdir -p $(coregen_work_dir); \
+ fi
+ cd $(coregen_work_dir); \
+ $(xil_env); \
+ coregen -b $$OLDPWD/$<; \
+ cd -
+ xcodir=`dirname $<`; \
+ basename=`basename $< .xco`; \
+ if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
+ echo "'$@' wasn't created."; \
+ exit 1; \
+ else \
+ cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
+ fi
+junk += $(coregen_work_dir)
+
+date = $(shell date +%F-%H-%M)
+
+# some common junk
+junk += *.xrpt
+
+programming_files: $(project).bit $(project).mcs
+ mkdir -p $@/$(date)
+ mkdir -p $@/latest
+ for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
+ $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr
+
+$(project).mcs: $(project).bit
+ $(xil_env); \
+ promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^
+junk += $(project).mcs $(project).cfi $(project).prm
+
+$(project).bit: $(project)_par.ncd
+ $(xil_env); \
+ bitgen $(intstyle) -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit
+junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
+
+
+$(project)_par.ncd: $(project).ncd
+ $(xil_env); \
+ if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
+ :; \
+ else \
+ $(MAKE) etwr; \
+ fi
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
+junk += $(project)_par_pad.csv $(project)_par_pad.txt
+junk += $(project)_par.grf $(project)_par.ptwx
+junk += $(project)_par.unroutes $(project)_par.xpi
+
+$(project).ncd: $(project).ngd
+ if [ -r $(project)_par.ncd ]; then \
+ cp $(project)_par.ncd smartguide.ncd; \
+ smartguide="-smartguide smartguide.ncd"; \
+ else \
+ smartguide=""; \
+ fi; \
+ $(xil_env); \
+ map $(intstyle) $(map_opts) $$smartguide $<
+junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
+junk += smartguide.ncd $(project).psr
+junk += $(project)_summary.xml $(project)_usage.xml
+
+$(project).ngd: $(project).ngc $(project).ucf $(project).bmm
+ $(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm
+junk += $(project).ngd $(project).bld
+
+$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
+ $(xil_env); xst $(intstyle) -ifn $(project).scr
+junk += xlnx_auto* $(top_module).lso $(project).srp
+junk += netlist.lst xst $(project).ngc
+
+$(project).prj: $(vfiles) $(mkfiles)
+ for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done
+ sort -u $(project).tmpprj > $(project).prj
+ rm -f $(project).tmpprj
+junk += $(project).prj
+
+optfile += $(wildcard $(project).opt)
+top_module ?= $(project)
+$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
+ echo "run" > $@
+ echo "-p $(part)" >> $@
+ echo "-top $(top_module)" >> $@
+ echo "-ifn $(project).prj" >> $@
+ echo "-ofn $(project).ngc" >> $@
+ cat ./xilinx.opt $(optfile) >> $@
+junk += $(project).scr
+
+$(project).post_map.twr: $(project).ncd
+ $(xil_env); trce -e 10 $< $(project).pcf -o $@
+junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
+
+$(project).twr: $(project)_par.ncd
+ $(xil_env); trce $< $(project).pcf -o $(project).twr
+junk += $(project).twr $(project).twx smartpreview.twr
+
+$(project)_err.twr: $(project)_par.ncd
+ $(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr
+junk += $(project)_err.twr $(project)_err.twx
+junk += $(project).lso $(project)_bitgen.xwb $(project)_bitgen.xwbt
+junk += usage_statistics_webtalk.html par_usage_statistics.html webtalk.log _xmsgs default.xreport
+
+.gitignore: $(mkfiles)
+ echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
+
+clean::
+ rm -rf $(junk)
diff --git a/build/xilinx.opt b/build/xilinx.opt
new file mode 100644
index 0000000..7fe9d8b
--- /dev/null
+++ b/build/xilinx.opt
@@ -0,0 +1,42 @@
+-ifmt mixed
+-ofmt NGC
+-opt_mode speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy no
+-netlist_hierarchy as_optimized
+-rtlview no
+-glob_opt AllClockNets
+-read_cores yes
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+#-dsp_utilization_ratio 100
+-safe_implementation No
+-fsm_extract YES
+-fsm_encoding Auto
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-shreg_extract YES
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+#-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v
new file mode 100644
index 0000000..50878eb
--- /dev/null
+++ b/src/rtl/coretest_hashes.v
@@ -0,0 +1,319 @@
+//======================================================================
+//
+// coretest_hashes.v
+// -----------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module coretest_hashes(
+ // Clock and reset.
+ input wire clk,
+ input wire reset_n,
+
+ // Control.
+ input wire cs,
+ input wire we,
+
+ // Data ports.
+ input wire [18:0] address,
+ input wire [15:0] write_data,
+ output reg [15:0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter SHA1_ADDR_PREFIX = 7'h42;
+ parameter SHA256_ADDR_PREFIX = 7'h43;
+ parameter SHA512_ADDR_PREFIX = 7'h44;
+
+
+ //----------------------------------------------------------------
+ // Wires and registers
+ //----------------------------------------------------------------
+// reg [18:0] address_reg;
+ reg [31:0] write_reg;
+ reg [31:0] read_reg;
+ reg cs_reg;
+ reg error_reg;
+
+ // sha1 connections.
+ reg sha1_cs;
+ reg sha1_we;
+ reg [7:0] sha1_address;
+ reg [31:0] sha1_write_data;
+ wire [31:0] sha1_read_data;
+ wire sha1_error;
+
+ // sha256 connections.
+ reg sha256_cs;
+ reg sha256_we;
+ reg [7:0] sha256_address;
+ reg [31:0] sha256_write_data;
+ wire [31:0] sha256_read_data;
+ wire sha256_error;
+
+ // sha512 connections.
+ reg sha512_cs;
+ reg sha512_we;
+ reg [7:0] sha512_address;
+ reg [31:0] sha512_write_data;
+ wire [31:0] sha512_read_data;
+ wire sha512_error;
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignment.
+ //----------------------------------------------------------------
+
+
+ //----------------------------------------------------------------
+ // Core instantiations.
+ //----------------------------------------------------------------
+ sha1 sha1(
+ // Clock and reset.
+ .clk(clk),
+ .reset_n(reset_n),
+
+ // Control.
+ .cs(sha1_cs),
+ .we(sha1_we),
+
+ // Data ports.
+ .address(sha1_address),
+ .write_data(sha1_write_data),
+ .read_data(sha1_read_data),
+ .error(sha1_error)
+ );
+
+
+ sha256 sha256(
+ // Clock and reset.
+ .clk(clk),
+ .reset_n(reset_n),
+
+ // Control.
+ .cs(sha256_cs),
+ .we(sha256_we),
+
+ // Data ports.
+ .address(sha256_address),
+ .write_data(sha256_write_data),
+ .read_data(sha256_read_data),
+ .error(sha256_error)
+ );
+
+
+ sha512 sha512(
+ // Clock and reset.
+ .clk(clk),
+ .reset_n(reset_n),
+
+ // Control.
+ .cs(sha512_cs),
+ .we(sha512_we),
+
+ // Data ports.
+ .address(sha512_address),
+ .write_data(sha512_write_data),
+ .read_data(sha512_read_data),
+ .error(sha512_error)
+ );
+
+`ifdef LOG
+ // A simple log of the last two 32-bit writes, to check hold times
+ // and to validate that data doesn't change on the wire.
+ // (6 clock cycles, and thankfully no)
+ parameter LOG_ADDR_PREFIX = 7'h45;
+ reg activated = 0;
+ reg [15:0] log_value [0:3];
+ reg [15:0] log_count [0:3];
+
+ always @(posedge clk)
+ begin
+ if (cs && we)
+ begin
+ if (!activated || (log_value[0] != write_data))
+ begin
+ log_value[3] = log_value[2];
+ log_count[3] = log_count[2];
+ log_value[2] = log_value[1];
+ log_count[2] = log_count[1];
+ log_value[1] = log_value[0];
+ log_count[1] = log_count[0];
+ log_value[0] = write_data;
+ log_count[0] = 0;
+ activated = 1'b1;
+ end
+ log_count[0] = log_count[0] + 1;
+ end
+ else
+ begin
+ activated = 1'b0;
+ end
+ end
+`endif
+
+ //----------------------------------------------------------------
+ // address_mux
+ //
+ // Combinational data mux that handles addressing between
+ // cores using the 32-bit memory like interface.
+ //----------------------------------------------------------------
+ always @*
+ begin : address_mux
+ // Default assignments.
+ cs_reg = cs;
+
+ sha1_cs = 0;
+ sha1_we = 0;
+ sha1_address = 8'h00;
+ sha1_write_data = 32'h00000000;
+
+ sha256_cs = 0;
+ sha256_we = 0;
+ sha256_address = 8'h00;
+ sha256_write_data = 32'h00000000;
+
+ sha512_cs = 0;
+ sha512_we = 0;
+ sha512_address = 8'h00;
+ sha512_write_data = 32'h00000000;
+
+ // Handle the awkward interface between 16-bit EIM operations and
+ // 32-bit SHA core wrapper operations.
+ // XXX assume that all reads and writes will be sequential and aligned
+
+ // write operations
+ if (cs && we && address[1:0] == 2'b00)
+ begin
+ // save the first word of the write data
+// address_reg = address;
+ write_reg[31:16] = write_data;
+ cs_reg = 0;
+ end
+ else if (cs && we && address[1:0] == 2'b10)
+ begin
+ // write out the complete 4 bytes
+// if (address[18:2] == address_reg[18:2])
+ begin
+ write_reg[15:0] = write_data;
+ end
+ end
+ else
+ begin
+// address_reg = address_reg;
+ write_reg = write_reg;
+ end
+
+ // address mux
+ case (address[18:12])
+ SHA1_ADDR_PREFIX:
+ begin
+ sha1_cs = cs_reg;
+ sha1_we = we;
+ sha1_address = address[9:2];
+ sha1_write_data = write_reg;
+ read_reg = sha1_read_data;
+ error_reg = sha1_error;
+ end
+
+ SHA256_ADDR_PREFIX:
+ begin
+ sha256_cs = cs_reg;
+ sha256_we = we;
+ sha256_address = address[9:2];
+ sha256_write_data = write_reg;
+ read_reg = sha256_read_data;
+ error_reg = sha256_error;
+ end
+
+ SHA512_ADDR_PREFIX:
+ begin
+ sha512_cs = cs_reg;
+ sha512_we = we;
+ sha512_address = address[9:2];
+ sha512_write_data = write_reg;
+ read_reg = sha512_read_data;
+ error_reg = sha512_error;
+ end
+
+ // read operations
+`ifdef LOG
+ LOG_ADDR_PREFIX:
+ begin
+ case (address[3:2])
+ 2'b00: read_reg = { log_value[0], log_count[0] };
+ 2'b01: read_reg = { log_value[1], log_count[1] };
+ 2'b10: read_reg = { log_value[2], log_count[2] };
+ 2'b11: read_reg = { log_value[3], log_count[3] };
+ endcase
+ end
+`endif
+ default:
+ begin
+ read_reg = 32'h0;
+ end
+ endcase
+
+ if (cs && !we && address[1:0] == 2'b00)
+ begin
+ // read the first word
+// address_reg = address;
+ read_data = read_reg[31:16];
+ end
+ else if (cs && !we && address[1:0] == 2'b10)
+ begin
+ // read the second word
+ // note this is done as two separate reads for convenience
+// if (address[18:2] == address_reg[18:2])
+ begin
+ read_data = read_reg[15:0];
+ end
+ end
+ else
+ begin
+ read_data = 16'hZZZZ;
+ end // else: !if(cs && !we && address[1:0] == 2'b10)
+ end // address_mux
+
+endmodule // coretest_hashes
+
+//======================================================================
+// EOF coretest_hashes.v
+//======================================================================
diff --git a/src/rtl/ip/ddr3_clkgen/ddr3_clkgen.v b/src/rtl/ip/clk_dll/clk_dll.v
similarity index 59%
rename from src/rtl/ip/ddr3_clkgen/ddr3_clkgen.v
rename to src/rtl/ip/clk_dll/clk_dll.v
index 6c2e504..1cd297c 100755
--- a/src/rtl/ip/ddr3_clkgen/ddr3_clkgen.v
+++ b/src/rtl/ip/clk_dll/clk_dll.v
@@ -1,158 +1,162 @@
-// file: ddr3_clkgen.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-// "Output Output Phase Duty Pk-to-Pk Phase"
-// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-//----------------------------------------------------------------------------
-// CLK_OUT1____50.000______0.000______50.0______267.325____251.827
-// CLK_OUT2___400.000______0.000______50.0______180.270____251.827
-// CLK_OUT3___100.000______0.000______50.0______231.478____251.827
-//
-//----------------------------------------------------------------------------
-// "Input Clock Freq (MHz) Input Jitter (UI)"
-//----------------------------------------------------------------------------
-// __primary______________50____________0.010
-
-`timescale 1ps/1ps
-
-(* CORE_GENERATION_INFO = "ddr3_clkgen,clk_wiz_v4_1,{component_name=ddr3_clkgen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type [...]
-module ddr3_clkgen
- (// Clock in ports
- input clk50in,
- // Clock out ports
- output clk50,
- output clk400,
- output clk100,
- // Status and control signals
- input RESET,
- output LOCKED
- );
-
- // Input buffering
- //------------------------------------
- BUFG clkin1_buf
- (.O (clkin1),
- .I (clk50in));
-
-
- // Clocking primitive
- //------------------------------------
- // Instantiation of the PLL primitive
- // * Unused inputs are tied off
- // * Unused outputs are labeled unused
- wire [15:0] do_unused;
- wire drdy_unused;
- wire clkfbout;
- wire clkfbout_buf;
- wire clkout3_unused;
- wire clkout4_unused;
- wire clkout5_unused;
-
- PLL_BASE
- #(.BANDWIDTH ("OPTIMIZED"),
- .CLK_FEEDBACK ("CLKFBOUT"),
- .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
- .DIVCLK_DIVIDE (1),
- .CLKFBOUT_MULT (8),
- .CLKFBOUT_PHASE (0.000),
- .CLKOUT0_DIVIDE (8),
- .CLKOUT0_PHASE (0.000),
- .CLKOUT0_DUTY_CYCLE (0.500),
- .CLKOUT1_DIVIDE (1),
- .CLKOUT1_PHASE (0.000),
- .CLKOUT1_DUTY_CYCLE (0.500),
- .CLKOUT2_DIVIDE (4),
- .CLKOUT2_PHASE (0.000),
- .CLKOUT2_DUTY_CYCLE (0.500),
- .CLKIN_PERIOD (20.0),
- .REF_JITTER (0.010))
- pll_base_inst
- // Output clocks
- (.CLKFBOUT (clkfbout),
- .CLKOUT0 (clkout0),
- .CLKOUT1 (clkout1),
- .CLKOUT2 (clkout2),
- .CLKOUT3 (clkout3_unused),
- .CLKOUT4 (clkout4_unused),
- .CLKOUT5 (clkout5_unused),
- // Status and control signals
- .LOCKED (LOCKED),
- .RST (RESET),
- // Input clock control
- .CLKFBIN (clkfbout_buf),
- .CLKIN (clkin1));
-
-
- // Output buffering
- //-----------------------------------
- BUFG clkf_buf
- (.O (clkfbout_buf),
- .I (clkfbout));
-
- BUFG clkout1_buf
- (.O (clk50),
- .I (clkout0));
-
-
- BUFG clkout2_buf
- (.O (clk400),
- .I (clkout1));
-
- BUFG clkout3_buf
- (.O (clk100),
- .I (clkout2));
-
-
-
-endmodule
+// file: clk_dll.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output Output Phase Duty Pk-to-Pk Phase"
+// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
+// CLK_OUT2____25.000______0.000______50.0______300.000____150.000
+// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock Freq (MHz) Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_dll,clk_wiz_v3_6,{component_name=clk_dll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manu [...]
+module clk_dll
+ (// Clock in ports
+ input clk50in,
+ // Clock out ports
+ output clk50,
+ output clk25,
+ output clk3p2,
+ // Status and control signals
+ input RESET,
+ output LOCKED
+ );
+
+ // Input buffering
+ //------------------------------------
+ BUFG clkin1_buf
+ (.O (clkin1),
+ .I (clk50in));
+
+
+ // Clocking primitive
+ //------------------------------------
+
+ // Instantiation of the DCM primitive
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire psdone_unused;
+ wire locked_int;
+ wire [7:0] status_int;
+ wire clkfb;
+ wire clk0;
+ wire clk2x;
+ wire clkdv;
+
+ DCM_SP
+ #(.CLKDV_DIVIDE (2.000),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+ .CLKIN_PERIOD (20.0),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+ .CLK_FEEDBACK ("1X"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .PHASE_SHIFT (0),
+ .STARTUP_WAIT ("FALSE"))
+ dcm_sp_inst
+ // Input clock
+ (.CLKIN (clkin1),
+ .CLKFB (clkfb),
+ // Output clocks
+ .CLK0 (clk0),
+ .CLK90 (),
+ .CLK180 (),
+ .CLK270 (),
+ .CLK2X (clk2x),
+ .CLK2X180 (),
+ .CLKFX (),
+ .CLKFX180 (),
+ .CLKDV (clkdv),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .STATUS (status_int),
+
+ .RST (RESET),
+ // Unused pin- tie low
+ .DSSEN (1'b0));
+
+ assign LOCKED = locked_int;
+
+ // Output buffering
+ //-----------------------------------
+ assign clkfb = clk50;
+
+ BUFG clkout1_buf
+ (.O (clk50),
+ .I (clk0));
+
+
+ BUFG clkout2_buf
+ (.O (clk25),
+ .I (clkdv));
+
+ BUFG clkout3_buf
+ (.O (clk3p2),
+ .I (clk2x));
+
+
+
+endmodule
diff --git a/src/rtl/ip/eimram/eimram.v b/src/rtl/ip/eimram/eimram.v
deleted file mode 100644
index b0bce79..0000000
--- a/src/rtl/ip/eimram/eimram.v
+++ /dev/null
@@ -1,186 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used solely *
-* for design, simulation, implementation and creation of design files *
-* limited to Xilinx devices or technologies. Use with non-Xilinx *
-* devices or technologies is expressly prohibited and immediately *
-* terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
-* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
-* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
-* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
-* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
-* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
-* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
-* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
-* PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support appliances, *
-* devices, or systems. Use in such applications are expressly *
-* prohibited. *
-* *
-* (c) Copyright 1995-2014 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// You must compile the wrapper file eimram.v when simulating
-// the core, eimram. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-`timescale 1ns/1ps
-
-module eimram(
- clka,
- ena,
- wea,
- addra,
- dina,
- clkb,
- addrb,
- doutb
-);
-
-input clka;
-input ena;
-input [1 : 0] wea;
-input [14 : 0] addra;
-input [15 : 0] dina;
-input clkb;
-input [14 : 0] addrb;
-output [15 : 0] doutb;
-
-// synthesis translate_off
-
- BLK_MEM_GEN_V7_3 #(
- .C_ADDRA_WIDTH(15),
- .C_ADDRB_WIDTH(15),
- .C_ALGORITHM(1),
- .C_AXI_ID_WIDTH(4),
- .C_AXI_SLAVE_TYPE(0),
- .C_AXI_TYPE(1),
- .C_BYTE_SIZE(8),
- .C_COMMON_CLK(0),
- .C_DEFAULT_DATA("0"),
- .C_DISABLE_WARN_BHV_COLL(0),
- .C_DISABLE_WARN_BHV_RANGE(0),
- .C_ENABLE_32BIT_ADDRESS(0),
- .C_FAMILY("spartan6"),
- .C_HAS_AXI_ID(0),
- .C_HAS_ENA(1),
- .C_HAS_ENB(0),
- .C_HAS_INJECTERR(0),
- .C_HAS_MEM_OUTPUT_REGS_A(0),
- .C_HAS_MEM_OUTPUT_REGS_B(0),
- .C_HAS_MUX_OUTPUT_REGS_A(0),
- .C_HAS_MUX_OUTPUT_REGS_B(0),
- .C_HAS_REGCEA(0),
- .C_HAS_REGCEB(0),
- .C_HAS_RSTA(0),
- .C_HAS_RSTB(0),
- .C_HAS_SOFTECC_INPUT_REGS_A(0),
- .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
- .C_INIT_FILE("BlankString"),
- .C_INIT_FILE_NAME("no_coe_file_loaded"),
- .C_INITA_VAL("0"),
- .C_INITB_VAL("0"),
- .C_INTERFACE_TYPE(0),
- .C_LOAD_INIT_FILE(0),
- .C_MEM_TYPE(1),
- .C_MUX_PIPELINE_STAGES(0),
- .C_PRIM_TYPE(1),
- .C_READ_DEPTH_A(32768),
- .C_READ_DEPTH_B(32768),
- .C_READ_WIDTH_A(16),
- .C_READ_WIDTH_B(16),
- .C_RST_PRIORITY_A("CE"),
- .C_RST_PRIORITY_B("CE"),
- .C_RST_TYPE("SYNC"),
- .C_RSTRAM_A(0),
- .C_RSTRAM_B(0),
- .C_SIM_COLLISION_CHECK("ALL"),
- .C_USE_BRAM_BLOCK(0),
- .C_USE_BYTE_WEA(1),
- .C_USE_BYTE_WEB(1),
- .C_USE_DEFAULT_DATA(0),
- .C_USE_ECC(0),
- .C_USE_SOFTECC(0),
- .C_WEA_WIDTH(2),
- .C_WEB_WIDTH(2),
- .C_WRITE_DEPTH_A(32768),
- .C_WRITE_DEPTH_B(32768),
- .C_WRITE_MODE_A("WRITE_FIRST"),
- .C_WRITE_MODE_B("WRITE_FIRST"),
- .C_WRITE_WIDTH_A(16),
- .C_WRITE_WIDTH_B(16),
- .C_XDEVICEFAMILY("spartan6")
- )
- inst (
- .CLKA(clka),
- .ENA(ena),
- .WEA(wea),
- .ADDRA(addra),
- .DINA(dina),
- .CLKB(clkb),
- .ADDRB(addrb),
- .DOUTB(doutb),
- .RSTA(),
- .REGCEA(),
- .DOUTA(),
- .RSTB(),
- .ENB(),
- .REGCEB(),
- .WEB(),
- .DINB(),
- .INJECTSBITERR(),
- .INJECTDBITERR(),
- .SBITERR(),
- .DBITERR(),
- .RDADDRECC(),
- .S_ACLK(),
- .S_ARESETN(),
- .S_AXI_AWID(),
- .S_AXI_AWADDR(),
- .S_AXI_AWLEN(),
- .S_AXI_AWSIZE(),
- .S_AXI_AWBURST(),
- .S_AXI_AWVALID(),
- .S_AXI_AWREADY(),
- .S_AXI_WDATA(),
- .S_AXI_WSTRB(),
- .S_AXI_WLAST(),
- .S_AXI_WVALID(),
- .S_AXI_WREADY(),
- .S_AXI_BID(),
- .S_AXI_BRESP(),
- .S_AXI_BVALID(),
- .S_AXI_BREADY(),
- .S_AXI_ARID(),
- .S_AXI_ARADDR(),
- .S_AXI_ARLEN(),
- .S_AXI_ARSIZE(),
- .S_AXI_ARBURST(),
- .S_AXI_ARVALID(),
- .S_AXI_ARREADY(),
- .S_AXI_RID(),
- .S_AXI_RDATA(),
- .S_AXI_RRESP(),
- .S_AXI_RLAST(),
- .S_AXI_RVALID(),
- .S_AXI_RREADY(),
- .S_AXI_INJECTSBITERR(),
- .S_AXI_INJECTDBITERR(),
- .S_AXI_SBITERR(),
- .S_AXI_DBITERR(),
- .S_AXI_RDADDRECC()
- );
-
-// synthesis translate_on
-
-endmodule
diff --git a/src/rtl/ip/eimram/eimram.xci b/src/rtl/ip/eimram/eimram.xci
deleted file mode 100644
index 2613016..0000000
--- a/src/rtl/ip/eimram/eimram.xci
+++ /dev/null
@@ -1,146 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>eimram</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="7.3"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">eimram</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Full</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_SLAVE_TYPE">Memory_Slave</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_AXI_ID">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMORY_TYPE">Simple_Dual_Port_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_32BIT_ADDRESS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECCTYPE">No_ECC</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SOFTECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ERROR_INJECTION_PINS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ERROR_INJECTION_TYPE">Single_Bit_Error_Injection</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BYTE_WRITE_ENABLE">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BYTE_SIZE">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALGORITHM">Minimum_Area</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">8kx2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSUME_SYNCHRONOUS_CLK">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_A">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DEPTH_A">32768</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_A">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_A">Use_ENA_Pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_B">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_B">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_B">Always_Enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEA_PIN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEB_PIN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_INPUT_OF_SOFTECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_SOFTECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIPELINE_STAGES">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOAD_INIT_FILE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COE_FILE">no_coe_file_loaded</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FILL_REMAINING_MEMORY_LOCATIONS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REMAINING_MEMORY_LOCATIONS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTA_PIN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_A">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_A">CE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_A">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTB_PIN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_B">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_B">CE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_B">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">SYNC</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDITIONAL_INPUTS_FOR_POWER_ESTIMATION">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_CLOCK">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_WRITE_RATE">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_CLOCK">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_WRITE_RATE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_ENABLE_RATE">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_ENABLE_RATE">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COLLISION_WARNINGS">ALL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_COLLISION_WARNINGS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_OUT_OF_RANGE_WARNINGS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BRAM_BLOCK">Stand_Alone</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_Mem_file_loaded</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">virtex4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">virtex4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">111111111</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_TYPE">SYNC</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2048</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2048</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2048</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">2048</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">NONE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">spartan6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc6slx45</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/src/rtl/ip/eimram/eimram.xco b/src/rtl/ip/eimram/eimram.xco
deleted file mode 100644
index 10f094a..0000000
--- a/src/rtl/ip/eimram/eimram.xco
+++ /dev/null
@@ -1,108 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.3
-# Date: Tue Sep 30 16:19:34 2014
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
-# END Select
-# BEGIN Parameters
-CSET additional_inputs_for_power_estimation=false
-CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
-CSET axi_id_width=4
-CSET axi_slave_type=Memory_Slave
-CSET axi_type=AXI4_Full
-CSET byte_size=8
-CSET coe_file=no_coe_file_loaded
-CSET collision_warnings=ALL
-CSET component_name=eimram
-CSET disable_collision_warnings=false
-CSET disable_out_of_range_warnings=false
-CSET ecc=false
-CSET ecctype=No_ECC
-CSET enable_32bit_address=false
-CSET enable_a=Use_ENA_Pin
-CSET enable_b=Always_Enabled
-CSET error_injection_type=Single_Bit_Error_Injection
-CSET fill_remaining_memory_locations=false
-CSET interface_type=Native
-CSET load_init_file=false
-CSET mem_file=no_Mem_file_loaded
-CSET memory_type=Simple_Dual_Port_RAM
-CSET operating_mode_a=WRITE_FIRST
-CSET operating_mode_b=WRITE_FIRST
-CSET output_reset_value_a=0
-CSET output_reset_value_b=0
-CSET pipeline_stages=0
-CSET port_a_clock=100
-CSET port_a_enable_rate=100
-CSET port_a_write_rate=50
-CSET port_b_clock=100
-CSET port_b_enable_rate=100
-CSET port_b_write_rate=0
-CSET primitive=8kx2
-CSET read_width_a=16
-CSET read_width_b=16
-CSET register_porta_input_of_softecc=false
-CSET register_porta_output_of_memory_core=false
-CSET register_porta_output_of_memory_primitives=false
-CSET register_portb_output_of_memory_core=false
-CSET register_portb_output_of_memory_primitives=false
-CSET register_portb_output_of_softecc=false
-CSET remaining_memory_locations=0
-CSET reset_memory_latch_a=false
-CSET reset_memory_latch_b=false
-CSET reset_priority_a=CE
-CSET reset_priority_b=CE
-CSET reset_type=SYNC
-CSET softecc=false
-CSET use_axi_id=false
-CSET use_bram_block=Stand_Alone
-CSET use_byte_write_enable=true
-CSET use_error_injection_pins=false
-CSET use_regcea_pin=false
-CSET use_regceb_pin=false
-CSET use_rsta_pin=false
-CSET use_rstb_pin=false
-CSET write_depth_a=32768
-CSET write_width_a=16
-CSET write_width_b=16
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-09-17T22:14:36Z
-# END Extra information
-GENERATE
-# CRC: e2f26d3f
diff --git a/src/rtl/ip/eimram/eimram.xise b/src/rtl/ip/eimram/eimram.xise
deleted file mode 100644
index 99af4a9..0000000
--- a/src/rtl/ip/eimram/eimram.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="eimram.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="eimram.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|eimram" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="eimram.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/eimram" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="eimram" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-30T12:21:01" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D2460403F288B65D2496353B592AB7A0" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/src/rtl/ip/nandadr_fifo/nandadr_fifo.v b/src/rtl/ip/nandadr_fifo/nandadr_fifo.v
deleted file mode 100644
index e9b5622..0000000
--- a/src/rtl/ip/nandadr_fifo/nandadr_fifo.v
+++ /dev/null
@@ -1,491 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used solely *
-* for design, simulation, implementation and creation of design files *
-* limited to Xilinx devices or technologies. Use with non-Xilinx *
-* devices or technologies is expressly prohibited and immediately *
-* terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
-* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
-* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
-* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
-* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
-* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
-* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
-* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
-* PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support appliances, *
-* devices, or systems. Use in such applications are expressly *
-* prohibited. *
-* *
-* (c) Copyright 1995-2014 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// You must compile the wrapper file nandadr_fifo.v when simulating
-// the core, nandadr_fifo. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-`timescale 1ns/1ps
-
-module nandadr_fifo(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- overflow,
- empty,
- rd_data_count
-);
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [29 : 0] din;
-input wr_en;
-input rd_en;
-output [29 : 0] dout;
-output full;
-output overflow;
-output empty;
-output [13 : 0] rd_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V9_3 #(
- .C_ADD_NGC_CONSTRAINT(0),
- .C_APPLICATION_TYPE_AXIS(0),
- .C_APPLICATION_TYPE_RACH(0),
- .C_APPLICATION_TYPE_RDCH(0),
- .C_APPLICATION_TYPE_WACH(0),
- .C_APPLICATION_TYPE_WDCH(0),
- .C_APPLICATION_TYPE_WRCH(0),
- .C_AXI_ADDR_WIDTH(32),
- .C_AXI_ARUSER_WIDTH(1),
- .C_AXI_AWUSER_WIDTH(1),
- .C_AXI_BUSER_WIDTH(1),
- .C_AXI_DATA_WIDTH(64),
- .C_AXI_ID_WIDTH(4),
- .C_AXI_RUSER_WIDTH(1),
- .C_AXI_TYPE(0),
- .C_AXI_WUSER_WIDTH(1),
- .C_AXIS_TDATA_WIDTH(64),
- .C_AXIS_TDEST_WIDTH(4),
- .C_AXIS_TID_WIDTH(8),
- .C_AXIS_TKEEP_WIDTH(4),
- .C_AXIS_TSTRB_WIDTH(4),
- .C_AXIS_TUSER_WIDTH(4),
- .C_AXIS_TYPE(0),
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(14),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(30),
- .C_DIN_WIDTH_AXIS(1),
- .C_DIN_WIDTH_RACH(32),
- .C_DIN_WIDTH_RDCH(64),
- .C_DIN_WIDTH_WACH(32),
- .C_DIN_WIDTH_WDCH(64),
- .C_DIN_WIDTH_WRCH(2),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(30),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_ERROR_INJECTION_TYPE_AXIS(0),
- .C_ERROR_INJECTION_TYPE_RACH(0),
- .C_ERROR_INJECTION_TYPE_RDCH(0),
- .C_ERROR_INJECTION_TYPE_WACH(0),
- .C_ERROR_INJECTION_TYPE_WDCH(0),
- .C_ERROR_INJECTION_TYPE_WRCH(0),
- .C_FAMILY("spartan6"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_AXI_ARUSER(0),
- .C_HAS_AXI_AWUSER(0),
- .C_HAS_AXI_BUSER(0),
- .C_HAS_AXI_RD_CHANNEL(0),
- .C_HAS_AXI_RUSER(0),
- .C_HAS_AXI_WR_CHANNEL(0),
- .C_HAS_AXI_WUSER(0),
- .C_HAS_AXIS_TDATA(0),
- .C_HAS_AXIS_TDEST(0),
- .C_HAS_AXIS_TID(0),
- .C_HAS_AXIS_TKEEP(0),
- .C_HAS_AXIS_TLAST(0),
- .C_HAS_AXIS_TREADY(1),
- .C_HAS_AXIS_TSTRB(0),
- .C_HAS_AXIS_TUSER(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_DATA_COUNTS_AXIS(0),
- .C_HAS_DATA_COUNTS_RACH(0),
- .C_HAS_DATA_COUNTS_RDCH(0),
- .C_HAS_DATA_COUNTS_WACH(0),
- .C_HAS_DATA_COUNTS_WDCH(0),
- .C_HAS_DATA_COUNTS_WRCH(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MASTER_CE(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(1),
- .C_HAS_PROG_FLAGS_AXIS(0),
- .C_HAS_PROG_FLAGS_RACH(0),
- .C_HAS_PROG_FLAGS_RDCH(0),
- .C_HAS_PROG_FLAGS_WACH(0),
- .C_HAS_PROG_FLAGS_WDCH(0),
- .C_HAS_PROG_FLAGS_WRCH(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SLAVE_CE(0),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_IMPLEMENTATION_TYPE_AXIS(1),
- .C_IMPLEMENTATION_TYPE_RACH(1),
- .C_IMPLEMENTATION_TYPE_RDCH(1),
- .C_IMPLEMENTATION_TYPE_WACH(1),
- .C_IMPLEMENTATION_TYPE_WDCH(1),
- .C_IMPLEMENTATION_TYPE_WRCH(1),
- .C_INIT_WR_PNTR_VAL(0),
- .C_INTERFACE_TYPE(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(1),
- .C_PRELOAD_REGS(0),
- .C_PRIM_FIFO_TYPE("8kx4"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_EMPTY_TYPE_AXIS(0),
- .C_PROG_EMPTY_TYPE_RACH(0),
- .C_PROG_EMPTY_TYPE_RDCH(0),
- .C_PROG_EMPTY_TYPE_WACH(0),
- .C_PROG_EMPTY_TYPE_WDCH(0),
- .C_PROG_EMPTY_TYPE_WRCH(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(16381),
- .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
- .C_PROG_FULL_THRESH_NEGATE_VAL(16380),
- .C_PROG_FULL_TYPE(0),
- .C_PROG_FULL_TYPE_AXIS(0),
- .C_PROG_FULL_TYPE_RACH(0),
- .C_PROG_FULL_TYPE_RDCH(0),
- .C_PROG_FULL_TYPE_WACH(0),
- .C_PROG_FULL_TYPE_WDCH(0),
- .C_PROG_FULL_TYPE_WRCH(0),
- .C_RACH_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(14),
- .C_RD_DEPTH(16384),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(14),
- .C_RDCH_TYPE(0),
- .C_REG_SLICE_MODE_AXIS(0),
- .C_REG_SLICE_MODE_RACH(0),
- .C_REG_SLICE_MODE_RDCH(0),
- .C_REG_SLICE_MODE_WACH(0),
- .C_REG_SLICE_MODE_WDCH(0),
- .C_REG_SLICE_MODE_WRCH(0),
- .C_SYNCHRONIZER_STAGE(2),
- .C_UNDERFLOW_LOW(0),
- .C_USE_COMMON_OVERFLOW(0),
- .C_USE_COMMON_UNDERFLOW(0),
- .C_USE_DEFAULT_SETTINGS(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_ECC_AXIS(0),
- .C_USE_ECC_RACH(0),
- .C_USE_ECC_RDCH(0),
- .C_USE_ECC_WACH(0),
- .C_USE_ECC_WDCH(0),
- .C_USE_ECC_WRCH(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WACH_TYPE(0),
- .C_WDCH_TYPE(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(14),
- .C_WR_DEPTH(16384),
- .C_WR_DEPTH_AXIS(1024),
- .C_WR_DEPTH_RACH(16),
- .C_WR_DEPTH_RDCH(1024),
- .C_WR_DEPTH_WACH(16),
- .C_WR_DEPTH_WDCH(1024),
- .C_WR_DEPTH_WRCH(16),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(14),
- .C_WR_PNTR_WIDTH_AXIS(10),
- .C_WR_PNTR_WIDTH_RACH(4),
- .C_WR_PNTR_WIDTH_RDCH(10),
- .C_WR_PNTR_WIDTH_WACH(4),
- .C_WR_PNTR_WIDTH_WDCH(10),
- .C_WR_PNTR_WIDTH_WRCH(4),
- .C_WR_RESPONSE_LATENCY(1),
- .C_WRCH_TYPE(0)
- )
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .OVERFLOW(overflow),
- .EMPTY(empty),
- .RD_DATA_COUNT(rd_data_count),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .WR_DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR(),
- .M_ACLK(),
- .S_ACLK(),
- .S_ARESETN(),
- .M_ACLK_EN(),
- .S_ACLK_EN(),
- .S_AXI_AWID(),
- .S_AXI_AWADDR(),
- .S_AXI_AWLEN(),
- .S_AXI_AWSIZE(),
- .S_AXI_AWBURST(),
- .S_AXI_AWLOCK(),
- .S_AXI_AWCACHE(),
- .S_AXI_AWPROT(),
- .S_AXI_AWQOS(),
- .S_AXI_AWREGION(),
- .S_AXI_AWUSER(),
- .S_AXI_AWVALID(),
- .S_AXI_AWREADY(),
- .S_AXI_WID(),
- .S_AXI_WDATA(),
- .S_AXI_WSTRB(),
- .S_AXI_WLAST(),
- .S_AXI_WUSER(),
- .S_AXI_WVALID(),
- .S_AXI_WREADY(),
- .S_AXI_BID(),
- .S_AXI_BRESP(),
- .S_AXI_BUSER(),
- .S_AXI_BVALID(),
- .S_AXI_BREADY(),
- .M_AXI_AWID(),
- .M_AXI_AWADDR(),
- .M_AXI_AWLEN(),
- .M_AXI_AWSIZE(),
- .M_AXI_AWBURST(),
- .M_AXI_AWLOCK(),
- .M_AXI_AWCACHE(),
- .M_AXI_AWPROT(),
- .M_AXI_AWQOS(),
- .M_AXI_AWREGION(),
- .M_AXI_AWUSER(),
- .M_AXI_AWVALID(),
- .M_AXI_AWREADY(),
- .M_AXI_WID(),
- .M_AXI_WDATA(),
- .M_AXI_WSTRB(),
- .M_AXI_WLAST(),
- .M_AXI_WUSER(),
- .M_AXI_WVALID(),
- .M_AXI_WREADY(),
- .M_AXI_BID(),
- .M_AXI_BRESP(),
- .M_AXI_BUSER(),
- .M_AXI_BVALID(),
- .M_AXI_BREADY(),
- .S_AXI_ARID(),
- .S_AXI_ARADDR(),
- .S_AXI_ARLEN(),
- .S_AXI_ARSIZE(),
- .S_AXI_ARBURST(),
- .S_AXI_ARLOCK(),
- .S_AXI_ARCACHE(),
- .S_AXI_ARPROT(),
- .S_AXI_ARQOS(),
- .S_AXI_ARREGION(),
- .S_AXI_ARUSER(),
- .S_AXI_ARVALID(),
- .S_AXI_ARREADY(),
- .S_AXI_RID(),
- .S_AXI_RDATA(),
- .S_AXI_RRESP(),
- .S_AXI_RLAST(),
- .S_AXI_RUSER(),
- .S_AXI_RVALID(),
- .S_AXI_RREADY(),
- .M_AXI_ARID(),
- .M_AXI_ARADDR(),
- .M_AXI_ARLEN(),
- .M_AXI_ARSIZE(),
- .M_AXI_ARBURST(),
- .M_AXI_ARLOCK(),
- .M_AXI_ARCACHE(),
- .M_AXI_ARPROT(),
- .M_AXI_ARQOS(),
- .M_AXI_ARREGION(),
- .M_AXI_ARUSER(),
- .M_AXI_ARVALID(),
- .M_AXI_ARREADY(),
- .M_AXI_RID(),
- .M_AXI_RDATA(),
- .M_AXI_RRESP(),
- .M_AXI_RLAST(),
- .M_AXI_RUSER(),
- .M_AXI_RVALID(),
- .M_AXI_RREADY(),
- .S_AXIS_TVALID(),
- .S_AXIS_TREADY(),
- .S_AXIS_TDATA(),
- .S_AXIS_TSTRB(),
- .S_AXIS_TKEEP(),
- .S_AXIS_TLAST(),
- .S_AXIS_TID(),
- .S_AXIS_TDEST(),
- .S_AXIS_TUSER(),
- .M_AXIS_TVALID(),
- .M_AXIS_TREADY(),
- .M_AXIS_TDATA(),
- .M_AXIS_TSTRB(),
- .M_AXIS_TKEEP(),
- .M_AXIS_TLAST(),
- .M_AXIS_TID(),
- .M_AXIS_TDEST(),
- .M_AXIS_TUSER(),
- .AXI_AW_INJECTSBITERR(),
- .AXI_AW_INJECTDBITERR(),
- .AXI_AW_PROG_FULL_THRESH(),
- .AXI_AW_PROG_EMPTY_THRESH(),
- .AXI_AW_DATA_COUNT(),
- .AXI_AW_WR_DATA_COUNT(),
- .AXI_AW_RD_DATA_COUNT(),
- .AXI_AW_SBITERR(),
- .AXI_AW_DBITERR(),
- .AXI_AW_OVERFLOW(),
- .AXI_AW_UNDERFLOW(),
- .AXI_AW_PROG_FULL(),
- .AXI_AW_PROG_EMPTY(),
- .AXI_W_INJECTSBITERR(),
- .AXI_W_INJECTDBITERR(),
- .AXI_W_PROG_FULL_THRESH(),
- .AXI_W_PROG_EMPTY_THRESH(),
- .AXI_W_DATA_COUNT(),
- .AXI_W_WR_DATA_COUNT(),
- .AXI_W_RD_DATA_COUNT(),
- .AXI_W_SBITERR(),
- .AXI_W_DBITERR(),
- .AXI_W_OVERFLOW(),
- .AXI_W_UNDERFLOW(),
- .AXI_B_INJECTSBITERR(),
- .AXI_W_PROG_FULL(),
- .AXI_W_PROG_EMPTY(),
- .AXI_B_INJECTDBITERR(),
- .AXI_B_PROG_FULL_THRESH(),
- .AXI_B_PROG_EMPTY_THRESH(),
- .AXI_B_DATA_COUNT(),
- .AXI_B_WR_DATA_COUNT(),
- .AXI_B_RD_DATA_COUNT(),
- .AXI_B_SBITERR(),
- .AXI_B_DBITERR(),
- .AXI_B_OVERFLOW(),
- .AXI_B_UNDERFLOW(),
- .AXI_AR_INJECTSBITERR(),
- .AXI_B_PROG_FULL(),
- .AXI_B_PROG_EMPTY(),
- .AXI_AR_INJECTDBITERR(),
- .AXI_AR_PROG_FULL_THRESH(),
- .AXI_AR_PROG_EMPTY_THRESH(),
- .AXI_AR_DATA_COUNT(),
- .AXI_AR_WR_DATA_COUNT(),
- .AXI_AR_RD_DATA_COUNT(),
- .AXI_AR_SBITERR(),
- .AXI_AR_DBITERR(),
- .AXI_AR_OVERFLOW(),
- .AXI_AR_UNDERFLOW(),
- .AXI_AR_PROG_FULL(),
- .AXI_AR_PROG_EMPTY(),
- .AXI_R_INJECTSBITERR(),
- .AXI_R_INJECTDBITERR(),
- .AXI_R_PROG_FULL_THRESH(),
- .AXI_R_PROG_EMPTY_THRESH(),
- .AXI_R_DATA_COUNT(),
- .AXI_R_WR_DATA_COUNT(),
- .AXI_R_RD_DATA_COUNT(),
- .AXI_R_SBITERR(),
- .AXI_R_DBITERR(),
- .AXI_R_OVERFLOW(),
- .AXI_R_UNDERFLOW(),
- .AXIS_INJECTSBITERR(),
- .AXI_R_PROG_FULL(),
- .AXI_R_PROG_EMPTY(),
- .AXIS_INJECTDBITERR(),
- .AXIS_PROG_FULL_THRESH(),
- .AXIS_PROG_EMPTY_THRESH(),
- .AXIS_DATA_COUNT(),
- .AXIS_WR_DATA_COUNT(),
- .AXIS_RD_DATA_COUNT(),
- .AXIS_SBITERR(),
- .AXIS_DBITERR(),
- .AXIS_OVERFLOW(),
- .AXIS_UNDERFLOW(),
- .AXIS_PROG_FULL(),
- .AXIS_PROG_EMPTY()
- );
-
-// synthesis translate_on
-
-endmodule
diff --git a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xci b/src/rtl/ip/nandadr_fifo/nandadr_fifo.xci
deleted file mode 100644
index 9c20cd4..0000000
--- a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xci
+++ /dev/null
@@ -1,378 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>nandadr_fifo</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">nandadr_fifo</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">30</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">16384</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">30</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">16384</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">16381</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">16380</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">8</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">spartan6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc6slx45</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xco b/src/rtl/ip/nandadr_fifo/nandadr_fifo.xco
deleted file mode 100644
index a6c6bcd..0000000
--- a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.3
-# Date: Tue Sep 30 16:17:28 2014
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=nandadr_fifo
-CSET data_count=false
-CSET data_count_width=14
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=3
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=16381
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=16380
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=30
-CSET input_depth=16384
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=30
-CSET output_depth=16384
-CSET overflow_flag=true
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=14
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=14
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-07-25T18:11:59Z
-# END Extra information
-GENERATE
-# CRC: a096c9ea
diff --git a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xise b/src/rtl/ip/nandadr_fifo/nandadr_fifo.xise
deleted file mode 100644
index d514f05..0000000
--- a/src/rtl/ip/nandadr_fifo/nandadr_fifo.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="nandadr_fifo.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="nandadr_fifo.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|nandadr_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="nandadr_fifo.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/nandadr_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="nandadr_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-30T12:19:24" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="EF4E589646C08AE4847EB1D43F3656A3" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/src/rtl/ip/uk_fifo/uk_fifo.v b/src/rtl/ip/uk_fifo/uk_fifo.v
deleted file mode 100644
index 27de6da..0000000
--- a/src/rtl/ip/uk_fifo/uk_fifo.v
+++ /dev/null
@@ -1,491 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used solely *
-* for design, simulation, implementation and creation of design files *
-* limited to Xilinx devices or technologies. Use with non-Xilinx *
-* devices or technologies is expressly prohibited and immediately *
-* terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
-* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
-* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
-* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
-* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
-* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
-* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
-* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
-* PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support appliances, *
-* devices, or systems. Use in such applications are expressly *
-* prohibited. *
-* *
-* (c) Copyright 1995-2014 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// You must compile the wrapper file uk_fifo.v when simulating
-// the core, uk_fifo. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-`timescale 1ns/1ps
-
-module uk_fifo(
- rst,
- wr_clk,
- rd_clk,
- din,
- wr_en,
- rd_en,
- dout,
- full,
- overflow,
- empty,
- rd_data_count
-);
-
-input rst;
-input wr_clk;
-input rd_clk;
-input [7 : 0] din;
-input wr_en;
-input rd_en;
-output [7 : 0] dout;
-output full;
-output overflow;
-output empty;
-output [11 : 0] rd_data_count;
-
-// synthesis translate_off
-
- FIFO_GENERATOR_V9_3 #(
- .C_ADD_NGC_CONSTRAINT(0),
- .C_APPLICATION_TYPE_AXIS(0),
- .C_APPLICATION_TYPE_RACH(0),
- .C_APPLICATION_TYPE_RDCH(0),
- .C_APPLICATION_TYPE_WACH(0),
- .C_APPLICATION_TYPE_WDCH(0),
- .C_APPLICATION_TYPE_WRCH(0),
- .C_AXI_ADDR_WIDTH(32),
- .C_AXI_ARUSER_WIDTH(1),
- .C_AXI_AWUSER_WIDTH(1),
- .C_AXI_BUSER_WIDTH(1),
- .C_AXI_DATA_WIDTH(64),
- .C_AXI_ID_WIDTH(4),
- .C_AXI_RUSER_WIDTH(1),
- .C_AXI_TYPE(0),
- .C_AXI_WUSER_WIDTH(1),
- .C_AXIS_TDATA_WIDTH(64),
- .C_AXIS_TDEST_WIDTH(4),
- .C_AXIS_TID_WIDTH(8),
- .C_AXIS_TKEEP_WIDTH(4),
- .C_AXIS_TSTRB_WIDTH(4),
- .C_AXIS_TUSER_WIDTH(4),
- .C_AXIS_TYPE(0),
- .C_COMMON_CLOCK(0),
- .C_COUNT_TYPE(0),
- .C_DATA_COUNT_WIDTH(12),
- .C_DEFAULT_VALUE("BlankString"),
- .C_DIN_WIDTH(8),
- .C_DIN_WIDTH_AXIS(1),
- .C_DIN_WIDTH_RACH(32),
- .C_DIN_WIDTH_RDCH(64),
- .C_DIN_WIDTH_WACH(32),
- .C_DIN_WIDTH_WDCH(64),
- .C_DIN_WIDTH_WRCH(2),
- .C_DOUT_RST_VAL("0"),
- .C_DOUT_WIDTH(8),
- .C_ENABLE_RLOCS(0),
- .C_ENABLE_RST_SYNC(1),
- .C_ERROR_INJECTION_TYPE(0),
- .C_ERROR_INJECTION_TYPE_AXIS(0),
- .C_ERROR_INJECTION_TYPE_RACH(0),
- .C_ERROR_INJECTION_TYPE_RDCH(0),
- .C_ERROR_INJECTION_TYPE_WACH(0),
- .C_ERROR_INJECTION_TYPE_WDCH(0),
- .C_ERROR_INJECTION_TYPE_WRCH(0),
- .C_FAMILY("spartan6"),
- .C_FULL_FLAGS_RST_VAL(1),
- .C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
- .C_HAS_AXI_ARUSER(0),
- .C_HAS_AXI_AWUSER(0),
- .C_HAS_AXI_BUSER(0),
- .C_HAS_AXI_RD_CHANNEL(0),
- .C_HAS_AXI_RUSER(0),
- .C_HAS_AXI_WR_CHANNEL(0),
- .C_HAS_AXI_WUSER(0),
- .C_HAS_AXIS_TDATA(0),
- .C_HAS_AXIS_TDEST(0),
- .C_HAS_AXIS_TID(0),
- .C_HAS_AXIS_TKEEP(0),
- .C_HAS_AXIS_TLAST(0),
- .C_HAS_AXIS_TREADY(1),
- .C_HAS_AXIS_TSTRB(0),
- .C_HAS_AXIS_TUSER(0),
- .C_HAS_BACKUP(0),
- .C_HAS_DATA_COUNT(0),
- .C_HAS_DATA_COUNTS_AXIS(0),
- .C_HAS_DATA_COUNTS_RACH(0),
- .C_HAS_DATA_COUNTS_RDCH(0),
- .C_HAS_DATA_COUNTS_WACH(0),
- .C_HAS_DATA_COUNTS_WDCH(0),
- .C_HAS_DATA_COUNTS_WRCH(0),
- .C_HAS_INT_CLK(0),
- .C_HAS_MASTER_CE(0),
- .C_HAS_MEMINIT_FILE(0),
- .C_HAS_OVERFLOW(1),
- .C_HAS_PROG_FLAGS_AXIS(0),
- .C_HAS_PROG_FLAGS_RACH(0),
- .C_HAS_PROG_FLAGS_RDCH(0),
- .C_HAS_PROG_FLAGS_WACH(0),
- .C_HAS_PROG_FLAGS_WDCH(0),
- .C_HAS_PROG_FLAGS_WRCH(0),
- .C_HAS_RD_DATA_COUNT(1),
- .C_HAS_RD_RST(0),
- .C_HAS_RST(1),
- .C_HAS_SLAVE_CE(0),
- .C_HAS_SRST(0),
- .C_HAS_UNDERFLOW(0),
- .C_HAS_VALID(0),
- .C_HAS_WR_ACK(0),
- .C_HAS_WR_DATA_COUNT(0),
- .C_HAS_WR_RST(0),
- .C_IMPLEMENTATION_TYPE(2),
- .C_IMPLEMENTATION_TYPE_AXIS(1),
- .C_IMPLEMENTATION_TYPE_RACH(1),
- .C_IMPLEMENTATION_TYPE_RDCH(1),
- .C_IMPLEMENTATION_TYPE_WACH(1),
- .C_IMPLEMENTATION_TYPE_WDCH(1),
- .C_IMPLEMENTATION_TYPE_WRCH(1),
- .C_INIT_WR_PNTR_VAL(0),
- .C_INTERFACE_TYPE(0),
- .C_MEMORY_TYPE(1),
- .C_MIF_FILE_NAME("BlankString"),
- .C_MSGON_VAL(1),
- .C_OPTIMIZATION_MODE(0),
- .C_OVERFLOW_LOW(0),
- .C_PRELOAD_LATENCY(1),
- .C_PRELOAD_REGS(0),
- .C_PRIM_FIFO_TYPE("4kx9"),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
- .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
- .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
- .C_PROG_EMPTY_TYPE(0),
- .C_PROG_EMPTY_TYPE_AXIS(0),
- .C_PROG_EMPTY_TYPE_RACH(0),
- .C_PROG_EMPTY_TYPE_RDCH(0),
- .C_PROG_EMPTY_TYPE_WACH(0),
- .C_PROG_EMPTY_TYPE_WDCH(0),
- .C_PROG_EMPTY_TYPE_WRCH(0),
- .C_PROG_FULL_THRESH_ASSERT_VAL(4093),
- .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
- .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
- .C_PROG_FULL_THRESH_NEGATE_VAL(4092),
- .C_PROG_FULL_TYPE(0),
- .C_PROG_FULL_TYPE_AXIS(0),
- .C_PROG_FULL_TYPE_RACH(0),
- .C_PROG_FULL_TYPE_RDCH(0),
- .C_PROG_FULL_TYPE_WACH(0),
- .C_PROG_FULL_TYPE_WDCH(0),
- .C_PROG_FULL_TYPE_WRCH(0),
- .C_RACH_TYPE(0),
- .C_RD_DATA_COUNT_WIDTH(12),
- .C_RD_DEPTH(4096),
- .C_RD_FREQ(1),
- .C_RD_PNTR_WIDTH(12),
- .C_RDCH_TYPE(0),
- .C_REG_SLICE_MODE_AXIS(0),
- .C_REG_SLICE_MODE_RACH(0),
- .C_REG_SLICE_MODE_RDCH(0),
- .C_REG_SLICE_MODE_WACH(0),
- .C_REG_SLICE_MODE_WDCH(0),
- .C_REG_SLICE_MODE_WRCH(0),
- .C_SYNCHRONIZER_STAGE(2),
- .C_UNDERFLOW_LOW(0),
- .C_USE_COMMON_OVERFLOW(0),
- .C_USE_COMMON_UNDERFLOW(0),
- .C_USE_DEFAULT_SETTINGS(0),
- .C_USE_DOUT_RST(1),
- .C_USE_ECC(0),
- .C_USE_ECC_AXIS(0),
- .C_USE_ECC_RACH(0),
- .C_USE_ECC_RDCH(0),
- .C_USE_ECC_WACH(0),
- .C_USE_ECC_WDCH(0),
- .C_USE_ECC_WRCH(0),
- .C_USE_EMBEDDED_REG(0),
- .C_USE_FIFO16_FLAGS(0),
- .C_USE_FWFT_DATA_COUNT(0),
- .C_VALID_LOW(0),
- .C_WACH_TYPE(0),
- .C_WDCH_TYPE(0),
- .C_WR_ACK_LOW(0),
- .C_WR_DATA_COUNT_WIDTH(12),
- .C_WR_DEPTH(4096),
- .C_WR_DEPTH_AXIS(1024),
- .C_WR_DEPTH_RACH(16),
- .C_WR_DEPTH_RDCH(1024),
- .C_WR_DEPTH_WACH(16),
- .C_WR_DEPTH_WDCH(1024),
- .C_WR_DEPTH_WRCH(16),
- .C_WR_FREQ(1),
- .C_WR_PNTR_WIDTH(12),
- .C_WR_PNTR_WIDTH_AXIS(10),
- .C_WR_PNTR_WIDTH_RACH(4),
- .C_WR_PNTR_WIDTH_RDCH(10),
- .C_WR_PNTR_WIDTH_WACH(4),
- .C_WR_PNTR_WIDTH_WDCH(10),
- .C_WR_PNTR_WIDTH_WRCH(4),
- .C_WR_RESPONSE_LATENCY(1),
- .C_WRCH_TYPE(0)
- )
- inst (
- .RST(rst),
- .WR_CLK(wr_clk),
- .RD_CLK(rd_clk),
- .DIN(din),
- .WR_EN(wr_en),
- .RD_EN(rd_en),
- .DOUT(dout),
- .FULL(full),
- .OVERFLOW(overflow),
- .EMPTY(empty),
- .RD_DATA_COUNT(rd_data_count),
- .BACKUP(),
- .BACKUP_MARKER(),
- .CLK(),
- .SRST(),
- .WR_RST(),
- .RD_RST(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .INT_CLK(),
- .INJECTDBITERR(),
- .INJECTSBITERR(),
- .ALMOST_FULL(),
- .WR_ACK(),
- .ALMOST_EMPTY(),
- .VALID(),
- .UNDERFLOW(),
- .DATA_COUNT(),
- .WR_DATA_COUNT(),
- .PROG_FULL(),
- .PROG_EMPTY(),
- .SBITERR(),
- .DBITERR(),
- .M_ACLK(),
- .S_ACLK(),
- .S_ARESETN(),
- .M_ACLK_EN(),
- .S_ACLK_EN(),
- .S_AXI_AWID(),
- .S_AXI_AWADDR(),
- .S_AXI_AWLEN(),
- .S_AXI_AWSIZE(),
- .S_AXI_AWBURST(),
- .S_AXI_AWLOCK(),
- .S_AXI_AWCACHE(),
- .S_AXI_AWPROT(),
- .S_AXI_AWQOS(),
- .S_AXI_AWREGION(),
- .S_AXI_AWUSER(),
- .S_AXI_AWVALID(),
- .S_AXI_AWREADY(),
- .S_AXI_WID(),
- .S_AXI_WDATA(),
- .S_AXI_WSTRB(),
- .S_AXI_WLAST(),
- .S_AXI_WUSER(),
- .S_AXI_WVALID(),
- .S_AXI_WREADY(),
- .S_AXI_BID(),
- .S_AXI_BRESP(),
- .S_AXI_BUSER(),
- .S_AXI_BVALID(),
- .S_AXI_BREADY(),
- .M_AXI_AWID(),
- .M_AXI_AWADDR(),
- .M_AXI_AWLEN(),
- .M_AXI_AWSIZE(),
- .M_AXI_AWBURST(),
- .M_AXI_AWLOCK(),
- .M_AXI_AWCACHE(),
- .M_AXI_AWPROT(),
- .M_AXI_AWQOS(),
- .M_AXI_AWREGION(),
- .M_AXI_AWUSER(),
- .M_AXI_AWVALID(),
- .M_AXI_AWREADY(),
- .M_AXI_WID(),
- .M_AXI_WDATA(),
- .M_AXI_WSTRB(),
- .M_AXI_WLAST(),
- .M_AXI_WUSER(),
- .M_AXI_WVALID(),
- .M_AXI_WREADY(),
- .M_AXI_BID(),
- .M_AXI_BRESP(),
- .M_AXI_BUSER(),
- .M_AXI_BVALID(),
- .M_AXI_BREADY(),
- .S_AXI_ARID(),
- .S_AXI_ARADDR(),
- .S_AXI_ARLEN(),
- .S_AXI_ARSIZE(),
- .S_AXI_ARBURST(),
- .S_AXI_ARLOCK(),
- .S_AXI_ARCACHE(),
- .S_AXI_ARPROT(),
- .S_AXI_ARQOS(),
- .S_AXI_ARREGION(),
- .S_AXI_ARUSER(),
- .S_AXI_ARVALID(),
- .S_AXI_ARREADY(),
- .S_AXI_RID(),
- .S_AXI_RDATA(),
- .S_AXI_RRESP(),
- .S_AXI_RLAST(),
- .S_AXI_RUSER(),
- .S_AXI_RVALID(),
- .S_AXI_RREADY(),
- .M_AXI_ARID(),
- .M_AXI_ARADDR(),
- .M_AXI_ARLEN(),
- .M_AXI_ARSIZE(),
- .M_AXI_ARBURST(),
- .M_AXI_ARLOCK(),
- .M_AXI_ARCACHE(),
- .M_AXI_ARPROT(),
- .M_AXI_ARQOS(),
- .M_AXI_ARREGION(),
- .M_AXI_ARUSER(),
- .M_AXI_ARVALID(),
- .M_AXI_ARREADY(),
- .M_AXI_RID(),
- .M_AXI_RDATA(),
- .M_AXI_RRESP(),
- .M_AXI_RLAST(),
- .M_AXI_RUSER(),
- .M_AXI_RVALID(),
- .M_AXI_RREADY(),
- .S_AXIS_TVALID(),
- .S_AXIS_TREADY(),
- .S_AXIS_TDATA(),
- .S_AXIS_TSTRB(),
- .S_AXIS_TKEEP(),
- .S_AXIS_TLAST(),
- .S_AXIS_TID(),
- .S_AXIS_TDEST(),
- .S_AXIS_TUSER(),
- .M_AXIS_TVALID(),
- .M_AXIS_TREADY(),
- .M_AXIS_TDATA(),
- .M_AXIS_TSTRB(),
- .M_AXIS_TKEEP(),
- .M_AXIS_TLAST(),
- .M_AXIS_TID(),
- .M_AXIS_TDEST(),
- .M_AXIS_TUSER(),
- .AXI_AW_INJECTSBITERR(),
- .AXI_AW_INJECTDBITERR(),
- .AXI_AW_PROG_FULL_THRESH(),
- .AXI_AW_PROG_EMPTY_THRESH(),
- .AXI_AW_DATA_COUNT(),
- .AXI_AW_WR_DATA_COUNT(),
- .AXI_AW_RD_DATA_COUNT(),
- .AXI_AW_SBITERR(),
- .AXI_AW_DBITERR(),
- .AXI_AW_OVERFLOW(),
- .AXI_AW_UNDERFLOW(),
- .AXI_AW_PROG_FULL(),
- .AXI_AW_PROG_EMPTY(),
- .AXI_W_INJECTSBITERR(),
- .AXI_W_INJECTDBITERR(),
- .AXI_W_PROG_FULL_THRESH(),
- .AXI_W_PROG_EMPTY_THRESH(),
- .AXI_W_DATA_COUNT(),
- .AXI_W_WR_DATA_COUNT(),
- .AXI_W_RD_DATA_COUNT(),
- .AXI_W_SBITERR(),
- .AXI_W_DBITERR(),
- .AXI_W_OVERFLOW(),
- .AXI_W_UNDERFLOW(),
- .AXI_B_INJECTSBITERR(),
- .AXI_W_PROG_FULL(),
- .AXI_W_PROG_EMPTY(),
- .AXI_B_INJECTDBITERR(),
- .AXI_B_PROG_FULL_THRESH(),
- .AXI_B_PROG_EMPTY_THRESH(),
- .AXI_B_DATA_COUNT(),
- .AXI_B_WR_DATA_COUNT(),
- .AXI_B_RD_DATA_COUNT(),
- .AXI_B_SBITERR(),
- .AXI_B_DBITERR(),
- .AXI_B_OVERFLOW(),
- .AXI_B_UNDERFLOW(),
- .AXI_AR_INJECTSBITERR(),
- .AXI_B_PROG_FULL(),
- .AXI_B_PROG_EMPTY(),
- .AXI_AR_INJECTDBITERR(),
- .AXI_AR_PROG_FULL_THRESH(),
- .AXI_AR_PROG_EMPTY_THRESH(),
- .AXI_AR_DATA_COUNT(),
- .AXI_AR_WR_DATA_COUNT(),
- .AXI_AR_RD_DATA_COUNT(),
- .AXI_AR_SBITERR(),
- .AXI_AR_DBITERR(),
- .AXI_AR_OVERFLOW(),
- .AXI_AR_UNDERFLOW(),
- .AXI_AR_PROG_FULL(),
- .AXI_AR_PROG_EMPTY(),
- .AXI_R_INJECTSBITERR(),
- .AXI_R_INJECTDBITERR(),
- .AXI_R_PROG_FULL_THRESH(),
- .AXI_R_PROG_EMPTY_THRESH(),
- .AXI_R_DATA_COUNT(),
- .AXI_R_WR_DATA_COUNT(),
- .AXI_R_RD_DATA_COUNT(),
- .AXI_R_SBITERR(),
- .AXI_R_DBITERR(),
- .AXI_R_OVERFLOW(),
- .AXI_R_UNDERFLOW(),
- .AXIS_INJECTSBITERR(),
- .AXI_R_PROG_FULL(),
- .AXI_R_PROG_EMPTY(),
- .AXIS_INJECTDBITERR(),
- .AXIS_PROG_FULL_THRESH(),
- .AXIS_PROG_EMPTY_THRESH(),
- .AXIS_DATA_COUNT(),
- .AXIS_WR_DATA_COUNT(),
- .AXIS_RD_DATA_COUNT(),
- .AXIS_SBITERR(),
- .AXIS_DBITERR(),
- .AXIS_OVERFLOW(),
- .AXIS_UNDERFLOW(),
- .AXIS_PROG_FULL(),
- .AXIS_PROG_EMPTY()
- );
-
-// synthesis translate_on
-
-endmodule
diff --git a/src/rtl/ip/uk_fifo/uk_fifo.xci b/src/rtl/ip/uk_fifo/uk_fifo.xci
deleted file mode 100644
index bafc8f8..0000000
--- a/src/rtl/ip/uk_fifo/uk_fifo.xci
+++ /dev/null
@@ -1,378 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>uk_fifo</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">uk_fifo</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">4096</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">4096</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">4093</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">4092</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WACH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WDCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_WRCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RACH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_RDCH">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_SLICE_MODE_AXIS">Fully_Registered</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_POINTER_INCREMENT_BY2">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
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diff --git a/src/rtl/ip/uk_fifo/uk_fifo.xco b/src/rtl/ip/uk_fifo/uk_fifo.xco
deleted file mode 100644
index 4be7520..0000000
--- a/src/rtl/ip/uk_fifo/uk_fifo.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.3
-# Date: Tue Sep 30 16:15:53 2014
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=uk_fifo
-CSET data_count=false
-CSET data_count_width=12
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=3
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=4093
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=4092
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=4096
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=4096
-CSET overflow_flag=true
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=12
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=12
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-07-25T18:11:59Z
-# END Extra information
-GENERATE
-# CRC: 2d113534
diff --git a/src/rtl/ip/uk_fifo/uk_fifo.xise b/src/rtl/ip/uk_fifo/uk_fifo.xise
deleted file mode 100644
index 8dc271b..0000000
--- a/src/rtl/ip/uk_fifo/uk_fifo.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="uk_fifo.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="uk_fifo.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top" xil_pn:value="Module|uk_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="uk_fifo.ngc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uk_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_DesignName" xil_pn:value="uk_fifo" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-30T12:17:17" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2745CDA7D3BDDAE1F7BE1495A8765992" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/src/rtl/nand_log_tb.v b/src/rtl/nand_log_tb.v
deleted file mode 100755
index 51fa59d..0000000
--- a/src/rtl/nand_log_tb.v
+++ /dev/null
@@ -1,225 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 2013, Andrew "bunnie" Huang
-//
-// See the NOTICE file distributed with this work for additional
-// information regarding copyright ownership. The copyright holder
-// licenses this file to you under the Apache License, Version 2.0
-// (the "License"); you may not use this file except in compliance
-// with the License. You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing,
-// code distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations
-// under the License.
-//////////////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-
-module nand_log_tb;
- reg bclk; // 133 Mhz clock
- reg clk100; // 100 Mhz clock
-
- reg nand_re;
- reg nand_we;
- reg nand_ale;
- reg nand_cle;
- reg nand_cs;
- reg nand_rb;
- reg [7:0] nand_din;
- reg [9:0] nand_uk;
-
- reg log_reset;
- reg log_run;
- wire log_cmd_error; // stuck high if cmd fifo overflowed during logging
- wire log_data_error; // stuck high if data fifo overflowed during logging
- wire [26:0] log_entries; // number of entries currently in the log
-
- wire [3:0] ddr3_wr_mask;
- wire [31:0] ddr3_wr_data;
- wire ddr3_wr_en;
- reg ddr3_wr_full;
- reg [6:0] ddr3_wr_count;
- wire ddr3_cmd_clk;
- wire [2:0] ddr3_cmd_instr;
- wire ddr3_cmd_en;
- wire [5:0] ddr3_cmd_burstlen;
- wire [29:0] ddr3_cmd_addr;
- reg ddr3_cmd_full;
-
- wire [63:0] time_t_clk100; // note synched to clk100
- reg reset;
-
-nand_log uut(
- bclk, // 133 Mhz clock
- clk100, // 100 Mhz clock
-
- nand_re,
- nand_we,
- nand_ale,
- nand_cle,
- nand_cs,
- nand_rb,
- nand_din,
- nand_uk,
-
- log_reset,
- log_run,
- log_cmd_error, // stuck high if cmd fifo overflowed during logging
- log_data_error, // stuck high if data fifo overflowed during logging
- log_entries, // number of entries currently in the log
-
- ddr3_wr_mask,
- ddr3_wr_data,
- ddr3_wr_en,
- ddr3_wr_full,
- ddr3_wr_count,
- ddr3_cmd_clk,
- ddr3_cmd_instr,
- ddr3_cmd_en,
- ddr3_cmd_burstlen,
- ddr3_cmd_addr,
- ddr3_cmd_full,
-
- time_t_clk100, // note synched to clk100
- reset
- );
-
- parameter PERIOD_BCLK = 16'd8; // 125 MHz (close to 133 MHz actual)
- always begin
- bclk = 1'b0;
- #(PERIOD_BCLK/2) bclk = 1'b1;
- #(PERIOD_BCLK/2);
- end
-
- parameter PERIOD_CLK100 = 16'd10;
- always begin
- clk100 = 1'b0;
- #(PERIOD_CLK100/2) clk100 = 1'b1;
- #(PERIOD_CLK100/2);
- end
-
- task nand_reset;
- begin
- nand_we = 1'b1;
- nand_re = 1'b1;
- nand_ale = 1'b0;
- nand_cle = 1'b0;
- nand_cs = 1'b1;
- nand_din = 8'hZZ;
-
- log_reset = 1'b1;
- log_run = 1'b0;
- #1000;
- log_reset = 1'b0;
- log_run = 1'b1;
- #1000;
- end
- endtask // nand_reset
-
- task nand_idle;
- begin
- nand_we = 1'b1;
- nand_re = 1'b1;
- nand_ale = 1'b0;
- nand_cle = 1'b0;
- nand_cs = 1'b1;
- nand_din = 8'hZZ;
- end
- endtask // nand_idle
-
- task nand_read_id;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_we = 1'b0;
- nand_din = 8'h90;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_din = 8'h01;
- #20;
-
- nand_ale = 1'b1;
- #25;
-
- nand_we = 1'b0;
- nand_din = 8'h00;
- #25;
- nand_we = 1'b1;
- #5;
- nand_din = 8'h23;
- #20;
-
- nand_ale = 1'b0;
-
- #10;
- nand_re = 1'b0;
- nand_din = 8'h45;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- nand_din = 8'h67;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- nand_din = 8'h89;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- nand_din = 8'hAB;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- nand_din = 8'hCD;
- #25;
- nand_re = 1'b1;
- #25;
-
- nand_cs = 1'b1;
- end
- endtask; // nand_read_id
-
- initial begin
- nand_re = 1;
- nand_we = 1;
- nand_ale = 0;
- nand_cle = 0;
- nand_rb = 1;
- nand_din = 8'h00;
- nand_uk[9:0] = 10'h0;
- nand_cs = 1;
-
- log_reset = 1'b0;
- log_run = 1'b0;
- ddr3_wr_full = 1'b0;
- ddr3_wr_count = 7'b0;
- ddr3_cmd_full = 1'b0;
-
- reset = 1;
- #1000;
- reset = 0;
- nand_reset();
- #1000;
-
- nand_idle();
- #200;
- nand_read_id();
-
- $stop;
-
- #1000;
- $stop;
- end
-
-endmodule // nand_log_tb
-
-
diff --git a/src/rtl/novena_fpga.v b/src/rtl/novena_fpga.v
index 442bbf4..27bc2f8 100755
--- a/src/rtl/novena_fpga.v
+++ b/src/rtl/novena_fpga.v
@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 2013, Andrew "bunnie" Huang
+// Copyright (c) 2014, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
@@ -16,158 +16,223 @@
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
-`timescale 1ns / 1ps
-//`define USE_ROMULATOR 1
+`timescale 1ns / 1ps
module novena_fpga(
- output wire APOPTOSIS,
-
- input wire AUD6_TFS,
- input wire AUD6_TXC,
- input wire AUD6_TXD,
- input wire AUD_MCLK,
- input wire AUD_MIC_CLK,
- input wire AUD_MIC_DAT,
-
- input wire BATT_NRST,
- input wire BATT_REFLASH_ALRT,
-
- input wire CLK2_N,
- input wire CLK2_P,
-
- input wire DDC_SCL,
- input wire DDC_SDA,
-
- output wire ECSPI3_MISO,
- input wire ECSPI3_MOSI,
- input wire ECSPI3_RDY,
- input wire ECSPI3_SCLK,
- input wire ECSPI3_SS2,
-
+ // CPU EIM register interface mapping
input wire EIM_BCLK,
input wire [1:0] EIM_CS,
- inout wire [15:0] EIM_DA,
input wire [18:16] EIM_A,
input wire EIM_LBA,
input wire EIM_OE,
input wire EIM_RW,
- input wire EIM_WAIT,
-
- output wire FPGA_LED2,
- input wire FPGA_LSPI_CLK,
- input wire FPGA_LSPI_CS,
- input wire FPGA_LSPI_HOLD,
- input wire FPGA_LSPI_MISO,
- input wire FPGA_LSPI_MOSI,
- input wire FPGA_LSPI_WP,
+ inout wire [15:0] EIM_DA,
+
+`ifdef UNDEFINED
+ ////// expansion connector side mapping
+ // CPU->DUT mappings bank A
+ output wire F_LVDS_P15,
+ output wire F_LVDS_N15,
+ output wire F_LVDS_P0,
+ output wire F_LVDS_N0,
+ output wire F_LVDS_CK1_P,
+ output wire F_LVDS_CK1_N,
+ output wire F_DX14,
+ output wire F_LVDS_P4,
+ // CPU->DUT mappings bank B
+ output wire F_LVDS_P11,
+ output wire F_LVDS_N11,
+ output wire F_DX1,
+ output wire F_LVDS_NC,
+ output wire F_LVDS_PC,
+ output wire F_DX17,
+ output wire F_LVDS_NB,
+ output wire F_LVDS_PB,
+
+ output wire F_LVDS_P7, // OE_N control for CPU->DUT bank A mappings
+ output wire F_LVDS_N7, // OE_N control for CPU->DUT bank B mappings
+
+ // DUT->CPU mappings
+ input wire F_DX18,
+ input wire F_LVDS_CK0_N,
+ input wire F_LVDS_CK0_P,
+ input wire F_LVDS_P9,
+ input wire F_DX0,
+ input wire F_DX3,
+ input wire F_DX2,
+ input wire F_DX11,
+
+ /// board control
+ output wire F_DX15, // output voltage select, 1 = Low V, 0 = 5V
+ input wire F_LVDS_NA, // OC flag
+
+ /// ADC
+ output wire F_DX13, // CS
+ output wire F_DX7, // SCLK
+ output wire F_DX6, // DIN
+ input wire F_DX12, // DOUT
input wire I2C3_SCL,
- input wire I2C3_SDA,
-
- input wire SMB_SCL,
- input wire SMB_SDA,
-
- input wire UART4_CTS,
- input wire UART4_RTS,
- input wire UART4_RXD,
- input wire UART4_TXD,
-
- // input wire UIM_CLK,
- // input wire UIM_DATA,
- // input wire UIM_PWR,
- // input wire UIM_PWRON,
- // input wire UIM_RESET,
-
- input wire F_LVDS_CK_P0, // sck
- input wire F_LVDS_CK_N0, // si
- input wire F_DX18, // cs input
- output wire F_LVDS_P11, // so
- output wire F_LVDS_P15, // cs output
-
- output wire F_LVDS_N7, // drivers
- output wire F_LVDS_P7,
-
- input wire RESETBMCU
+ inout wire I2C3_SDA,
+`endif // UNDEFINED
+
+ //// clocks n stuff
+ input wire CLK2_N, // free-runs at 50 MHz
+ input wire CLK2_P,
+ output wire FPGA_LED2,
+ input wire RESETBMCU,
+ output wire APOPTOSIS
);
wire [15:0] eim_dout;
wire [15:0] eim_din;
wire clk; // free-runs at 50 MHz, unbuffered
wire clk50; // zero-delay, DLL version of above. Use this.
- wire clk100; // doubled-up version of the above. For time base applications.
wire bclk; // NOTE: doesn't run until first CPU access to EIM; then free-runs at 133 MHz
reg [23:0] counter;
-
- wire ddr3_dll_locked;
- wire ddr3clk;
-
-
wire reset;
- reg emulate_r;
-
- always @(posedge spiclk) begin
- emulate_r <= emulate;
- end
-
- assign F_LVDS_N7 = !emulate_r; // drives so when low -- set to 1 for bypass mode
- assign F_LVDS_P7 = 1'b0; // drives cs when low
-
- // P15 is cs output to SPINOR
- assign F_LVDS_P15 = emulate_r ? 1'b1 : F_DX18;
-// assign F_LVDS_P15 = F_DX18; // set this for bypass mode
-// assign F_LVDS_P15 = 1'b1; // set to 1 to disable SPINOR during emulation
-// assign F_LVDS_P11 = 1'bz;
-
-
- ////////////////////////////////////
- ///// MASTER RESET
- ////////////////////////////////////
-
- sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );
-
- wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
- wire bclk_early;
-
- ////////////////////////////////////
- ///// BCLK DLL -- generate zero-delay clock plus slower versions for internal use
- ////////////////////////////////////
- wire bclk_int_in, bclk_io_in;
- IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
- BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
-
- bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
- .RESET(reset), .LOCKED(bclk_locked));
- wire i_reset, i_locked;
- wire o_reset, o_locked;
- wire bclk_i, bclk_o;
- wire i_fbk_out, i_fbk_in;
- wire o_fbk_out, o_fbk_in;
-
- dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
- .CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
- .RESET(i_reset), .LOCKED(i_locked));
+ wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
+ wire bclk_early;
+ wire bclk_i, bclk_o;
+ wire clk25;
- dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
- .CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
- .RESET(o_reset), .LOCKED(o_locked));
-
- // lock it to the input path
- BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
- // assign o_fbk_in = bclk_o;
-// BUFG bclk_io_fbk(.I(bclk_io), .O(io_fbk_in));
-
- assign i_fbk_in = bclk_i;
+`ifdef UNDEFINED
+ ////////////
+ // This code section is specific to the GPBB
+ //
+ // The rest of the code is generic to creating EIM/I2C interfaces in the FPGA
+ ////////////
+ wire [7:0] cpu_to_dutA; // this set of wires connected to EIM registers below
+ wire [7:0] cpu_to_dutB;
+ wire drive_dutA_N;
+ wire drive_dutB_N;
+ wire [7:0] dut_to_cpu;
+ wire [15:0] gpbb_ctl;
+ wire [15:0] gpbb_stat;
+
+ /// the following is a set of board/pin-name to logical mappings
+ // CPU->DUT mappings bank A
+ assign F_LVDS_P15 = cpu_to_dutA[0];
+ assign F_LVDS_N15 = cpu_to_dutA[1];
+ assign F_LVDS_P0 = cpu_to_dutA[2];
+ assign F_LVDS_N0 = cpu_to_dutA[3];
+ assign F_LVDS_CK1_P = cpu_to_dutA[4];
+ assign F_LVDS_CK1_N = cpu_to_dutA[5];
+ assign F_DX14 = cpu_to_dutA[6];
+ assign F_LVDS_P4 = cpu_to_dutA[7];
+ // CPU->DUT mappings bank B
+ assign F_LVDS_P11 = cpu_to_dutB[0]; // LED 0
+ assign F_LVDS_N11 = cpu_to_dutB[1]; // LED 1
+ assign F_DX1 = cpu_to_dutB[2]; // LED 2
+ assign F_LVDS_NC = cpu_to_dutB[3]; // LED 3
+ assign F_LVDS_PC = cpu_to_dutB[4];
+ assign F_DX17 = cpu_to_dutB[5];
+ assign F_LVDS_NB = cpu_to_dutB[6];
+ assign F_LVDS_PB = cpu_to_dutB[7];
+
+ assign F_LVDS_P7 = drive_dutA_N; // OE_N control for CPU->DUT mappings
+ assign F_LVDS_N7 = drive_dutB_N; // OE_N control for CPU->DUT mappings
+
+ assign drive_dutA_N = !gpbb_ctl[0]; // invert so drive is true from programming model
+ assign drive_dutB_N = !gpbb_ctl[1]; // invert so drive is true from programming model
+
+ assign F_DX15 = !gpbb_ctl[15]; // bit 15 selects output voltage
+ // invert so from software, default 0 = low voltage; 1 = drive 5V
+
+ // DUT->CPU mappings
+ assign dut_to_cpu[0] = F_DX18;
+ assign dut_to_cpu[1] = F_LVDS_CK0_N;
+ assign dut_to_cpu[2] = F_LVDS_CK0_P;
+ assign dut_to_cpu[3] = F_LVDS_P9;
+ assign dut_to_cpu[4] = F_DX0;
+ assign dut_to_cpu[5] = F_DX3;
+ assign dut_to_cpu[6] = F_DX2;
+ assign dut_to_cpu[7] = F_DX11;
+
+
+ assign gpbb_stat[15:0] = {15'b0, F_LVDS_NA}; // tie unused lines to 0
+ // bit 0 is overcurrent flag
+
+ /////////////
+ // right, so fwiw, we map the ADC to the I2C bus.
+ // you can also map this to EIM by making registers that
+ // map to ADC wires, but this is an instructive example of
+ // how to use I2C-to-FPGA mappings with something reasonably generic.
+ // the I2C interface block is called i2c_slave and is near the bottom of this file
+
+ /// ADC
+ wire adc_go;
+ wire [2:0] adc_chan;
+
+ wire [9:0] adc_in;
+ wire adc_valid;
+ wire slowclk;
+
+ adc10cs022 adc10cs022 (
+ .DIG_ADC_CS(F_DX13),
+ .DIG_ADC_IN(F_DX6),
+ .DIG_ADC_OUT(F_DX12),
+ .DIG_ADC_SCLK(F_DX7),
+
+ .adc_in(adc_in),
+ .adc_chan(adc_chan),
+ .adc_valid(adc_valid),
+ .adc_go(adc_go),
+
+ .clk_3p2MHz(slowclk),
+ .reset(reset)
+ );
+`endif // UNDEFINED
+
+ //////////////////////////////
+ ///// The following code is used to create the EIM interface to the CPU
+ /////
+ ///// Copy-and-paste the memory-mapped register templates to make
+ ///// more control registers. If you're working on your own design,
+ ///// I recommend you start with all the code below this area as a baseline.
+ /////
+ ///// It's tricky to change code that relates to
+ ///// the details of talking to the i.MX6 EIM -- it's difficult to
+ ///// close timing, so you'll need to understand a bit about FPGA timing
+ ///// closure to make chages to that section
+ //////////////////////////////
////////////////////////////////////
- ///// Register set -- area-inefficient, high fan-out/in registers for controlling/monitoring internal signals
+ ///// EIM Register set
+ /////
///// All registers split into write or read only blanks
- ///// 0x40000 - 0x40FFF is reserved for w/o
- ///// 0x41000 - 0x41FFF is reserved for r/o
- ///// -> if you want to check a w/o value, loop it back to an r/o register
+ /////
+ ///// bank 0 maps to CS0 in EIM space, and the CPU timings should
+ ///// be configured for "word mode" (e.g. 16-bit accesses) only
+ ///// This address space has the fundamental C type of (unsigned short *)
+ ///// 0x40000 - 0x40FFF is reserved for write-only bank 0
+ ///// 0x41000 - 0x41FFF is reserved for read-only bank 0
+ /////
+ ///// bank 1 maps to CS1 in EIM space. The CPU timings should be
+ ///// configured for "burst mode". Accessing this space is most
+ ///// efficient using memcpy() with a block size of 8 bytes, as all
+ ///// registers in this space are 64-bit values. You can also try
+ ///// using a fundamental C type of (unsigned long long *)
+ /////
+ ///// 0xC040000 - 0xC040FFF is reserved for w/o bank 1
+ ///// 0xC041000 - 0xC041FFF is reserved for r/o bank 1
////////////////////////////////////
+ ////////// VERSION LOG (major version 000B) /////////////
+ ////// by convention, I reserve 0x41FFC and 0x41FFE for
+ ////// minor and major version codes, respectively
+ ////// I try to give every FPGA design type a unique version
+ ////// code, and keep track of the rev of the design with the
+ ////// minor code.
+ //////
+ ////// This particular design gets Major version 0xB.
+ //////
+ // Minor version 0001, October 19 2014
+ // Initial design to validate GPBB
+ //
+
reg cs0_r, rw_r;
reg [15:0] din_r;
reg [18:0] bus_addr_r;
@@ -176,7 +241,8 @@ module novena_fpga(
reg cs0_in, rw_in, adv_in;
reg [15:0] din_in;
reg [2:0] a_in;
-
+
+ /// pipeline the inputs to allow for s/h closure
always @(posedge bclk_i) begin
cs0_in <= EIM_CS[0];
rw_in <= EIM_RW;
@@ -198,41 +264,57 @@ module novena_fpga(
end
end
- wire [15:0] r40000wo;
- wire [15:0] r40002wo;
+ /// retime and mux between cs0 and cs1 banks on the output
+`ifdef UNDEFINED
+ wire [15:0] ro_d_b;
+ reg [15:0] ro_d_b_r;
+ always @(posedge bclk_i) begin
+ ro_d_b_r[15:0] <= ro_d_b[15:0];
+ end
+`endif
+ reg [15:0] ro_d_r;
+ reg [1:0] eim_rdcs;
+ reg [15:0] eim_dout_pipe;
+ reg [15:0] eim_dout_pipe2;
+
+ always @(posedge bclk_dll) begin
+ ro_d_r <= ro_d;
+ eim_rdcs[1:0] <= EIM_CS[1:0];
+`ifdef UNDEFINED
+ eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
+`else
+ eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : 16'b0;
+`endif
+ end
+ always @(posedge bclk_o) begin
+ eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
+ end;
+
wire [15:0] ro_d;
+`ifdef UNDEFINED
+ wire [15:0] r40000wo;
+ wire [15:0] r40002wo;
+
//////// write-only registers
reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( r40000wo[15:0] ) );
reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
- .bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable
+ .bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable for testing
.reg_d( r40002wo[15:0] ) );
- wire [15:0] romulator_ctl;
- wire emulate;
- wire spi_uk_rd_en;
- wire spi_uk_rst;
- wire spi_out_rd_en;
- wire spi_out_rst;
- wire spi_adr_rd_en;
- wire spi_adr_rst;
- assign emulate = romulator_ctl[0]; // 1
- assign spi_uk_rd_en = romulator_ctl[1]; // 2
- assign spi_uk_rst = romulator_ctl[2]; // 4
- assign spi_adr_rd_en = romulator_ctl[3]; // 8
- assign spi_adr_rst = romulator_ctl[4]; // 10
- assign spi_out_rd_en = romulator_ctl[5]; // 20
- assign spi_out_rst = romulator_ctl[6]; // 40
-
- reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
- .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r),
- .rbk_d(ro_d), .reg_d( romulator_ctl[15:0] ) );
+ reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
+ .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
+ .reg_d( {cpu_to_dutB[7:0], cpu_to_dutA[7:0]} ) );
+ reg_wo reg_wo_40012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40012),
+ .bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
+ .reg_d( gpbb_ctl[15:0] ) );
+
//////// read-only registers
// loopback readback
reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
@@ -243,54 +325,21 @@ module novena_fpga(
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40002wo[15:0] ) );
-
- wire [15:0] romulator_stat;
- reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_stat[15:0] ) );
-
- wire [15:0] romulator_count;
- reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_count[15:0] ) );
-
- wire [15:0] romulator_adr_stat;
- reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_stat[15:0] ) );
-
- wire [15:0] romulator_adr_count;
- reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),
+ reg_ro reg_ro_41010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41010),
.bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_count[15:0] ) );
+ .reg_d( {8'b0,dut_to_cpu[7:0]} ) );
- wire [23:0] romulator_adr_dout;
- reg_ro reg_ro_41108 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41108),
+ reg_ro reg_ro_41012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41012),
.bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_adr_dout[15:0] ) );
+ .reg_d( gpbb_stat[15:0] ) );
- reg_ro reg_ro_4110A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110A),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( {8'b0,romulator_adr_dout[23:16]} ) );
-
- wire [15:0] romulator_out_stat;
- reg_ro reg_ro_4110C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_out_stat[15:0] ) );
-
- wire [15:0] romulator_out_count;
- reg_ro reg_ro_4110E ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110E),
- .bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( romulator_out_count[15:0] ) );
///////////////////////
- ///////////////////////
// CS1 bank registers: minimum size here is 64-bit, tuned for synchronous burst access only
///////////////////////
wire [63:0] rC04_0000wo;
wire [63:0] rC04_0008wo;
- wire [15:0] ro_d_b;
///////// write registers
// loopback test
@@ -320,260 +369,118 @@ module novena_fpga(
// FPGA major version code
reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
.bus_d(ro_d), .re(!cs0_r && rw_r),
- .reg_d( 16'h000A ) ); // 000A is for the SPI romulator
+ .reg_d( 16'h000B ) ); // 000B is for GPBB release
- ////////// VERSION LOG (major version 000A) /////////////
- //////
- // Minor version 0001, May 13 2014
- // Initial cull to the SPI ROM feature set
- //
+ ////////////////////////////////////
+ ///// I2C register set -- for those who don't want to use EIM
+ ////////////////////////////////////
+ wire [7:0] reg_0_test;
+ wire SDA_pd;
+ wire SDA_int;
+
+ IOBUF #(.DRIVE(8), .SLEW("SLOW")) IOBUF_sda (.IO(I2C3_SDA), .I(1'b0), .T(!SDA_pd), .O(SDA_int));
+ i2c_slave i2c_slave(
+ .SCL(I2C3_SCL),
+ .SDA(SDA_int),
+ .SDA_pd(SDA_pd),
+ .clk(clk25), // nominally 26 MHz, this is close enough
+ .glbl_reset(reset),
+ .i2c_device_addr(8'h3C),
+
+ // outputs from I2C block (CPU->FPGA) 0-3F
+ .reg_0(reg_0_test),
+
+ .reg_2({adc_go,adc_chan[2:0]}),
+ // bit 2-0: ADC channel
+ // bit 3: initiate conversion
+
+ // inputs to I2C block (FPGA->CPU) 40-7F
+ .reg_40(adc_in[7:0]),
+ .reg_41({6'b0,adc_in[9:8]}),
+
+ .reg_42({7'b0, adc_valid}),
+
+ // ID / version code
+ // minor / major
+ .reg_fc(8'h00), .reg_fd(8'h01), .reg_fe(8'h00), .reg_ff(8'h0B)
+ );
+`endif // UNDEFINED
+
+ ////////////////////////////////////
+ ///// MASTER RESET
+ ////////////////////////////////////
+ // synced to a 3.2MHz clock
+ sync_reset dll_res_sync( .glbl_reset(!RESETBMCU), .clk(slowclk), .reset(reset) );
- // mux between block memory and register set based on high bits
- // assign eim_dout = (bus_addr[18:16] != 3'b000) ? ro_d : bram_dout;
- // pipeline to improve timing
- reg [15:0] ro_d_r;
- reg [15:0] ro_d_b_r;
- reg [1:0] eim_rdcs;
- reg [15:0] eim_dout_pipe;
- reg [15:0] eim_dout_pipe2;
- always @(posedge bclk_i) begin
- ro_d_b_r <= ro_d_b;
- end
+ ////////////////////////////////////
+ ///// BCLK DLL -- generate zero-delay clock plus slower versions for internal use
+ ////////////////////////////////////
+ wire bclk_int_in, bclk_io_in;
+ IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
+ BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
- always @(posedge bclk_dll) begin
- ro_d_r <= ro_d;
- eim_rdcs[1:0] <= EIM_CS[1:0];
- eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
- end
-
- always @(posedge bclk_o) begin
- eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
- end;
-
- wire [15:0] spi_eeprom_rbk;
- wire [7:0] spi_uk_cmd;
- wire spi_uk_cmd_updated;
+ bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
+ .RESET(reset), .LOCKED(bclk_locked));
- wire spiclk_i;
- wire spiclk;
+ wire o_reset, o_locked;
+ wire i_fbk_out, i_fbk_in;
+ wire o_fbk_out, o_fbk_in;
- IBUFG spi_clkibufg( .I(F_LVDS_CK_P0), .O(spiclk_i));
- BUFG spi_clkbufg( .I(spiclk_i), .O(spiclk) );
-
- wire [23:0] spi_adr;
- wire spi_adr_updated;
+ dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
+ .CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
+ .RESET(reset), .LOCKED(i_locked));
- wire [7:0] spi_byte;
- wire spi_byte_updated;
+ dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
+ .CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
+ .RESET(reset), .LOCKED(o_locked));
- wire [7:0] spi_obyte;
- wire spi_obyte_updated;
+ // lock it to the input path
+ BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in)); // was this
+// assign o_fbk_in = bclk_o;
+// BUFG bclk_io_fbk(.I(bclk_io), .O(io_fbk_in));
- spi_eeprom spi_eeprom(
- .sdout(F_LVDS_P11),
- .sdin(F_LVDS_CK_N0),
- .scs(F_DX18),
- .sclk(spiclk),
- .swp(1'b1),
- .shold(1'b1),
-
- .eim_clk(bclk_i),
- .bus_a(bus_addr_r),
- .bus_d(din_r),
- .we(!cs0_r && !rw_r),
- .re(!cs0_r && rw_r),
- .reg_d(spi_eeprom_rbk),
- .rbk_d(ro_d),
-
- .spi_uk_cmd(spi_uk_cmd), // bitbucket for unknown commands
- .spi_uk_cmd_updated(spi_uk_cmd_updated),
-
- .spi_byte(spi_byte),
- .spi_byte_updated(spi_byte_updated),
-
- .spi_obyte(spi_obyte),
- .spi_obyte_updated(spi_obyte_updated),
-
- .spi_adr(spi_adr),
- .spi_adr_updated(spi_adr_updated),
-
- .reset(reset)
- );
-
- wire [11:0] spi_uk_rd_data_count;
- wire spi_uk_empty;
- wire spi_uk_overflow;
- wire spi_uk_full;
- wire [7:0] spi_uk_dout;
- wire spi_uk_rd_en_pulse;
-
- rising_edge spi_re( .clk(bclk_dll),
- .level(spi_uk_rd_en),
- .pulse(spi_uk_rd_en_pulse)
- );
+ assign i_fbk_in = bclk_i;
- assign romulator_stat[7:0] = spi_uk_dout[7:0];
- assign romulator_stat[8] = spi_uk_empty;
- assign romulator_stat[9] = spi_uk_full;
- assign romulator_stat[10] = spi_uk_overflow;
- assign romulator_count[11:0] = spi_uk_rd_data_count[11:0];
-
- uk_fifo spi_uk (
- .rst(spi_uk_rst), // input rst
-// .wr_clk(spiclk), // input wr_clk
- .wr_clk(!spiclk), // input wr_clk // invert for monitoring
-
-// .din(spi_uk_cmd), // input [7 : 0] din
-// .wr_en(spi_uk_cmd_updated), // input wr_en
- .din(spi_byte),
- .wr_en(spi_byte_updated),
-
- .rd_clk(bclk_dll), // input rd_clk
- .rd_en(spi_uk_rd_en_pulse), // input rd_en
- .dout(spi_uk_dout), // output [7 : 0] dout
- .full(spi_uk_full), // output full
- .overflow(spi_uk_overflow), // output overflow
- .empty(spi_uk_empty), // output empty
- .rd_data_count(spi_uk_rd_data_count) // output [11 : 0] rd_data_count
- );
-
- wire [11:0] spi_out_rd_data_count;
- wire spi_out_empty;
- wire spi_out_overflow;
- wire spi_out_full;
- wire [7:0] spi_out_dout;
- wire spi_out_rd_en_pulse;
-
- rising_edge spi_out_re( .clk(bclk_dll),
- .level(spi_out_rd_en),
- .pulse(spi_out_rd_en_pulse)
- );
-
- assign romulator_out_stat[7:0] = spi_out_dout[7:0];
- assign romulator_out_stat[8] = spi_out_empty;
- assign romulator_out_stat[9] = spi_out_full;
- assign romulator_out_stat[10] = spi_out_overflow;
- assign romulator_out_count[11:0] = spi_out_rd_data_count[11:0];
-
- uk_fifo spi_out (
- .rst(spi_out_rst), // input rst
- .wr_clk(!spiclk), // input wr_clk
- // invert from negedge sampling of sdout
-
- .din(spi_obyte),
- .wr_en(spi_obyte_updated),
-
- .rd_clk(bclk_dll), // input rd_clk
- .rd_en(spi_out_rd_en_pulse), // input rd_en
- .dout(spi_out_dout), // output [7 : 0] dout
- .full(spi_out_full), // output full
- .overflow(spi_out_overflow), // output overflow
- .empty(spi_out_empty), // output empty
- .rd_data_count(spi_out_rd_data_count) // output [11 : 0] rd_data_count
- );
-
- wire spi_adr_rd_en_pulse;
- wire [23:0] spi_adr_dout;
- wire spi_adr_full;
- wire spi_adr_overflow;
- wire spi_adr_empty;
- wire [13:0] spi_adr_rd_data_count;
- assign romulator_adr_count[13:0] = spi_adr_rd_data_count[13:0];
- assign romulator_adr_stat[8] = spi_adr_empty;
- assign romulator_adr_stat[9] = spi_adr_full;
- assign romulator_adr_stat[10] = spi_adr_overflow;
-
- assign romulator_adr_dout[23:0] = spi_adr_dout[23:0];
-
- rising_edge spi_adr_re( .clk(bclk_dll),
- .level(spi_adr_rd_en),
- .pulse(spi_adr_rd_en_pulse)
- );
- nandadr_fifo spi_adr_fifo (
- .rst(spi_adr_rst), // input rst
- .wr_clk(spiclk), // input wr_clk
- .rd_clk(bclk_dll), // input rd_clk
- .din({6'b0,spi_adr[23:0]}), // input [29 : 0] din
- .wr_en(spi_adr_updated), // input wr_en
- .rd_en(spi_adr_rd_en_pulse), // input rd_en
- .dout(spi_adr_dout[23:0]), // output [29 : 0] dout
- .full(spi_adr_full), // output full
- .overflow(spi_adr_overflow), // output overflow
- .empty(spi_adr_empty), // output empty
- .rd_data_count(spi_adr_rd_data_count) // output [13 : 0] rd_data_count
- );
+ ////////////////////////////////////
+ ///// create 3.2MHz, 25MHz, and 50MHz buffered clocks from clk using DLL
+ ////////////////////////////////////
+ wire dll_locked;
+
+ clk_dll clk_dll
+ (// Clock in ports
+ .clk50in(clk), // IN
+ // Clock out ports
+ .clk50(clk50), // OUT
+ .clk25(clk25), // OUT
+ .clk3p2(slowclk), // OUT
+ // Status and control signals
+ .RESET(!RESETBMCU),// IN
+ .LOCKED(dll_locked)); // OUT
+
//////////////
// Output pipeline registers -- explicit instantiation as their LOCs are controlled in the UCF.
//////////////
- FDSE oddr2_eim0( .D( eim_dout_pipe2[0] ),
- .C( bclk_o ),
- .Q( eim_dout[0] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim1( .D( eim_dout_pipe2[1] ),
- .C( bclk_o ),
- .Q( eim_dout[1] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim2( .D( eim_dout_pipe2[2] ),
- .C( bclk_o ),
- .Q( eim_dout[2] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim3( .D( eim_dout_pipe2[3] ),
- .C( bclk_o ),
- .Q( eim_dout[3] ),
- .CE( 1'b1 ), .S(1'b0) );
-
- FDSE oddr2_eim4( .D( eim_dout_pipe2[4] ),
- .C( bclk_o ),
- .Q( eim_dout[4] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim5( .D( eim_dout_pipe2[5] ),
- .C( bclk_o ),
- .Q( eim_dout[5] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim6( .D( eim_dout_pipe2[6] ),
- .C( bclk_o ),
- .Q( eim_dout[6] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim7( .D( eim_dout_pipe2[7] ),
- .C( bclk_o ),
- .Q( eim_dout[7] ),
- .CE( 1'b1 ), .S(1'b0) );
-
- FDSE oddr2_eim8( .D( eim_dout_pipe2[8] ),
- .C( bclk_o ),
- .Q( eim_dout[8] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eim9( .D( eim_dout_pipe2[9] ),
- .C( bclk_o ),
- .Q( eim_dout[9] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimA( .D( eim_dout_pipe2[10] ),
- .C( bclk_o ),
- .Q( eim_dout[10] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimB( .D( eim_dout_pipe2[11] ),
- .C( bclk_o ),
- .Q( eim_dout[11] ),
- .CE( 1'b1 ), .S(1'b0) );
-
- FDSE oddr2_eimC( .D( eim_dout_pipe2[12] ),
- .C( bclk_o ),
- .Q( eim_dout[12] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimD( .D( eim_dout_pipe2[13] ),
- .C( bclk_o ),
- .Q( eim_dout[13] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimE( .D( eim_dout_pipe2[14] ),
- .C( bclk_o ),
- .Q( eim_dout[14] ),
- .CE( 1'b1 ), .S(1'b0) );
- FDSE oddr2_eimF( .D( eim_dout_pipe2[15] ),
- .C( bclk_o ),
- .Q( eim_dout[15] ),
- .CE( 1'b1 ), .S(1'b0) );
+ FDSE oddr2_eim0(.D(eim_dout_pipe2[ 0]), .C(bclk_o), .Q(eim_dout[ 0]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim1(.D(eim_dout_pipe2[ 1]), .C(bclk_o), .Q(eim_dout[ 1]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim2(.D(eim_dout_pipe2[ 2]), .C(bclk_o), .Q(eim_dout[ 2]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim3(.D(eim_dout_pipe2[ 3]), .C(bclk_o), .Q(eim_dout[ 3]), .CE(1'b1), .S(1'b0));
+
+ FDSE oddr2_eim4(.D(eim_dout_pipe2[ 4]), .C(bclk_o), .Q(eim_dout[ 4]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim5(.D(eim_dout_pipe2[ 5]), .C(bclk_o), .Q(eim_dout[ 5]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim6(.D(eim_dout_pipe2[ 6]), .C(bclk_o), .Q(eim_dout[ 6]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim7(.D(eim_dout_pipe2[ 7]), .C(bclk_o), .Q(eim_dout[ 7]), .CE(1'b1), .S(1'b0));
+
+ FDSE oddr2_eim8(.D(eim_dout_pipe2[ 8]), .C(bclk_o), .Q(eim_dout[ 8]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eim9(.D(eim_dout_pipe2[ 9]), .C(bclk_o), .Q(eim_dout[ 9]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eimA(.D(eim_dout_pipe2[10]), .C(bclk_o), .Q(eim_dout[10]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eimB(.D(eim_dout_pipe2[11]), .C(bclk_o), .Q(eim_dout[11]), .CE(1'b1), .S(1'b0));
+
+ FDSE oddr2_eimC(.D(eim_dout_pipe2[12]), .C(bclk_o), .Q(eim_dout[12]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eimD(.D(eim_dout_pipe2[13]), .C(bclk_o), .Q(eim_dout[13]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eimE(.D(eim_dout_pipe2[14]), .C(bclk_o), .Q(eim_dout[14]), .CE(1'b1), .S(1'b0));
+ FDSE oddr2_eimF(.D(eim_dout_pipe2[15]), .C(bclk_o), .Q(eim_dout[15]), .CE(1'b1), .S(1'b0));
//////////////
@@ -598,7 +505,7 @@ module novena_fpga(
eim_lba_reg <= EIM_LBA;
eim_oe_reg <= EIM_OE;
end
-
+
always @(posedge bclk_o) begin
eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
@@ -618,42 +525,43 @@ module novena_fpga(
eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
end
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
- IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
-
- //////////////
- // DDR3 interface macro
- //////////////
-
- wire c1_clk0, c1_rst0;
-
- ddr3_clkgen ddr3_clkgen (
- .clk50in(clk),
- .clk50(clk50),
- .clk400(ddr3clk),
- .clk100(clk100),
- .RESET(reset),
- .LOCKED(ddr3_dll_locked)
- );
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t[ 0]), .O(eim_din[ 0]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t[ 1]), .O(eim_din[ 1]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t[ 2]), .O(eim_din[ 2]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t[ 3]), .O(eim_din[ 3]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t[ 4]), .O(eim_din[ 4]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t[ 5]), .O(eim_din[ 5]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t[ 6]), .O(eim_din[ 6]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t[ 7]), .O(eim_din[ 7]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t[ 8]), .O(eim_din[ 8]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t[ 9]), .O(eim_din[ 9]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t[10]), .O(eim_din[10]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t[11]), .O(eim_din[11]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t[12]), .O(eim_din[12]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t[13]), .O(eim_din[13]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t[14]), .O(eim_din[14]));
+ IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t[15]), .O(eim_din[15]));
//////////////
// tie downs (unused signals as of this rev of design)
//////////////
assign APOPTOSIS = 1'b0; // make apoptosis inactive, tigh high to force reboot on config
- assign ECSPI3_MISO = 1'b0;
+ //////////////
+ // coretest hash cores
+ //////////////
+ coretest_hashes core(
+ //.clk(bclk_dll),
+ //.clk(clk50),
+ .clk(clk25),
+ .reset_n(1'b1),
+
+ .cs(!cs0_r && !adv_r),
+ .we(!rw_r),
+
+ .address(bus_addr_r),
+ .write_data(din_r),
+ .read_data(ro_d)
+ );
+
endmodule
diff --git a/src/rtl/romulator_ddr3_tb.v b/src/rtl/romulator_ddr3_tb.v
deleted file mode 100755
index 2ac7ecc..0000000
--- a/src/rtl/romulator_ddr3_tb.v
+++ /dev/null
@@ -1,802 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 2013, Andrew "bunnie" Huang
-//
-// See the NOTICE file distributed with this work for additional
-// information regarding copyright ownership. The copyright holder
-// licenses this file to you under the Apache License, Version 2.0
-// (the "License"); you may not use this file except in compliance
-// with the License. You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing,
-// code distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations
-// under the License.
-//////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-module romulator_ddr3_tb;
- reg clk;
-
- reg nand_we;
- reg nand_re;
- reg nand_ale;
- reg nand_cle;
- wire nand_rb;
- reg nand_wp;
- reg nand_cs;
-
- reg [7:0] nand_din;
- wire [7:0] nand_dout;
- wire nand_drive_out;
-
- wire [15:0] ram_adr;
- wire [7:0] ram_d_to_ram;
- wire [7:0] ram_d_from_ram;
- wire ram_we;
- wire ram_clk_to_ram;
-
- wire [7:0] nand_uk_cmd; // pipe to a FIFO to store unknown commands
- wire nand_uk_cmd_updated;
-
- reg reset;
-
- reg rom_ddr3_reset; // reset just the ddr3-romulator interface
-
- wire ddr3_wr_clk;
- wire ddr3_wr_cmd_en;
- wire [2:0] ddr3_wr_cmd_instr;
- wire [5:0] ddr3_wr_cmd_bl;
- wire [29:0] ddr3_wr_adr;
- reg ddr3_wr_cmd_full;
- wire ddr3_wr_cmd_empty;
-
- wire ddr3_wr_dat_en;
- wire [31:0] ddr3_wr_dat;
- reg ddr3_wr_full;
- reg ddr3_wr_empty;
-
- wire ddr3_rd_clk;
- wire ddr3_rd_cmd_en;
- wire [2:0] ddr3_rd_cmd_instr;
- wire [5:0] ddr3_rd_cmd_bl;
- wire [29:0] ddr3_rd_adr;
- reg ddr3_rd_cmd_full;
- wire ddr3_rd_dat_en;
- reg [31:0] ddr3_rd_dat;
- reg ddr3_rd_dat_empty;
- reg ddr3_rd_dat_full;
- reg ddr3_rd_dat_overflow; // need to monitor this
-
- wire page_addra_over;
- wire outstanding_under;
-
- glbl glbl(); // add global reset capabiilities
-
- romulator_ddr3 dut (
- .clk(clk),
- .nand_we( nand_we),
- .nand_re( nand_re),
- .nand_ale( nand_ale),
- .nand_cle( nand_cle),
- .nand_rb( nand_rb),
- .nand_wp( nand_wp),
- .nand_cs( nand_cs),
-
- .nand_din(nand_din),
- .nand_dout(nand_dout),
- .nand_drive_out(nand_drive_out),
-
- .rom_ddr3_reset(rom_ddr3_reset),
-
- .ddr3_wr_clk(ddr3_wr_clk),
- .ddr3_wr_cmd_en(ddr3_wr_cmd_en),
- .ddr3_wr_cmd_instr(ddr3_wr_cmd_instr[2:0]),
- .ddr3_wr_cmd_bl(ddr3_wr_cmd_bl[5:0]),
- .ddr3_wr_adr(ddr3_wr_adr[29:0]),
- .ddr3_wr_cmd_full(ddr3_wr_cmd_full),
- .ddr3_wr_cmd_empty(ddr3_wr_cmd_empty),
- .ddr3_wr_dat_en(ddr3_wr_dat_en),
- .ddr3_wr_dat(ddr3_wr_dat[31:0]),
- .ddr3_wr_full(ddr3_wr_full),
- .ddr3_wr_empty(ddr3_wr_empty),
-
- .ddr3_rd_clk(ddr3_rd_clk),
- .ddr3_rd_cmd_en(ddr3_rd_cmd_en),
- .ddr3_rd_cmd_instr(ddr3_rd_cmd_instr[2:0]),
- .ddr3_rd_cmd_bl(ddr3_rd_cmd_bl[5:0]),
- .ddr3_rd_adr(ddr3_rd_adr[29:0]),
- .ddr3_rd_cmd_full(ddr3_rd_cmd_full),
- .ddr3_rd_dat_en(ddr3_rd_dat_en),
- .ddr3_rd_dat(ddr3_rd_dat[31:0]),
- .ddr3_rd_dat_empty(ddr3_rd_dat_empty),
- .ddr3_rd_dat_count(data_count[6:0]),
- .ddr3_rd_dat_full(ddr3_rd_dat_full),
- .ddr3_rd_dat_overflow(ddr3_rd_dat_overflow),
-
- .page_addra_over(page_addra_over),
- .outstanding_under(outstanding_under),
-
- .nand_uk_cmd(nand_uk_cmd),
- .nand_uk_cmd_updated(nand_uk_cmd_updated),
-
- .reset(reset)
- );
-
- // emulate a very simple DDR3-MIG moderated memory interface here
- reg [1:0] cmd_count;
- reg [7:0] data_count;
- reg [7:0] wdata_count;
- reg [31:0] latency_timer;
- reg [31:0] wlatency_timer;
- reg add_data;
- reg minus_data;
- reg ddr3_go;
- reg ddr3_wgo;
- reg [1:0] wcmd_count;
-
- parameter DDR3_TURNAROUND_TIME = 32'h20;
-
- assign ddr3_wr_cmd_empty = (wcmd_count == 2'b00);
-
- // we're going to cheat and use blocking assignments.
- always @(posedge clk) begin
- if( ddr3_rd_cmd_en ) begin
- if( cmd_count == 2'b11 ) begin
- cmd_count = cmd_count;
- end else begin
- cmd_count = cmd_count + 1;
- end
- end else begin
- cmd_count = cmd_count;
- end
-
- if( ddr3_wr_cmd_en ) begin
- if( wcmd_count == 2'b11 ) begin
- wcmd_count = wcmd_count;
- end else begin
- wcmd_count = wcmd_count + 1;
- end
- end else begin
- wcmd_count = wcmd_count;
- end
-
- if( cmd_count == 2'b11 ) begin
- ddr3_rd_cmd_full = 1'b1;
- end else begin
- ddr3_rd_cmd_full = 1'b0;
- end
-
- if( wcmd_count == 2'b11 || (wcmd_count == 2'b10 && ddr3_wr_cmd_en)) begin
- ddr3_wr_cmd_full = 1'b1;
- end else begin
- ddr3_wr_cmd_full = 1'b0;
- end
-
- if( cmd_count > 2'b00 ) begin
- ddr3_go = 1;
- end else begin
- ddr3_go = 0;
- end
-
- if( wcmd_count > 2'b00 ) begin
- ddr3_wgo = 1;
- end else begin
- ddr3_wgo = 0;
- end
-
- if( ddr3_wr_dat_en ) begin
- wdata_count <= wdata_count + 1;
- end
-
- if( wdata_count > 0 ) begin
- ddr3_wr_empty <= 1'b0;
- end else begin
- ddr3_wr_empty <= 1'b1;
- end
-
- if( ddr3_wgo ) begin
- wlatency_timer = wlatency_timer + 1;
- if( wdata_count != 8'b0 ) begin
- wdata_count <= wdata_count - 1;
- end
- end
-
- if( wlatency_timer >= 32'd16 ) begin
- wlatency_timer <= 32'd0;
- wcmd_count <= wcmd_count - 2'b1;
- end
-
- if( wdata_count >= 8'd64 ) begin
- ddr3_wr_full <= 1'b1;
- end else begin
- ddr3_wr_full <= 1'b0;
- end
-
- if( ddr3_go && !add_data ) begin
- latency_timer = latency_timer + 1;
- end else if (add_data || !ddr3_go) begin
- latency_timer = 0;
- end else begin
- latency_timer = latency_timer;
- end
-
- if( latency_timer > DDR3_TURNAROUND_TIME ) begin
- add_data = 1;
- cmd_count = cmd_count - 1;
- latency_timer = 0;
- end else begin
- add_data = 0;
- end
-
- if( add_data ) begin
- if( data_count < 8'd64 ) begin
- data_count = data_count + 8'd16; // we get 16 words at a time
- ddr3_rd_dat_full = 1'b0;
- end else if (data_count == 8'd64) begin
- ddr3_rd_dat_overflow = 1'b0;
- ddr3_rd_dat_full = 1'b1;
- data_count = data_count;
- end else begin
- ddr3_rd_dat_overflow = 1'b1;
- ddr3_rd_dat_full = 1'b1;
- data_count = data_count;
- end
- end else begin
- // need a delete data entry here too
- data_count = data_count;
- end // else: !if( add_data )
-
-
- if( ddr3_rd_dat_en ) begin
- if( data_count > 8'd0 ) begin
- ddr3_rd_dat = ddr3_rd_dat + 32'h01010101;
- data_count = data_count - 1;
- end else begin
- data_count = 0;
- end
- end
-
- if( data_count[6:0] > 7'd0 ) begin
- ddr3_rd_dat_empty = 1'b0;
- end else begin
- ddr3_rd_dat_empty = 1'b1;
- end
-
- end
-
- parameter PERIOD = 16'd8; // 125 MHz (close to 133 MHz actual)
- always begin
- clk = 1'b0;
- #(PERIOD/2) clk = 1'b1;
- #(PERIOD/2);
- end
-
- task nand_idle;
- begin
- nand_we = 1'b1;
- nand_re = 1'b1;
- nand_ale = 1'b0;
- nand_cle = 1'b0;
- nand_cs = 1'b1;
- nand_din = 8'hZZ;
- end
- endtask // nand_idle
-
- task nand_read_id;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_we = 1'b0;
- nand_din = 8'h90;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_din = 8'hZZ;
- #20;
-
- nand_ale = 1'b1;
- #25;
-
- nand_we = 1'b0;
- nand_din = 8'h00;
- #25;
- nand_we = 1'b1;
- #5;
- nand_din = 8'hZZ;
- #20;
-
- nand_ale = 1'b0;
-
- #10;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
-
- nand_cs = 1'b1;
- end
- endtask; // nand_read_id
-
- task unknown_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h44; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- nand_cs = 1'b1;
- end
- endtask; // unknown_op
-
- task reset_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'hFF; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- nand_cs = 1'b1;
-
- #6000;
- end
- endtask; // reset_op
-
- task status_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h70; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- #100;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #20;
-
- nand_cs = 1'b1;
- end
- endtask; // status_op
-
-
- task nand_read_op;
- input [29:0] adr;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h00;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_ale = 1'b1;
-
- nand_din = adr[7:0];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {4'b0,adr[11:8]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[19:12];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[27:20];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {6'b0,adr[29:28]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b1;
- nand_din = 8'h30;
- nand_ale = 1'b0;
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b0;
-
- while( nand_rb == 1'b0 ) begin
- #50;
- end
-
-// #7000;
- #500;
-
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
-
- nand_cs = 1'b1;
-
- end
- endtask; // nand_read_op
-
- reg [7:0] testdat;
- task nand_write_op;
- input [29:0] adr;
- begin
- testdat = 8'b0;
-
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h80;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_ale = 1'b1;
-
- nand_din = adr[7:0];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {4'b0,adr[11:8]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[19:12];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[27:20];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {6'b0,adr[29:28]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
- nand_ale = 1'b0;
- #25;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_we = 1'b0;
- nand_din = testdat;
- #25;
- nand_we = 1'b1;
- #25;
- testdat = testdat + 8'b10;
-
- nand_cle = 1'b1;
- nand_din = 8'h10;
- nand_ale = 1'b0;
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b0;
-
- while( nand_rb == 1'b0 ) begin
- #50;
- end
-
- nand_cs = 1'b1;
-
- end
- endtask; // nand_write_op
-
-
- task nand_erase_op;
- input [29:0] adr;
- begin
- testdat = 8'b0;
-
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h60;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_ale = 1'b1;
-
- nand_din = adr[19:12];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[27:20];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {6'b0,adr[29:28]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
- nand_ale = 1'b0;
- #25;
-
- nand_cle = 1'b1;
- nand_din = 8'hD0;
- nand_ale = 1'b0;
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b0;
-
- while( nand_rb == 1'b0 ) begin
- #50;
- end
-
- nand_cs = 1'b1;
-
- end
- endtask; // nand_erase_op
-
-
- initial begin
- // emu params
- cmd_count = 0;
- data_count = 0;
- latency_timer = 0;
- add_data = 0;
- ddr3_go = 0;
-
- wcmd_count = 0;
- wdata_count = 0;
- wlatency_timer = 0;
- ddr3_wgo = 0;
-
- // normal params
- nand_wp = 0;
- reset = 0;
- ddr3_wr_cmd_full = 0;
- ddr3_wr_full = 0;
- ddr3_rd_cmd_full = 0;
- ddr3_rd_dat = 32'h04030201;
- ddr3_rd_dat_full = 0;
- ddr3_rd_dat_overflow = 0;
- rom_ddr3_reset = 0;
-
- // reset
- nand_idle();
- #(PERIOD*4);
- reset = 1;
- #(PERIOD*4);
- reset = 0;
- #(PERIOD*4);
- #(PERIOD*4);
- reset = 1;
- #(PERIOD*4);
- reset = 0;
- #(PERIOD*4);
- #100;
-
-
- // now test
- nand_read_id();
- #100;
- nand_read_id();
-
- // postamble
- #50;
- nand_idle();
- #100;
-
- unknown_op();
- #100;
-
- status_op();
- #100;
-
- nand_read_op(29'h0);
- #100;
- // address 20100 -> row/col 40100
- nand_read_op(29'h40100); // maps to 100
- #100;
- // address 80210 -> 100210
- nand_read_op(29'h100210); // maps to 8210
- #100;
- // address 81000 -> 120000
- nand_read_op(29'h120000); // maps to invalid
- #100;
- // address 100000 -> 200000
- nand_read_op(29'h200000); // maps to 9000
- #100;
- // address 120000 -> 240000
- nand_read_op(29'h240000); // maps to invalid
-
- #1000;
-
- nand_write_op(29'h0);
-
- #1000;
-
- nand_write_op(29'h100210);
- #100;
-
- #1000;
-
- nand_read_op(29'h0);
- #100;
- // address 20100 -> row/col 40100
-
- reset_op();
- #100;
-
- nand_erase_op(29'h100210);
- #1000;
-
- nand_read_id();
- #500;
-
- $stop;
- end // initial begin
-
-endmodule // romulator_ddr3_tb
-
diff --git a/src/rtl/romulator_tb.v b/src/rtl/romulator_tb.v
deleted file mode 100755
index 5954580..0000000
--- a/src/rtl/romulator_tb.v
+++ /dev/null
@@ -1,370 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 2013, Andrew "bunnie" Huang
-//
-// See the NOTICE file distributed with this work for additional
-// information regarding copyright ownership. The copyright holder
-// licenses this file to you under the Apache License, Version 2.0
-// (the "License"); you may not use this file except in compliance
-// with the License. You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing,
-// code distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations
-// under the License.
-//////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-module romulator_tb;
- reg clk;
-
- reg nand_we;
- reg nand_re;
- reg nand_ale;
- reg nand_cle;
- wire nand_rb;
- reg nand_wp;
- reg nand_cs;
-
- reg [7:0] nand_din;
- wire [7:0] nand_dout;
- wire nand_drive_out;
-
- wire [15:0] ram_adr;
- wire [7:0] ram_d_to_ram;
- wire [7:0] ram_d_from_ram;
- wire ram_we;
- wire ram_clk_to_ram;
-
- wire [7:0] nand_uk_cmd; // pipe to a FIFO to store unknown commands
- wire nand_uk_cmd_updated;
-
- reg reset;
-
- // a RAM for sim sake
- reg [15:0] extram [7:0];
-
- assign ram_d_from_ram[7:0] = extram[ram_adr];
-
- romulator dut (
- .clk(clk),
- .nand_we( nand_we),
- .nand_re( nand_re),
- .nand_ale( nand_ale),
- .nand_cle( nand_cle),
- .nand_rb( nand_rb),
- .nand_wp( nand_wp),
- .nand_cs( nand_cs),
-
- .nand_din(nand_din),
- .nand_dout(nand_dout),
- .nand_drive_out(nand_drive_out),
-
- .ram_adr(ram_adr),
- .ram_d_to_ram(ram_d_to_ram),
- .ram_d_from_ram(ram_d_from_ram),
- .ram_we(ram_we),
- .ram_clk_to_ram(ram_clk_to_ram),
-
- .nand_uk_cmd(nand_uk_cmd),
- .nand_uk_cmd_updated(nand_uk_cmd_updated),
-
- .reset(reset)
- );
-
-
- parameter PERIOD = 16'd8; // 125 MHz (close to 133 MHz actual)
- always begin
- clk = 1'b0;
- #(PERIOD/2) clk = 1'b1;
- #(PERIOD/2);
- end
-
- task nand_idle;
- begin
- nand_we = 1'b1;
- nand_re = 1'b1;
- nand_ale = 1'b0;
- nand_cle = 1'b0;
- nand_cs = 1'b1;
- nand_din = 8'hZZ;
- end
- endtask // nand_idle
-
- task nand_read_id;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_we = 1'b0;
- nand_din = 8'h90;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_din = 8'hZZ;
- #20;
-
- nand_ale = 1'b1;
- #25;
-
- nand_we = 1'b0;
- nand_din = 8'h00;
- #25;
- nand_we = 1'b1;
- #5;
- nand_din = 8'hZZ;
- #20;
-
- nand_ale = 1'b0;
-
- #10;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
-
- nand_cs = 1'b1;
- end
- endtask; // nand_read_id
-
- task unknown_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h44; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- nand_cs = 1'b1;
- end
- endtask; // unknown_op
-
- task reset_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'hFF; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- nand_cs = 1'b1;
-
- #6000;
- end
- endtask; // reset_op
-
- task status_op;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h70; // some random unknown opcode
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
-
- #100;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #20;
-
- nand_cs = 1'b1;
- end
- endtask; // status_op
-
-
- task nand_read_op;
- input [29:0] adr;
- begin
- nand_cs = 1'b0;
-
- nand_cle = 1'b1;
- nand_ale = 1'b0;
- nand_we = 1'b0;
- nand_din = 8'h00;
- #25;
- nand_we = 1'b1;
- #5;
- nand_cle = 1'b0;
- nand_ale = 1'b1;
-
- nand_din = adr[7:0];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {4'b0,adr[11:8]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[19:12];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = adr[27:20];
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_din = {6'b0,adr[29:28]};
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b1;
- nand_din = 8'h30;
- nand_ale = 1'b0;
- #20;
-
- nand_we = 1'b0;
- #25;
- nand_we = 1'b1;
- #5;
-
- nand_cle = 1'b0;
-
-// #7000;
- #500;
-
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
- nand_re = 1'b0;
- #25;
- nand_re = 1'b1;
- #25;
-
- nand_cs = 1'b1;
-
- end
- endtask; // nand_read_op
-
-
- initial begin
- nand_wp = 0;
- reset = 0;
- $readmemb( "f:\largework\fpga\novena-sd-fpga\extram.bin", extram, 0, 65535 );
-
- $stop;
-
- // reset
- nand_idle();
- #(PERIOD*4);
- reset = 1;
- #(PERIOD*4);
- reset = 0;
- #(PERIOD*4);
- #(PERIOD*4);
- reset = 1;
- #(PERIOD*4);
- reset = 0;
- #(PERIOD*4);
- #100;
-
-
- // now test
- nand_read_id();
- #100;
- nand_read_id();
-
- // postamble
- #50;
- nand_idle();
- #100;
-
- unknown_op();
- #100;
-
- status_op();
- #100;
-
- nand_read_op(29'h0);
- #100;
- // address 20100 -> row/col 40100
- nand_read_op(29'h40100); // maps to 100
- #100;
- // address 80210 -> 100210
- nand_read_op(29'h100210); // maps to 8210
- #100;
- // address 81000 -> 120000
- nand_read_op(29'h120000); // maps to invalid
- #100;
- // address 100000 -> 200000
- nand_read_op(29'h200000); // maps to 9000
- #100;
- // address 120000 -> 240000
- nand_read_op(29'h240000); // maps to invalid
-
- #100;
-
- reset_op();
- #100;
-
- nand_read_id();
- #500;
-
- $stop;
- end // initial begin
-
-endmodule // romulator_tb
diff --git a/src/rtl/spi_eeprom.v b/src/rtl/spi_eeprom.v
deleted file mode 100755
index 5e9f6c4..0000000
--- a/src/rtl/spi_eeprom.v
+++ /dev/null
@@ -1,255 +0,0 @@
-module spi_eeprom(
- output wire sdout,
- input wire sdin,
- input wire scs,
- input wire sclk,
- input wire swp,
- input wire shold,
-
- input wire eim_clk,
- input wire [18:0] bus_a,
- input wire [15:0] bus_d,
- input wire we,
- input wire re,
- output wire [15:0] reg_d,
- output reg [15:0] rbk_d,
-
- output reg [7:0] spi_uk_cmd, // bitbucket for unknown commands
- output reg spi_uk_cmd_updated,
-
- output reg spi_byte_updated, // updates every byte
- output reg [7:0] spi_byte,
- output reg spi_obyte_updated,
- output reg [7:0] spi_obyte,
-
- output wire [23:0] spi_adr,
- output reg spi_adr_updated,
-
- input reset
- );
-
- reg [7:0] inreg;
- reg [31:0] addreg; // top 8 bits are dummy (replica of command)
- reg [23:0] address; // address to read
- reg [15:0] cycle; // cycle counter
- reg [7:0] command;
-
- reg [23:0] shiftout; // ID shift out register
- reg readmode; // 1 if in read mode
- reg [7:0] uk_cmd; // capture unknown commands
- reg uk_cmd_stb; // pulse high once sync to sclk for fifo
-
- wire [31:0] rom_dout;
- reg [31:0] dataout; // shift register for data going out
-
- assign spi_adr = address;
-
- always @(posedge sclk or posedge scs) begin
- if( scs ) begin
- inreg[7:0] <= 8'b0;
- end else begin
- inreg[7:0] <= {inreg[6:0],sdin};
- end
- end
-
- always @(posedge sclk or posedge scs) begin
- if( scs ) begin
- addreg[31:0] <= 32'b0;
- end else begin
- addreg[31:0] <= {addreg[30:0],sdin};
- end
- end
-
- always @(posedge sclk or posedge scs) begin
- if( scs ) begin
- cycle <= 16'b0;
- end else begin
- cycle <= cycle + 16'b1;
- end
- end
-
- always @(posedge sclk) begin
- spi_obyte[7:0] <= {spi_obyte[6:0],sdout};
-
- if( cycle[2:0] == 3'b111 ) begin
- spi_obyte_updated <= 1'b1;
- end else begin
- spi_obyte_updated <= 1'b0;
- end
- end
-
- always @(posedge sclk) begin
- spi_byte[7:0] <= {spi_byte[6:0],sdin};
-
- if( cycle[2:0] == 3'b111 ) begin
- spi_byte_updated <= 1'b1;
- end else begin
- spi_byte_updated <= 1'b0;
- end
- end
-
- always @(negedge sclk) begin
- if( cycle == 16'd9 ) begin
- command <= inreg;
- end else begin
- command <= command;
- end
-
- if( cycle == 16'h20 ) begin
- address[23:0] <= {addreg[23:2],2'b00}; // we're just going to make this bad
- spi_adr_updated <= 1'b1;
- // assumption that all reads are word-aligned
- end else if( (cycle > 16'd40) && (cycle[4:0] == 5'b1_1111) ) begin
- address[23:0] <= address[23:0] + 24'd4;
- spi_adr_updated <= 1'b0;
- end else begin
- address <= address;
- spi_adr_updated <= 1'b0;
- end
- end
-
- `ifdef ORIG_CODE
- always @(negedge sclk) begin
- if( cycle < 16'd8 ) begin // command not valid until 9 but need to know sooner
- shiftout <= shiftout;
- readmode <= 1'b0;
- spi_uk_cmd_updated <= 1'b0;
- spi_uk_cmd <= spi_uk_cmd;
- end else if( cycle == 16'd8 ) begin // do command dispatch
- if( inreg[7:0] == 8'h9f ) begin
- shiftout <= 24'hc86017;
- readmode <= 1'b0;
- spi_uk_cmd_updated <= 1'b1; // grab known for now
- spi_uk_cmd <= inreg[7:0];
- end else if( inreg[7:0] == 8'h0b ) begin
- readmode <= 1'b1;
- shiftout <= shiftout;
- spi_uk_cmd_updated <= 1'b1; // grab known for now
- spi_uk_cmd <= inreg[7:0];
- end else begin
- spi_uk_cmd <= inreg[7:0]; // record the unknown command
- spi_uk_cmd_updated <= 1'b1;
- readmode <= 1'b0;
- shiftout <= shiftout;
- end
- end else begin // cycle > 16'd7
- shiftout[23:0] <= {shiftout[22:0],shiftout[23]};
- readmode <= readmode;
- spi_uk_cmd_updated <= 1'b0;
- spi_uk_cmd <= spi_uk_cmd;
- end
- end // always @ (negedge sclk)
-
- assign sdout = readmode ? dataout[31] : shiftout[23];
-
- always @(negedge sclk) begin
- // 8 cycles for command
- // 24 cycles for address
- // 8 dummy cycles because it's command 0B (only command we support)
- // 40th cycle start shifting the data
- if ( (cycle >= 16'd33) && (cycle[4:0] == 5'b0_1000) ) begin
- dataout[31:0] <= {rom_dout[7:0],rom_dout[15:8],rom_dout[23:16],rom_dout[31:24]};
- end else if( cycle >= 16'd41 ) begin
- dataout[31:0] <= {dataout[30:0],dataout[31]};
- end else begin
- dataout <= dataout;
- end
- end // always @ (negedge sclk)
- `else // !`ifdef ORIG_CODE
- always @(posedge sclk) begin
- if( cycle < 16'd7 ) begin // command not valid until 9 but need to know sooner
- shiftout <= shiftout;
- readmode <= 1'b0;
- spi_uk_cmd_updated <= 1'b0;
- spi_uk_cmd <= spi_uk_cmd;
- end else if( cycle == 16'd7 ) begin // do command dispatch
- if( {inreg[6:0],sdin} == 8'h9f ) begin
- shiftout <= 24'hc86017;
- readmode <= 1'b0;
- spi_uk_cmd_updated <= 1'b1; // grab known for now
- spi_uk_cmd <= inreg[7:0];
- end else if( {inreg[6:0],sdin} == 8'h0b ) begin
- readmode <= 1'b1;
- shiftout <= shiftout;
- spi_uk_cmd_updated <= 1'b1; // grab known for now
- spi_uk_cmd <= inreg[7:0];
- end else begin
- spi_uk_cmd <= inreg[7:0]; // record the unknown command
- spi_uk_cmd_updated <= 1'b1;
- readmode <= 1'b0;
- shiftout <= shiftout;
- end
- end else begin // cycle > 16'd7
- shiftout[23:0] <= {shiftout[22:0],shiftout[23]};
- readmode <= readmode;
- spi_uk_cmd_updated <= 1'b0;
- spi_uk_cmd <= spi_uk_cmd;
- end
- end // always @ (negedge sclk)
-
- assign sdout = readmode ? dataout[31] : shiftout[23];
-
- always @(posedge sclk) begin
- // 8 cycles for command
- // 24 cycles for address
- // 8 dummy cycles because it's command 0B (only command we support)
- // 40th cycle start shifting the data
- if ( (cycle >= 16'd32) && (cycle[4:0] == 5'b0_0111) ) begin
- dataout[31:0] <= {rom_dout[7:0],rom_dout[15:8],rom_dout[23:16],rom_dout[31:24]};
- end else if( cycle >= 16'd40 ) begin
- dataout[31:0] <= {dataout[30:0],dataout[31]};
- end else begin
- dataout <= dataout;
- end
- end // always @ (negedge sclk)
-
-`endif
-
- // if cycle == 8'd34 && readmode, issue the read request to the dram interface
- // time to respond is thus 6 cycles * 37ns = 222 ns. Max DDR3 latency is 85ns. We should be ok.
- // this gives 130ns for data readback, which is enough time to trasnfer 208 bytes -- not
- // quite a whole page. We need 160ns to get the full page.
- // see if we can optimize to 7 cycles allowed response time to first data out
-
- wire my_a;
-
- // 19'h1_0000 >> 1 due to short-align
- assign my_a = (bus_a[18:16] == 3'b001);
-
- eimram spi_romulator_64k (
- .clka(eim_clk), // input clka
- .ena(my_a), // input ena
- .wea(we), // input [0 : 0] wea
- .addra(bus_a[15:1]), // input [14 : 0] addra
- .dina(bus_d[15:0]), // input [15 : 0] dina
- .clkb(sclk), // input clkb
- .addrb(address[15:2]), // input [13 : 0] addrb
- .doutb(rom_dout) // output [31 : 0] doutb // 4 bytes at a time
- );
-
- // shadow for readback (chee-z three portnedness
- wire [31:0] state;
- eimram spi_romulator_64k_shadow (
- .clka(eim_clk), // input clka
- .ena(my_a), // input ena
- .wea(we), // input [0 : 0] wea
- .addra(bus_a[15:1]), // input [14 : 0] addra
- .dina(bus_d[15:0]), // input [15 : 0] dina
- .clkb(eim_clk), // input clkb
- .addrb(bus_a[15:2]), // input [13 : 0] addrb
- .doutb(state) // output [31 : 0] doutb
- );
-
- always @(bus_a or my_a or re or state) begin
- if( my_a && re ) begin
- if( bus_a[1] == 1'b0 ) begin
- rbk_d = state[15:0];
- end else begin
- rbk_d = state[31:16];
- end
- end else begin
- rbk_d = 16'hZZZZ;
- end
- end
-
-endmodule // spi_eeprom
diff --git a/src/rtl/spi_eeprom_tb.v b/src/rtl/spi_eeprom_tb.v
deleted file mode 100755
index 431c214..0000000
--- a/src/rtl/spi_eeprom_tb.v
+++ /dev/null
@@ -1,317 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 2013, Andrew "bunnie" Huang
-//
-// See the NOTICE file distributed with this work for additional
-// information regarding copyright ownership. The copyright holder
-// licenses this file to you under the Apache License, Version 2.0
-// (the "License"); you may not use this file except in compliance
-// with the License. You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing,
-// code distributed under the License is distributed on an
-// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-// KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations
-// under the License.
-//////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-module spi_eeprom_tb;
-
- wire sdout;
- reg sdin;
- reg scs;
- reg sclk;
- reg swp;
- reg shold;
-
- reg eim_clk;
- reg [18:0] bus_a;
- reg [15:0] bus_d;
- reg we;
- reg re;
- wire [15:0] reg_d;
- wire [15:0] rbk_d;
-
- wire [7:0] spi_uk_cmd; // bitbucket for unknown commands
- wire spi_uk_cmd_updated;
-
- reg reset;
- reg sclk_on;
-
- // a RAM for sim sake
-// reg [15:0] extram [7:0];
-
- spi_eeprom dut (
- .sdout(sdout),
- .sdin(sdin),
- .scs(scs),
- .sclk(sclk),
- .swp(swp),
- .shold(shold),
-
- .eim_clk(eim_clk),
- .bus_a(bus_a),
- .bus_d(bus_d),
- .we(we),
- .re(re),
- .reg_d(reg_d),
- .rbk_d(rbk_d),
-
- .spi_uk_cmd(spi_uk_cmd),
- .spi_uk_cmd_updated(spi_uk_cmd_updated),
-
- .reset(reset)
- );
-
- parameter PERIOD = 16'd26; // 37 MHz
- always begin
- if( sclk_on ) begin
- sclk = 1'b0;
- #(PERIOD/2) sclk = 1'b1;
- #(PERIOD/2);
- end else begin
- sclk = 1'b0;
- #PERIOD;
- end
- end
-
- parameter PERIOD_EIM = 16'd26; // should be 125 MHz but adjust to this due to sim artifacts
- always begin
- eim_clk = 1'b0;
- #(PERIOD_EIM/2) eim_clk = 1'b1;
- #(PERIOD_EIM/2);
- end
-
- task seeprom_idle;
- begin
- sclk_on = 0;
- scs = 1;
- swp = 1;
- shold = 1;
- end
- endtask // nand_idle
-
- task eim_idle;
- begin
- we = 1'b0;
- re = 1'b0;
- bus_a = 18'h4E73;
- bus_d = 16'hzzzz;
- end
- endtask // nand_read_id
-
- task eim_write;
- input [18:0] t_a;
- input [15:0] t_d;
- begin // a poor approximation of what happens but good enough
- bus_a = t_a;
- #PERIOD_EIM;
- bus_d = t_d;
- #PERIOD_EIM;
- we = 1;
- #PERIOD_EIM;
- we = 0;
- #PERIOD_EIM;
- end
- endtask // eim_write
-
- task seeprom_id;
- begin
- scs = 1;
- sdin = 0;
- #PERIOD;
-
- scs = 0;
- sdin = 0;
- #PERIOD;
-
- // 9f
- sclk_on = 1;
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
-
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
-
- #(PERIOD*24);
- sclk_on = 0;
-
- #PERIOD;
- scs = 1;
- end
- endtask // seeprom_id
-
- task seeprom_invalid;
- begin
- scs = 1;
- sdin = 0;
- #PERIOD;
-
- scs = 0;
- sdin = 0;
- #PERIOD;
-
- // 03
- sclk_on = 1;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
-
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
-
- sdin = 1'b0;
- #(PERIOD*31);
- sclk_on = 0;
-
- #PERIOD;
- scs = 1;
- end
- endtask // seeprom_invalid
-
- integer index;
- task seeprom_read;
- input [15:0] t_a;
- begin
- scs = 1;
- sdin = 0;
- #PERIOD;
-
- scs = 0;
- sdin = 0;
- #PERIOD;
-
- // 0b
- sclk_on = 1;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
-
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b0;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
- sdin = 1'b1;
- #PERIOD;
-
- // top 8 bits always 0
- sdin = 1'b0;
- #(PERIOD*8);
-
- for( index = 15; index >=0; index = index - 1 ) begin
- sdin = t_a[index];
- #PERIOD;
- end
-
- // dummy cycle
- sdin = 1'b0;
- #(PERIOD*8);
-
- // and eight bytes of data
- sdin = 1'b0;
- #(PERIOD*64);
-
- sclk_on = 0;
-
- #PERIOD;
- scs = 1;
- #PERIOD;
- #PERIOD;
- end
- endtask // seeprom_read
-
- initial begin
- reset = 0;
-
- sclk_on = 0;
- sdin = 0;
- scs = 1;
- swp = 1;
- shold = 1;
-
- bus_a = 0;
- bus_d = 0;
- we = 0;
- re = 0;
-
- #(PERIOD);
- scs = 0;
- #(PERIOD*2);
- scs = 1;
- // $readmemb( "f:\largework\fpga\novena-sd-fpga\extram.bin", extram, 0, 65535 );
-
- #(PERIOD*4);
- $stop;
-
- // reset
- eim_idle();
- seeprom_idle();
- #(PERIOD*4);
- reset = 1;
- #(PERIOD*4);
- reset = 0;
- #(PERIOD*4);
- #(PERIOD*4);
-
- #(PERIOD*4);
-
- // now test
- eim_write(18'h1_0000, 16'hbeef);
- eim_write(18'h1_0004, 16'hdead);
- eim_write(18'h1_0006, 16'h8181);
- eim_write(18'h1_0008, 16'ha581);
- eim_write(18'h1_000A, 16'h6009);
-
- eim_write(18'h0_0000, 16'h3333); // this should do nothing
- #(PERIOD*4);
-
- seeprom_id();
-
- #(PERIOD*4);
-
- seeprom_read(16'h0004);
-
- #(PERIOD*4);
-
- seeprom_invalid();
-
- #(PERIOD*4);
-
- $stop;
- end // initial begin
-
-endmodule // romulator_tb
diff --git a/src/sw/Makefile b/src/sw/Makefile
index caf7e0f..4ea6a3f 100644
--- a/src/sw/Makefile
+++ b/src/sw/Makefile
@@ -1,4 +1,4 @@
-SOURCES=novena-fpga.c gpio.c eim.c
+SOURCES=novena-fpga.c
OBJECTS=$(SOURCES:.c=.o)
EXEC=novena-fpga
MY_CFLAGS += -Wall -O0 -g
diff --git a/src/sw/eim.c b/src/sw/eim.c
deleted file mode 100644
index 8896c0a..0000000
--- a/src/sw/eim.c
+++ /dev/null
@@ -1,285 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <strings.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <stdint.h>
-
-#include "gpio.h"
-#include "eim.h"
-
-#define EIM_BASE (0x08040000)
-#define EIM_DOUT (0x0010)
-#define EIM_DIR (0x0012)
-#define EIM_DIN (0x1010)
-
-static int *mem_32 = 0;
-static short *mem_16 = 0;
-static char *mem_8 = 0;
-static int *prev_mem_range = 0;
-
-uint8_t cached_dout = 0;
-uint8_t cached_dir = 0;
-
-static int read_kernel_memory(long offset, int virtualized, int size) {
- int result;
- static int mem_fd;
-
- int *mem_range = (int *)(offset & ~0xFFFF);
- if( mem_range != prev_mem_range ) {
- prev_mem_range = mem_range;
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(mem_fd)
- close(mem_fd);
-
- if(virtualized) {
- mem_fd = open("/dev/kmem", O_RDWR);
- if( mem_fd < 0 ) {
- perror("Unable to open /dev/kmem");
- mem_fd = 0;
- return -1;
- }
- }
- else {
- mem_fd = open("/dev/mem", O_RDWR);
- if( mem_fd < 0 ) {
- perror("Unable to open /dev/mem");
- mem_fd = 0;
- return -1;
- }
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, offset&~0xFFFF);
- if( (void *)-1 == mem_32 ) {
- perror("Unable to mmap file");
-
- if( -1 == close(mem_fd) )
- perror("Also couldn't close file");
-
- mem_fd=0;
- return -1;
- }
- mem_16 = (short *)mem_32;
- mem_8 = (char *)mem_32;
- }
-
- int scaled_offset = (offset-(offset&~0xFFFF));
- if(size==1)
- result = mem_8[scaled_offset/sizeof(char)];
- else if(size==2)
- result = mem_16[scaled_offset/sizeof(short)];
- else
- result = mem_32[scaled_offset/sizeof(long)];
-
- return result;
-}
-
-static int write_kernel_memory(long offset, long value, int virtualized, int size) {
- int old_value = read_kernel_memory(offset, virtualized, size);
- int scaled_offset = (offset-(offset&~0xFFFF));
- if(size==1)
- mem_8[scaled_offset/sizeof(char)] = value;
- else if(size==2)
- mem_16[scaled_offset/sizeof(short)] = value;
- else
- mem_32[scaled_offset/sizeof(long)] = value;
- return old_value;
-}
-
-
-static int prep_eim(void) {
- int i;
- // set up pads to be mapped to EIM
- for( i = 0; i < 16; i++ ) {
- write_kernel_memory( 0x20e0114 + i*4, 0x0, 0, 4 ); // mux mapping
- write_kernel_memory( 0x20e0428 + i*4, 0xb0b1, 0, 4 ); // pad strength config'd for a 100MHz rate
- }
-
- // mux mapping
- write_kernel_memory( 0x20e046c - 0x314, 0x0, 0, 4 ); // BCLK
- write_kernel_memory( 0x20e040c - 0x314, 0x0, 0, 4 ); // CS0
- write_kernel_memory( 0x20e0410 - 0x314, 0x0, 0, 4 ); // CS1
- write_kernel_memory( 0x20e0414 - 0x314, 0x0, 0, 4 ); // OE
- write_kernel_memory( 0x20e0418 - 0x314, 0x0, 0, 4 ); // RW
- write_kernel_memory( 0x20e041c - 0x314, 0x0, 0, 4 ); // LBA
- write_kernel_memory( 0x20e0468 - 0x314, 0x0, 0, 4 ); // WAIT
- write_kernel_memory( 0x20e0408 - 0x314, 0x0, 0, 4 ); // A16
- write_kernel_memory( 0x20e0404 - 0x314, 0x0, 0, 4 ); // A17
- write_kernel_memory( 0x20e0400 - 0x314, 0x0, 0, 4 ); // A18
-
- // pad strength
- write_kernel_memory( 0x20e046c, 0xb0b1, 0, 4 ); // BCLK
- write_kernel_memory( 0x20e040c, 0xb0b1, 0, 4 ); // CS0
- write_kernel_memory( 0x20e0410, 0xb0b1, 0, 4 ); // CS1
- write_kernel_memory( 0x20e0414, 0xb0b1, 0, 4 ); // OE
- write_kernel_memory( 0x20e0418, 0xb0b1, 0, 4 ); // RW
- write_kernel_memory( 0x20e041c, 0xb0b1, 0, 4 ); // LBA
- write_kernel_memory( 0x20e0468, 0xb0b1, 0, 4 ); // WAIT
- write_kernel_memory( 0x20e0408, 0xb0b1, 0, 4 ); // A16
- write_kernel_memory( 0x20e0404, 0xb0b1, 0, 4 ); // A17
- write_kernel_memory( 0x20e0400, 0xb0b1, 0, 4 ); // A18
-
- write_kernel_memory( 0x020c4080, 0xcf3, 0, 4 ); // ungate eim slow clocks
-
- // EIM_CS0GCR1
- // 0101 0 001 1 001 0 001 11 00 0 000 1 0 1 1 1 0 0 1
- // PSZ WP GBC AUS CSREC SP DSZ BCS BCD WC BL CREP CRE RFL WFL MUM SRD SWR CSEN
- //
- // PSZ = 0101 256 words page size
- // WP = 0 (not protected)
- // GBC = 001 min 1 cycles between chip select changes
- // AUS = 0 address shifted according to port size
- // CSREC = 001 min 1 cycles between CS, OE, WE signals
- // SP = 0 no supervisor protect (user mode access allowed)
- // DSZ = 001 16-bit port resides on DATA[15:0]
- // BCS = 11 3 clock delay for burst generation
- // BCD = 00 divide EIM clock by 1 for burst clock
- // WC = 0 specify write bust according to BL
- // BL = 000 4 words wrap burst length
- // CREP = 1 non-PSRAM, set to 1
- // CRE = 0 CRE is disabled
- // RFL = 1 fixed latency reads (don't monitor WAIT)
- // WFL = 1 fixed latency writes (don't monitor WAIT)
- // MUM = 1 multiplexed mode enabled
- // SRD = 0 no synch reads
- // SWR = 0 no synch writes
- // CSEN = 1 chip select is enabled
-
- // 0101 0111 1111 0001 1100 0000 1011 1 0 0 1
- // 0x5 7 F 1 C 0 B 9
-
- // 0101 0001 1001 0001 1100 0000 1011 1001
- // 5 1 9 1 c 0 B 9
-
- write_kernel_memory( 0x21b8000, 0x5191C0B9, 0, 4 );
-
- // EIM_CS0GCR2
- // MUX16_BYP_GRANT = 1
- // ADH = 1 (1 cycles)
- // 0x1001
- write_kernel_memory( 0x21b8004, 0x1001, 0, 4 );
-
-
- // EIM_CS0RCR1
- // 00 000101 0 000 0 000 0 000 0 000 0 000 0 000
- // RWSC RADVA RAL RADVN OEA OEN RCSA RCSN
- // RWSC 000101 5 cycles for reads to happen
- //
- // 0000 0111 0000 0011 0000 0000 0000 0000
- // 0 7 0 3 0 0 0 0
- // 0000 0101 0000 0000 0 000 0 000 0 000 0 000
- // write_kernel_memory( 0x21b8008, 0x05000000, 0, 4 );
- write_kernel_memory( 0x21b8008, 0x0A024000, 0, 4 );
- // EIM_CS0RCR2
- // 0000 0000 0 000 00 00 0 010 0 001
- // APR PAT RL RBEA RBEN
- // APR = 0 mandatory because MUM = 1
- // PAT = XXX because APR = 0
- // RL = 00 because async mode
- // RBEA = 000 these match RCSA/RCSN from previous field
- // RBEN = 000
- // 0000 0000 0000 0000 0000 0000
- write_kernel_memory( 0x21b800c, 0x00000000, 0, 4 );
-
- // EIM_CS0WCR1
- // 0 0 000100 000 000 000 000 010 000 000 000
- // WAL WBED WWSC WADVA WADVN WBEA WBEN WEA WEN WCSA WCSN
- // WAL = 0 use WADVN
- // WBED = 0 allow BE during write
- // WWSC = 000100 4 write wait states
- // WADVA = 000 same as RADVA
- // WADVN = 000 this sets WE length to 1 (this value +1)
- // WBEA = 000 same as RBEA
- // WBEN = 000 same as RBEN
- // WEA = 010 2 cycles between beginning of access and WE assertion
- // WEN = 000 1 cycles to end of WE assertion
- // WCSA = 000 cycles to CS assertion
- // WCSN = 000 cycles to CS negation
- // 1000 0111 1110 0001 0001 0100 0101 0001
- // 8 7 E 1 1 4 5 1
- // 0000 0111 0000 0100 0000 1000 0000 0000
- // 0 7 0 4 0 8 0 0
- // 0000 0100 0000 0000 0000 0100 0000 0000
- // 0 4 0 0 0 4 0 0
-
- write_kernel_memory( 0x21b8010, 0x09080800, 0, 4 );
-
- // EIM_WCR
- // BCM = 1 free-run BCLK
- // GBCD = 0 don't divide the burst clock
- write_kernel_memory( 0x21b8090, 0x1, 0, 4 );
-
- // EIM_WIAR
- // ACLK_EN = 1
- write_kernel_memory( 0x21b8094, 0x10, 0, 4 );
-
- return 0;
-}
-
-uint16_t *eim_get(enum eim_type type) {
- static uint16_t *mem = NULL;
- static int fd;
-
- if (mem)
- return ((uint16_t *) (((uint8_t *)mem)+type));
-
- prep_eim();
-
- fd = open("/dev/mem", O_RDWR);
- if (fd == -1) {
- perror("Couldn't open /dev/mem");
- return NULL;
- }
-
- mem = mmap(NULL, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, EIM_BASE);
- if (mem == ((uint16_t *)-1)) {
- perror("Couldn't mmap EIM region");
- return NULL;
- }
-
- return eim_get(type);
-}
-
-int eim_set_direction(int gpio, int is_output) {
- uint16_t *mem = eim_get(fpga_w_gpioa_dir);
- if (!mem)
- return -1;
- gpio &= ~GPIO_IS_EIM;
- if (is_output)
- cached_dir |= (1<<gpio);
- else
- // Clear direction
- cached_dir &= ~(1<<gpio);
-
- *mem = cached_dir;
- return 0;
-}
-
-
-int eim_set_value(int gpio, int value) {
- uint16_t *mem = eim_get(fpga_w_gpioa_dout);
- if (!mem)
- return -1;
- gpio &= ~GPIO_IS_EIM;
- if (value)
- cached_dout |= (1<<gpio);
- else
- cached_dout &= ~(1<<gpio);
- *mem = cached_dout;
- return 0;
-}
-
-int eim_get_value(int gpio) {
- uint16_t *mem = eim_get(fpga_r_gpioa_din);
- if (!mem)
- return -1;
- gpio &= ~GPIO_IS_EIM;
- return (*mem >> gpio)&1;
-}
-
diff --git a/src/sw/eim.h b/src/sw/eim.h
deleted file mode 100644
index ee7def3..0000000
--- a/src/sw/eim.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __eim_h__
-#define __eim_h__
-
-enum eim_type {
- fpga_w_test0 = 0x0000,
- fpga_w_test1 = 0x0002,
- fpga_w_gpioa_dout = 0x0010,
- fpga_w_gpioa_dir = 0x0012,
-
- fpga_w_ddr3_p2_cmd = 0x0020,
- fpga_w_ddr3_p2_ladr = 0x0022,
- fpga_w_ddr3_p2_hadr = 0x0024,
- fpga_w_ddr3_p2_wen = 0x0026,
- fpga_w_ddr3_p2_ldat = 0x0028,
- fpga_w_ddr3_p2_hdat = 0x002A,
-
- fpga_w_ddr3_p3_cmd = 0x0030,
- fpga_w_ddr3_p3_ladr = 0x0032,
- fpga_w_ddr3_p3_hadr = 0x0034,
- fpga_w_ddr3_p3_ren = 0x0036,
-
- fpga_w_nand_uk_ctl = 0x0100,
- fpga_w_nand_power = 0x0102,
-
- fpga_r_test0 = 0x1000,
- fpga_r_test1 = 0x1002,
- fpga_r_ddr3_cal = 0x1004,
- fpga_r_gpioa_din = 0x1010,
-
- fpga_r_ddr3_p2_stat = 0x1020,
- fpga_r_ddr3_p3_stat = 0x1030,
- fpga_r_ddr3_p3_ldat = 0x1032,
- fpga_r_ddr3_p3_hdat = 0x1034,
-
- // every time I read it auto-advances the queue
- fpga_r_nand_uk_data = 0x1100,
- fpga_r_nand_uk_stat = 0x1102,
-
- fpga_r_ddr3_v_minor = 0x1FFC,
- fpga_r_ddr3_v_major = 0x1FFE,
-
-};
-
-uint16_t *eim_get(enum eim_type type);
-
-#endif // __eim_h__
diff --git a/src/sw/gpio.c b/src/sw/gpio.c
deleted file mode 100644
index 43a67f4..0000000
--- a/src/sw/gpio.c
+++ /dev/null
@@ -1,163 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <strings.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <stdint.h>
-
-#include "gpio.h"
-
-#define GPIO_PATH "/sys/class/gpio"
-#define EXPORT_PATH GPIO_PATH "/export"
-#define UNEXPORT_PATH GPIO_PATH "/unexport"
-
-static int gpio_is_exported(int gpio) {
- char gpio_path[256];
- struct stat buf;
- int ret;
- snprintf(gpio_path, sizeof(gpio_path)-1, GPIO_PATH "/gpio%d/direction", gpio);
- ret = stat(gpio_path, &buf);
- if (ret == -1)
- return 0;
- return 1;
-}
-
-
-static int gpio_export_unexport(char *path, int gpio) {
- int fd;
- char str[16];
- int bytes;
-
- fd = open(path, O_WRONLY);
- if (fd == -1) {
- perror("Unable to find GPIO files -- /sys/class/gpio enabled?");
- return -errno;
- }
-
- bytes = snprintf(str, sizeof(str)-1, "%d", gpio) + 1;
-
- if (-1 == write(fd, str, bytes)) {
- fprintf(stderr, "Unable to modify gpio%d: %s",
- gpio, strerror(errno));
- close(fd);
- return -errno;
- }
-
- close(fd);
- return 0;
-}
-
-int gpio_export(int gpio) {
- if (gpio&GPIO_IS_EIM)
- return 0;
- if (gpio_is_exported(gpio))
- return 0;
- return gpio_export_unexport(EXPORT_PATH, gpio);
-}
-
-int gpio_unexport(int gpio) {
- if (gpio&GPIO_IS_EIM)
- return 0;
- if (!gpio_is_exported(gpio))
- return 0;
- return gpio_export_unexport(UNEXPORT_PATH, gpio);
-}
-
-int gpio_set_direction(int gpio, int is_output) {
- char gpio_path[256];
- int fd;
- int ret;
-
- if (gpio&GPIO_IS_EIM)
- return eim_set_direction(gpio&(~GPIO_IS_EIM), is_output);
-
- snprintf(gpio_path, sizeof(gpio_path)-1, GPIO_PATH "/gpio%d/direction", gpio);
-
- fd = open(gpio_path, O_WRONLY);
- if (fd == -1) {
- fprintf(stderr, "Direction file: [%s]\n", gpio_path);
- perror("Couldn't open direction file for gpio");
- return -errno;
- }
-
- if (is_output)
- ret = write(fd, "out", 4);
- else
- ret = write(fd, "in", 3);
-
- if (ret == -1) {
- perror("Couldn't set output direction");
- close(fd);
- return -errno;
- }
-
- close(fd);
- return 0;
-}
-
-
-int gpio_set_value(int gpio, int value) {
- char gpio_path[256];
- int fd;
- int ret;
-
- if (gpio&GPIO_IS_EIM)
- return eim_set_value(gpio&(~GPIO_IS_EIM), value);
-
- snprintf(gpio_path, sizeof(gpio_path)-1, GPIO_PATH "/gpio%d/value", gpio);
-
- fd = open(gpio_path, O_WRONLY);
- if (fd == -1) {
- fprintf(stderr, "Value file: [%s]\n", gpio_path);
- perror("Couldn't open value file for gpio");
- return -errno;
- }
-
- if (value)
- ret = write(fd, "1", 2);
- else
- ret = write(fd, "0", 2);
-
- if (ret == -1) {
- fprintf(stderr, "Couldn't set GPIO %d output value: %s\n",
- gpio, strerror(errno));
- close(fd);
- return -errno;
- }
-
- close(fd);
- return 0;
-}
-
-
-int gpio_get_value(int gpio) {
- char gpio_path[256];
- int fd;
-
- if (gpio&GPIO_IS_EIM)
- return eim_get_value(gpio&(~GPIO_IS_EIM));
-
- snprintf(gpio_path, sizeof(gpio_path)-1, GPIO_PATH "/gpio%d/value", gpio);
-
- fd = open(gpio_path, O_RDONLY);
- if (fd == -1) {
- perror("Couldn't open value file for gpio");
- return -errno;
- }
-
- if (read(fd, gpio_path, sizeof(gpio_path)) <= 0) {
- perror("Couldn't get input value");
- close(fd);
- return -errno;
- }
-
- close(fd);
-
- return gpio_path[0] != '0';
-}
-
-
diff --git a/src/sw/gpio.h b/src/sw/gpio.h
deleted file mode 100644
index 59716c2..0000000
--- a/src/sw/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-#define GPIO_IS_EIM (0x80000000)
-
-enum gpio_dir {
- GPIO_IN = 0,
- GPIO_OUT = 1,
-};
-
-int gpio_export(int gpio);
-int gpio_unexport(int gpio);
-int gpio_set_direction(int gpio, int is_output);
-int gpio_set_value(int gpio, int value);
-int gpio_get_value(int gpio);
-
-
-int eim_set_direction(int gpio, int is_output);
-int eim_set_value(int gpio, int value);
-int eim_get_value(int gpio);
-#endif /* __GPIO_H__ */
diff --git a/src/sw/hash_tester.c b/src/sw/hash_tester.c
new file mode 100644
index 0000000..9d86fa8
--- /dev/null
+++ b/src/sw/hash_tester.c
@@ -0,0 +1,962 @@
+/*
+ * hash_tester.c
+ * --------------
+ * This program sends several commands to the coretest_hashes subsystem
+ * in order to verify the SHA-1, SHA-256 and SHA-512/x hash function
+ * cores.
+ *
+ * Note: This version of the program talks to the FPGA over an EIM bus.
+ *
+ * The single and dual block test cases are taken from the
+ * NIST KAT document:
+ * http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
+ *
+ *
+ * Authors: Joachim Strömbergson, Paul Selkirk
+ * Copyright (c) 2014, NORDUnet A/S All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ * be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <time.h>
+#include <sys/ioctl.h>
+#include <arpa/inet.h>
+#include <ctype.h>
+
+int debug = 0;
+
+#define EIM_ADDR_BASE 0x08040000
+
+/* addresses and codes common to all hash cores */
+#define ADDR_NAME0 0x00
+#define ADDR_NAME1 0x04
+#define ADDR_VERSION 0x08
+#define ADDR_CTRL 0x20
+#define CTRL_INIT_CMD 1
+#define CTRL_NEXT_CMD 2
+#define ADDR_STATUS 0x24
+#define STATUS_READY_BIT 1
+#define STATUS_VALID_BIT 2
+#define ADDR_BLOCK 0x40
+#define ADDR_DIGEST 0x80
+
+/* addresses and codes for the specific hash cores */
+#define SHA1_ADDR_BASE 0x2000
+#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0
+#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1
+#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION
+#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL
+#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS
+#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK
+#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST
+#define SHA1_BLOCK_LEN 512 / 8
+#define SHA1_DIGEST_LEN 160 / 8
+
+#define SHA256_ADDR_BASE 0x3000
+#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0
+#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1
+#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION
+#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL
+#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS
+#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK
+#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST
+#define SHA256_BLOCK_LEN 512 / 8
+#define SHA256_DIGEST_LEN 256 / 8
+
+#define SHA512_ADDR_BASE 0x4000
+#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0
+#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1
+#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION
+#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL
+#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS
+#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK
+#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x100
+#define SHA512_BLOCK_LEN 1024 / 8
+#define SHA512_224_DIGEST_LEN 224 / 8
+#define SHA512_256_DIGEST_LEN 256 / 8
+#define SHA384_DIGEST_LEN 384 / 8
+#define SHA512_DIGEST_LEN 512 / 8
+#define MODE_SHA_512_224 0 << 2
+#define MODE_SHA_512_256 1 << 2
+#define MODE_SHA_384 2 << 2
+#define MODE_SHA_512 3 << 2
+
+/* SHA-1/SHA-256 One Block Message Sample
+ Input Message: "abc" */
+const uint8_t NIST_512_SINGLE[] =
+{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 };
+
+const uint8_t SHA1_SINGLE_DIGEST[] =
+{ 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a,
+ 0xba, 0x3e, 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c,
+ 0x9c, 0xd0, 0xd8, 0x9d };
+
+const uint8_t SHA256_SINGLE_DIGEST[] =
+{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA,
+ 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23,
+ 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C,
+ 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD };
+
+/* SHA-1/SHA-256 Two Block Message Sample
+ Input Message: "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" */
+const uint8_t NIST_512_DOUBLE0[] =
+{ 0x61, 0x62, 0x63, 0x64, 0x62, 0x63, 0x64, 0x65,
+ 0x63, 0x64, 0x65, 0x66, 0x64, 0x65, 0x66, 0x67,
+ 0x65, 0x66, 0x67, 0x68, 0x66, 0x67, 0x68, 0x69,
+ 0x67, 0x68, 0x69, 0x6A, 0x68, 0x69, 0x6A, 0x6B,
+ 0x69, 0x6A, 0x6B, 0x6C, 0x6A, 0x6B, 0x6C, 0x6D,
+ 0x6B, 0x6C, 0x6D, 0x6E, 0x6C, 0x6D, 0x6E, 0x6F,
+ 0x6D, 0x6E, 0x6F, 0x70, 0x6E, 0x6F, 0x70, 0x71,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+const uint8_t NIST_512_DOUBLE1[] =
+{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0 };
+
+const uint8_t SHA1_DOUBLE_DIGEST[] =
+{ 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E,
+ 0xBA, 0xAE, 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5,
+ 0xE5, 0x46, 0x70, 0xF1 };
+
+const uint8_t SHA256_DOUBLE_DIGEST[] =
+{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8,
+ 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39,
+ 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67,
+ 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 };
+
+/* SHA-512 One Block Message Sample
+ Input Message: "abc" */
+const uint8_t NIST_1024_SINGLE[] =
+{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 };
+
+const uint8_t SHA512_224_SINGLE_DIGEST[] =
+{ 0x46, 0x34, 0x27, 0x0f, 0x70, 0x7b, 0x6a, 0x54,
+ 0xda, 0xae, 0x75, 0x30, 0x46, 0x08, 0x42, 0xe2,
+ 0x0e, 0x37, 0xed, 0x26, 0x5c, 0xee, 0xe9, 0xa4,
+ 0x3e, 0x89, 0x24, 0xaa };
+const uint8_t SHA512_256_SINGLE_DIGEST[] =
+{ 0x53, 0x04, 0x8e, 0x26, 0x81, 0x94, 0x1e, 0xf9,
+ 0x9b, 0x2e, 0x29, 0xb7, 0x6b, 0x4c, 0x7d, 0xab,
+ 0xe4, 0xc2, 0xd0, 0xc6, 0x34, 0xfc, 0x6d, 0x46,
+ 0xe0, 0xe2, 0xf1, 0x31, 0x07, 0xe7, 0xaf, 0x23 };
+const uint8_t SHA384_SINGLE_DIGEST[] =
+{ 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b,
+ 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07,
+ 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63,
+ 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed,
+ 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23,
+ 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 };
+const uint8_t SHA512_SINGLE_DIGEST[] =
+{ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba,
+ 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31,
+ 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
+ 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a,
+ 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8,
+ 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
+ 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e,
+ 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f };
+
+/* SHA-512 Two Block Message Sample
+ Input Message: "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn"
+ "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" */
+const uint8_t NIST_1024_DOUBLE0[] =
+{ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+ 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+ 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a,
+ 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b,
+ 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c,
+ 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d,
+ 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
+ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+ 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
+ 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
+ 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72,
+ 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73,
+ 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74,
+ 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+const uint8_t NIST_1024_DOUBLE1[] =
+{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 };
+
+const uint8_t SHA512_224_DOUBLE_DIGEST[] =
+{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23,
+ 0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33,
+ 0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72,
+ 0x68, 0x67, 0x4a, 0xf9 };
+const uint8_t SHA512_256_DOUBLE_DIGEST[] =
+{ 0x39, 0x28, 0xe1, 0x84, 0xfb, 0x86, 0x90, 0xf8,
+ 0x40, 0xda, 0x39, 0x88, 0x12, 0x1d, 0x31, 0xbe,
+ 0x65, 0xcb, 0x9d, 0x3e, 0xf8, 0x3e, 0xe6, 0x14,
+ 0x6f, 0xea, 0xc8, 0x61, 0xe1, 0x9b, 0x56, 0x3a };
+const uint8_t SHA384_DOUBLE_DIGEST[] =
+{ 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8,
+ 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47,
+ 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2,
+ 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12,
+ 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9,
+ 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 };
+const uint8_t SHA512_DOUBLE_DIGEST[] =
+{ 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda,
+ 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f,
+ 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1,
+ 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18,
+ 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4,
+ 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a,
+ 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54,
+ 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 };
+
+/* ---------------- EIM low-level code ---------------- */
+
+/* Here be dragons.
+ *
+ * 1. setup_fpga() is some serious rubber-chicken voodoo, and I'm not
+ * convinced it's 100% correct. In particular, memcpy() seems to result in
+ * stuttering.
+ *
+ * 2. The native transfer size for EIM is 16 bits, and it *byte swaps* on the
+ * wire. Again, this has been observed with memcpy. I hope it's a peculiarity
+ * of the implementation, and not a "feature" of the protocol.
+ *
+ * 3. Remember that this is mmap'd memory, and you have to calculate the
+ * offset from the base of the block. If you try to access address 0x08042000
+ * directly, Bad Things will happen (really, it will just seg-fault).
+ */
+
+static int fd = 0;
+static uint32_t *mem_32 = NULL;
+static uint16_t *mem_16 = NULL;
+static uint8_t *mem_8 = NULL;
+static void *prev_mem_range = NULL;
+
+void map_mem(off_t offset)
+{
+ void *mem_range = (void *)(offset & ~0xFFFF);
+
+ if (mem_range == prev_mem_range)
+ return;
+
+ //fprintf(stderr, "New range detected. Reopening at memory range %p\n", mem_range);
+ prev_mem_range = mem_range;
+
+ if (mem_32)
+ munmap((void *)mem_32, 0xFFFF);
+ if (fd)
+ close(fd);
+
+ fd = open("/dev/mem", O_RDWR);
+ if (fd < 0) {
+ perror("Unable to open /dev/mem");
+ fd = 0;
+ return;
+ }
+
+ mem_32 = (uint32_t *)mmap(NULL, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, offset&~0xFFFF);
+ if (mem_32 == MAP_FAILED) {
+ perror("Unable to mmap file");
+
+ if (close(fd) < 0)
+ perror("Also couldn't close file");
+
+ fd=0;
+ return;
+ }
+ mem_16 = (uint16_t *)mem_32;
+ mem_8 = (uint8_t *)mem_32;
+}
+
+uint32_t read_kernel_memory(off_t offset, size_t size)
+{
+ uint32_t result;
+
+ //fprintf(stderr, "read_kernel_memory(0x%04x, %d)\n", (unsigned int)offset, (int)size);
+ map_mem(offset);
+
+ off_t scaled_offset = (offset-(offset&~0xFFFF));
+ //fprintf(stderr, "Returning offset 0x%08x\n", scaled_offset);
+ if (size == 1)
+ result = mem_8[scaled_offset/sizeof(uint8_t)];
+ else if (size == 2)
+ result = mem_16[scaled_offset/sizeof(uint16_t)];
+ else
+ result = mem_32[scaled_offset/sizeof(uint32_t)];
+
+ return result;
+}
+
+uint32_t write_kernel_memory(off_t offset, uint32_t value, size_t size)
+{
+ uint32_t old_value = read_kernel_memory(offset, size);
+ off_t scaled_offset = (offset-(offset&~0xFFFF));
+ if (size == 1)
+ mem_8[scaled_offset/sizeof(uint8_t)] = value;
+ else if (size == 2)
+ mem_16[scaled_offset/sizeof(uint16_t)] = value;
+ else
+ mem_32[scaled_offset/sizeof(uint32_t)] = value;
+ return old_value;
+}
+
+void setup_fpga() {
+ int i;
+ //printf( "setting up EIM CS0 (register interface) pads and configuring timing\n" );
+ // set up pads to be mapped to EIM
+ for( i = 0; i < 16; i++ ) {
+ write_kernel_memory( 0x20e0114 + i*4, 0x0, 4 ); // mux mapping
+ write_kernel_memory( 0x20e0428 + i*4, 0xb0b1, 4 ); // pad strength config'd for a 100MHz rate
+ }
+
+ // mux mapping
+ write_kernel_memory( 0x20e046c - 0x314, 0x0, 4 ); // BCLK
+ write_kernel_memory( 0x20e040c - 0x314, 0x0, 4 ); // CS0
+ write_kernel_memory( 0x20e0410 - 0x314, 0x0, 4 ); // CS1
+ write_kernel_memory( 0x20e0414 - 0x314, 0x0, 4 ); // OE
+ write_kernel_memory( 0x20e0418 - 0x314, 0x0, 4 ); // RW
+ write_kernel_memory( 0x20e041c - 0x314, 0x0, 4 ); // LBA
+ write_kernel_memory( 0x20e0468 - 0x314, 0x0, 4 ); // WAIT
+ write_kernel_memory( 0x20e0408 - 0x314, 0x0, 4 ); // A16
+ write_kernel_memory( 0x20e0404 - 0x314, 0x0, 4 ); // A17
+ write_kernel_memory( 0x20e0400 - 0x314, 0x0, 4 ); // A18
+
+ // pad strength
+ write_kernel_memory( 0x20e046c, 0xb0b1, 4 ); // BCLK
+ write_kernel_memory( 0x20e040c, 0xb0b1, 4 ); // CS0
+ write_kernel_memory( 0x20e0410, 0xb0b1, 4 ); // CS1
+ write_kernel_memory( 0x20e0414, 0xb0b1, 4 ); // OE
+ write_kernel_memory( 0x20e0418, 0xb0b1, 4 ); // RW
+ write_kernel_memory( 0x20e041c, 0xb0b1, 4 ); // LBA
+ write_kernel_memory( 0x20e0468, 0xb0b1, 4 ); // WAIT
+ write_kernel_memory( 0x20e0408, 0xb0b1, 4 ); // A16
+ write_kernel_memory( 0x20e0404, 0xb0b1, 4 ); // A17
+ write_kernel_memory( 0x20e0400, 0xb0b1, 4 ); // A18
+
+ write_kernel_memory( 0x020c4080, 0xcf3, 4 ); // ungate eim slow clocks
+
+ // rework timing for sync use
+ // EIM_CS0GCR1
+ // 0011 0 001 1 001 0 001 00 00 1 011 1 0 1 1 1 1 1 1
+ // PSZ WP GBC AUS CSREC SP DSZ BCS BCD WC BL CREP CRE RFL WFL MUM SRD SWR CSEN
+ //
+ // PSZ = 0011 64 words page size
+ // WP = 0 (not protected)
+ // GBC = 001 min 1 cycles between chip select changes
+ // AUS = 0 address shifted according to port size
+ // CSREC = 001 min 1 cycles between CS, OE, WE signals
+ // SP = 0 no supervisor protect (user mode access allowed)
+ // DSZ = 001 16-bit port resides on DATA[15:0]
+ // BCS = 00 0 clock delay for burst generation
+ // BCD = 00 divide EIM clock by 0 for burst clock
+ // WC = 1 write accesses are continuous burst length
+ // BL = 011 32 word memory wrap length
+ // CREP = 1 non-PSRAM, set to 1
+ // CRE = 0 CRE is disabled
+ // RFL = 1 fixed latency reads
+ // WFL = 1 fixed latency writes
+ // MUM = 1 multiplexed mode enabled
+ // SRD = 1 synch reads
+ // SWR = 1 synch writes
+ // CSEN = 1 chip select is enabled
+
+ // write_kernel_memory( 0x21b8000, 0x5191C0B9, 4 );
+ write_kernel_memory( 0x21b8000, 0x31910BBF, 4 );
+
+ // EIM_CS0GCR2
+ // MUX16_BYP_GRANT = 1
+ // ADH = 1 (1 cycles)
+ // 0x1001
+ write_kernel_memory( 0x21b8004, 0x1000, 4 );
+
+
+ // EIM_CS0RCR1
+ // 00 000101 0 000 0 000 0 000 0 000 0 000 0 000
+ // RWSC RADVA RAL RADVN OEA OEN RCSA RCSN
+ // RWSC 000101 5 cycles for reads to happen
+ //
+ // 0000 0111 0000 0011 0000 0000 0000 0000
+ // 0 7 0 3 0 0 0 0
+ // 0000 0101 0000 0000 0 000 0 000 0 000 0 000
+// write_kernel_memory( 0x21b8008, 0x05000000, 4 );
+// write_kernel_memory( 0x21b8008, 0x0A024000, 4 );
+ write_kernel_memory( 0x21b8008, 0x09014000, 4 );
+ // EIM_CS0RCR2
+ // 0000 0000 0 000 00 00 0 010 0 001
+ // APR PAT RL RBEA RBEN
+ // APR = 0 mandatory because MUM = 1
+ // PAT = XXX because APR = 0
+ // RL = 00 because async mode
+ // RBEA = 000 these match RCSA/RCSN from previous field
+ // RBEN = 000
+ // 0000 0000 0000 0000 0000 0000
+ write_kernel_memory( 0x21b800c, 0x00000000, 4 );
+
+ // EIM_CS0WCR1
+ // 0 0 000100 000 000 000 000 010 000 000 000
+ // WAL WBED WWSC WADVA WADVN WBEA WBEN WEA WEN WCSA WCSN
+ // WAL = 0 use WADVN
+ // WBED = 0 allow BE during write
+ // WWSC = 000100 4 write wait states
+ // WADVA = 000 same as RADVA
+ // WADVN = 000 this sets WE length to 1 (this value +1)
+ // WBEA = 000 same as RBEA
+ // WBEN = 000 same as RBEN
+ // WEA = 010 2 cycles between beginning of access and WE assertion
+ // WEN = 000 1 cycles to end of WE assertion
+ // WCSA = 000 cycles to CS assertion
+ // WCSN = 000 cycles to CS negation
+ // 1000 0111 1110 0001 0001 0100 0101 0001
+ // 8 7 E 1 1 4 5 1
+ // 0000 0111 0000 0100 0000 1000 0000 0000
+ // 0 7 0 4 0 8 0 0
+ // 0000 0100 0000 0000 0000 0100 0000 0000
+ // 0 4 0 0 0 4 0 0
+
+ write_kernel_memory( 0x21b8010, 0x09080800, 4 );
+ // write_kernel_memory( 0x21b8010, 0x02040400, 4 );
+
+ // EIM_WCR
+ // BCM = 1 free-run BCLK
+ // GBCD = 0 don't divide the burst clock
+ write_kernel_memory( 0x21b8090, 0x701, 4 );
+
+ // EIM_WIAR
+ // ACLK_EN = 1
+ write_kernel_memory( 0x21b8094, 0x10, 4 );
+
+ //printf( "done.\n" );
+
+ map_mem(EIM_ADDR_BASE);
+}
+
+void eim_copy(void *dest, void *src, int len)
+{
+ int i;
+ for (i = 0; i < len/2; ++i) {
+ ((uint16_t *)dest)[i] = htons(((uint16_t *)src)[i]);
+ }
+}
+
+/* ---------------- test-case low-level code ---------------- */
+
+int tc_write(off_t offset, const uint8_t *buf, int len)
+{
+ if (debug) {
+ int i;
+ printf("write [");
+ for (i = 0; i < len; ++i)
+ printf(" %02x", buf[i]);
+ printf(" ]\n");
+ }
+
+ eim_copy((void *)(mem_8 + offset), (void *)buf, len);
+
+ return 0;
+}
+
+int tc_read(off_t offset, uint8_t *buf, int len)
+{
+ eim_copy((void *)buf, (void *)(mem_8 + offset), len);
+
+ if (debug) {
+ int i;
+ printf("read [");
+ for (i = 0; i < len; ++i)
+ printf(" %02x", buf[i]);
+ printf(" ]\n");
+ }
+
+ return 0;
+}
+
+int tc_expected(off_t offset, const uint8_t *expected, int len)
+{
+ uint8_t *buf;
+ int i;
+
+ buf = malloc(len);
+ if (buf == NULL) {
+ perror("malloc");
+ return 1;
+ }
+ if (debug) {
+ int i;
+ printf("expect [");
+ for (i = 0; i < len; ++i)
+ printf(" %02x", expected[i]);
+ printf(" ]\n");
+ }
+
+ if (tc_read(offset, buf, len) != 0)
+ goto errout;
+
+ for (i = 0; i < len; ++i)
+ if (buf[i] != expected[i]) {
+ fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n",
+ i, expected[i], buf[i]);
+ goto errout;
+ }
+
+ free(buf);
+ return 0;
+errout:
+ free(buf);
+ return 1;
+}
+
+int tc_init(off_t offset)
+{
+ uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD };
+
+ return tc_write(offset, buf, 4);
+}
+
+int tc_next(off_t offset)
+{
+ uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD };
+
+ return tc_write(offset, buf, 4);
+}
+
+int tc_wait(off_t offset, uint8_t status)
+{
+ uint8_t buf[4];
+
+ do {
+ if (tc_read(offset, buf, 4) != 0)
+ return 1;
+ } while (!(buf[3] & status));
+
+ return 0;
+}
+
+int tc_wait_ready(off_t offset)
+{
+ return tc_wait(offset, STATUS_READY_BIT);
+}
+
+int tc_wait_valid(off_t offset)
+{
+ return tc_wait(offset, STATUS_VALID_BIT);
+}
+
+/* ---------------- SHA-1 test cases ---------------- */
+
+/* TC1: Read name and version from SHA-1 core. */
+int TC1(void)
+{
+ uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x31 }; /* "sha1" */
+ uint8_t name1[4] = { 0x20, 0x20, 0x20, 0x20 }; /* " " */
+ uint8_t version[4] = { 0x30, 0x2e, 0x35, 0x30 }; /* "0.50" */
+
+ printf("TC1: Reading name, type and version words from SHA-1 core.\n");
+
+ return
+ tc_expected(SHA1_ADDR_NAME0, name0, 4) ||
+ tc_expected(SHA1_ADDR_NAME1, name1, 4) ||
+ tc_expected(SHA1_ADDR_VERSION, version, 4);
+}
+
+/* TC2: SHA-1 Single block message test as specified by NIST. */
+int TC2(void)
+{
+ const uint8_t *block = NIST_512_SINGLE;
+ const uint8_t *expected = SHA1_SINGLE_DIGEST;
+
+ printf("TC2: Single block message test for SHA-1.\n");
+
+ return
+ /* Write block to SHA-1. */
+ tc_write(SHA1_ADDR_BLOCK, block, SHA1_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_init(SHA1_ADDR_CTRL) ||
+ tc_wait_valid(SHA1_ADDR_STATUS) ||
+ /* Extract the digest. */
+ tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN);
+}
+
+/* TC3: SHA-1 Double block message test as specified by NIST. */
+int TC3(void)
+{
+ const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 };
+ static const uint8_t block0_expected[] =
+ { 0xF4, 0x28, 0x68, 0x18, 0xC3, 0x7B, 0x27, 0xAE,
+ 0x04, 0x08, 0xF5, 0x81, 0x84, 0x67, 0x71, 0x48,
+ 0x4A, 0x56, 0x65, 0x72 };
+ const uint8_t *expected = SHA1_DOUBLE_DIGEST;
+
+ printf("TC3: Double block message test for SHA-1.\n");
+
+ return
+ /* Write first block to SHA-1. */
+ tc_write(SHA1_ADDR_BLOCK, block[0], SHA1_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_init(SHA1_ADDR_CTRL) ||
+ tc_wait_valid(SHA1_ADDR_STATUS) ||
+ /* Extract the first digest. */
+ tc_expected(SHA1_ADDR_DIGEST, block0_expected, SHA1_DIGEST_LEN) ||
+ /* Write second block to SHA-1. */
+ tc_write(SHA1_ADDR_BLOCK, block[1], SHA1_BLOCK_LEN) ||
+ /* Start next block hashing, wait and check status. */
+ tc_next(SHA1_ADDR_CTRL) ||
+ tc_wait_valid(SHA1_ADDR_STATUS) ||
+ /* Extract the second digest. */
+ tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN);
+}
+
+/* ---------------- SHA-256 test cases ---------------- */
+
+/* TC4: Read name and version from SHA-256 core. */
+int TC4(void)
+{
+ uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x32 }; /* "sha2" */
+ uint8_t name1[4] = { 0x2d, 0x32, 0x35, 0x36 }; /* "-256" */
+ uint8_t version[4] = { 0x30, 0x2e, 0x38, 0x30 }; /* "0.80" */
+
+ printf("TC4: Reading name, type and version words from SHA-256 core.\n");
+
+ return
+ tc_expected(SHA256_ADDR_NAME0, name0, 4) ||
+ tc_expected(SHA256_ADDR_NAME1, name1, 4) ||
+ tc_expected(SHA256_ADDR_VERSION, version, 4);
+}
+
+/* TC5: SHA-256 Single block message test as specified by NIST. */
+int TC5()
+{
+ const uint8_t *block = NIST_512_SINGLE;
+ const uint8_t *expected = SHA256_SINGLE_DIGEST;
+
+ printf("TC5: Single block message test for SHA-256.\n");
+
+ return
+ /* Write block to SHA-256. */
+ tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_init(SHA256_ADDR_CTRL) ||
+ tc_wait_valid(SHA256_ADDR_STATUS) ||
+ /* Extract the digest. */
+ tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN);
+}
+
+/* TC6: SHA-256 Double block message test as specified by NIST. */
+int TC6()
+{
+ const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 };
+ static const uint8_t block0_expected[] =
+ { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95,
+ 0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C,
+ 0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11,
+ 0xCC, 0x4B, 0x32, 0xC1, 0xF2, 0x0E, 0x53, 0x3A };
+ const uint8_t *expected = SHA256_DOUBLE_DIGEST;
+
+ printf("TC6: Double block message test for SHA-256.\n");
+
+ return
+ /* Write first block to SHA-256. */
+ tc_write(SHA256_ADDR_BLOCK, block[0], SHA256_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_init(SHA256_ADDR_CTRL) ||
+ tc_wait_valid(SHA256_ADDR_STATUS) ||
+ /* Extract the first digest. */
+ tc_expected(SHA256_ADDR_DIGEST, block0_expected, SHA256_DIGEST_LEN) ||
+ /* Write second block to SHA-256. */
+ tc_write(SHA256_ADDR_BLOCK, block[1], SHA256_BLOCK_LEN) ||
+ /* Start next block hashing, wait and check status. */
+ tc_next(SHA256_ADDR_CTRL) ||
+ tc_wait_valid(SHA256_ADDR_STATUS) ||
+ /* Extract the second digest. */
+ tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN);
+}
+
+/* TC7: SHA-256 Huge message test. */
+int TC7()
+{
+ static const uint8_t block[] =
+ { 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef,
+ 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f,
+ 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef,
+ 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f,
+ 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef,
+ 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f,
+ 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef,
+ 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f };
+
+ /* final digest after 1000 iterations */
+ static const uint8_t expected[] =
+ { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6,
+ 0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf,
+ 0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28,
+ 0xd5, 0x84, 0x2f, 0xab, 0x03, 0xa4, 0x0f, 0x2a };
+
+ int i, n = 1000;
+
+ printf("TC7: Message with %d blocks test for SHA-256.\n", n);
+
+ /* Write block data to SHA-256. */
+ if (tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN))
+ return 1;
+
+ /* Start initial block hashing, wait and check status. */
+ if (tc_init(SHA256_ADDR_CTRL) ||
+ tc_wait_ready(SHA256_ADDR_STATUS))
+ return 1;
+
+ /* First block done. Do the rest. */
+ for (i = 1; i < n; ++i) {
+ /* Start next block hashing, wait and check status. */
+ if (tc_next(SHA256_ADDR_CTRL) ||
+ tc_wait_ready(SHA256_ADDR_STATUS))
+ return 1;
+ }
+
+ /* XXX valid is probably set at the same time as ready */
+ if (tc_wait_valid(SHA256_ADDR_STATUS))
+ return 1;
+ /* Extract the final digest. */
+ return tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN);
+}
+
+/* ---------------- SHA-512 test cases ---------------- */
+
+/* TC8: Read name and version from SHA-512 core. */
+int TC8()
+{
+ uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x32 }; /* "sha2" */
+ uint8_t name1[4] = { 0x2d, 0x35, 0x31, 0x32 }; /* "-512" */
+ uint8_t version[4] = { 0x30, 0x2e, 0x38, 0x30 }; /* "0.80" */
+
+ printf("TC8: Reading name, type and version words from SHA-512 core.\n");
+
+ return
+ tc_expected(SHA512_ADDR_NAME0, name0, 4) ||
+ tc_expected(SHA512_ADDR_NAME1, name1, 4) ||
+ tc_expected(SHA512_ADDR_VERSION, version, 4);
+}
+
+/* TC9: SHA-512 Single block message test as specified by NIST.
+ We do this for all modes. */
+int tc9(int mode, const uint8_t *expected, int digest_len)
+{
+ const uint8_t *block = NIST_1024_SINGLE;
+ uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode };
+
+ return
+ /* Write block to SHA-512. */
+ tc_write(SHA512_ADDR_BLOCK, block, SHA512_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_write(SHA512_ADDR_CTRL, init, 4) ||
+ tc_wait_valid(SHA512_ADDR_STATUS) ||
+ /* Extract the digest. */
+ tc_expected(SHA512_ADDR_DIGEST, expected, digest_len);
+}
+
+int TC9()
+{
+ printf("TC9-1: Single block message test for SHA-512/224.\n");
+ if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, SHA512_224_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC9-2: Single block message test for SHA-512/256.\n");
+ if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, SHA512_256_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC9-3: Single block message test for SHA-384.\n");
+ if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, SHA384_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC9-4: Single block message test for SHA-512.\n");
+ if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, SHA512_DIGEST_LEN) != 0)
+ return 1;
+
+ return 0;
+}
+
+/* TC10: SHA-512 Double block message test as specified by NIST.
+ We do this for all modes. */
+int tc10(int mode, const uint8_t *expected, int digest_len)
+{
+ const uint8_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 };
+ uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode };
+ uint8_t next[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode };
+
+ return
+ /* Write first block to SHA-512. */
+ tc_write(SHA512_ADDR_BLOCK, block[0], SHA512_BLOCK_LEN) ||
+ /* Start initial block hashing, wait and check status. */
+ tc_write(SHA512_ADDR_CTRL, init, 4) ||
+ tc_wait_ready(SHA512_ADDR_STATUS) ||
+ /* Write second block to SHA-512. */
+ tc_write(SHA512_ADDR_BLOCK, block[1], SHA512_BLOCK_LEN) ||
+ /* Start next block hashing, wait and check status. */
+ tc_write(SHA512_ADDR_CTRL, next, 4) ||
+ tc_wait_valid(SHA512_ADDR_STATUS) ||
+ /* Extract the digest. */
+ tc_expected(SHA512_ADDR_DIGEST, expected, digest_len);
+}
+
+int TC10()
+{
+ printf("TC10-1: Double block message test for SHA-512/224.\n");
+ if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, SHA512_224_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC10-2: Double block message test for SHA-512/256.\n");
+ if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, SHA512_256_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC10-3: Double block message test for SHA-384.\n");
+ if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, SHA384_DIGEST_LEN) != 0)
+ return 1;
+
+ printf("TC10-4: Double block message test for SHA-512.\n");
+ if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, SHA512_DIGEST_LEN) != 0)
+ return 1;
+
+ return 0;
+}
+
+/* ---------------- main ---------------- */
+
+int main(int argc, char *argv[])
+{
+ typedef int (*tcfp)(void);
+ tcfp sha1_tests[] = { TC1, TC2, TC3 };
+ tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 };
+ tcfp sha512_tests[] = { TC8, TC9, TC10 };
+ tcfp all_tests[] = { TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10 };
+
+ char *usage = "Usage: %s [-h] [-d] tc...\n";
+ int i, j, opt;
+
+ while ((opt = getopt(argc, argv, "h?d")) != -1) {
+ switch (opt) {
+ case 'h':
+ case '?':
+ printf(usage, argv[0]);
+ return 0;
+ case 'd':
+ debug = 1;
+ break;
+ default:
+ fprintf(stderr, usage, argv[0]);
+ return 1;
+ }
+ }
+
+ setup_fpga();
+
+ /* no args == run all tests */
+ if (optind >= argc) {
+ for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j)
+ if (all_tests[j]() != 0)
+ return 1;
+ return 0;
+ }
+
+ for (i = optind; i < argc; ++i) {
+ if (strcmp(argv[i], "sha1") == 0) {
+ for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j)
+ if (sha1_tests[j]() != 0)
+ return 1;
+ }
+ else if (strcmp(argv[i], "sha256") == 0) {
+ for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j)
+ if (sha256_tests[j]() != 0)
+ return 1;
+ }
+ else if (strcmp(argv[i], "sha512") == 0) {
+ for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j)
+ if (sha512_tests[j]() != 0)
+ return 1;
+ }
+ else if (strcmp(argv[i], "all") == 0) {
+ for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j)
+ if (all_tests[j]() != 0)
+ return 1;
+ }
+ else if (isdigit(argv[i][0]) &&
+ (((j = atoi(argv[i])) > 0) &&
+ (j <= sizeof(all_tests)/sizeof(all_tests[0])))) {
+ if (all_tests[j - 1]() != 0)
+ return 1;
+ }
+ else {
+ fprintf(stderr, "unknown test case %s\n", argv[i]);
+ return 1;
+ }
+ }
+
+ return 0;
+}
diff --git a/src/sw/novena-fpga.c b/src/sw/novena-fpga.c
deleted file mode 100644
index 60595b7..0000000
--- a/src/sw/novena-fpga.c
+++ /dev/null
@@ -1,1031 +0,0 @@
-//#define _GNU_SOURCE // for O_DIRECT
-
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/mman.h>
-//#include <sys/types.h>
-//#include <sys/stat.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <time.h>
-#include "gpio.h"
-//#include "sd.h"
-
-/** Definitions for Novena EIM interface */
-#define CS_PIN GPIO_IS_EIM | 3
-#define MISO_PIN GPIO_IS_EIM | 0
-#define CLK_PIN GPIO_IS_EIM | 4
-#define MOSI_PIN GPIO_IS_EIM | 5
-#define POWER_PIN 17 //GPIO1_IO17
-
-static int fd = 0;
-static int *mem_32 = 0;
-static short *mem_16 = 0;
-static char *mem_8 = 0;
-static int *prev_mem_range = 0;
-
-#define FPGA_REG_OFFSET 0x08040000
-#define FPGA_CS1_REG_OFFSET 0x0C040000
-
-#define FPGA_MAP(x) ( (x - FPGA_REG_OFFSET) >> 1 )
-#define F(x) ( (x - FPGA_REG_OFFSET) >> 1 )
-#define F1(x) ( (x - FPGA_CS1_REG_OFFSET) >> 3 )
-
-#define FPGA_W_TEST0 0x08040000
-#define FPGA_W_TEST1 0x08040002
-
-#define FPGA_W_ROMULATE_CTL 0x08040010
-
-#define FPGA_R_TEST0 0x08041000
-#define FPGA_R_TEST1 0x08041002
-
-#define FPGA_R_ROMULATE_STAT 0x08041100
-#define FPGA_R_ROMULATE_CNT 0x08041102
-
-#define FPGA_R_ROMADR_STAT 0x08041104
-#define FPGA_R_ROMADR_CNT 0x08041106
-#define FPGA_R_ROMADR_DL 0x08041108
-#define FPGA_R_ROMADR_DH 0x0804110A
-
-#define FPGA_R_ROMOUT_STAT 0x0804110C
-#define FPGA_R_ROMOUT_CNT 0x0804110E
-
-#define FPGA_R_DDR3_V_MINOR 0x08041FFC
-#define FPGA_R_DDR3_V_MAJOR 0x08041FFE
-
-// burst access registers (in CS1 bank -- only 64-bit access allowed)
-#define FPGA_WB_LOOP0 0x0C040000
-#define FPGA_WB_LOOP1 0x0C040008
-
-#define FPGA_RB_LOOP0 0x0C041000
-#define FPGA_RB_LOOP1 0x0C041008
-
-#define FPGA_RB_DDR3_RD_DATA 0x0C041100
-#define FPGA_RB_DDR3_RD_STAT 0x0C041108
-
-
-int read_kernel_memory(long offset, int virtualized, int size) {
- int result;
-
- int *mem_range = (int *)(offset & ~0xFFFF);
- if( mem_range != prev_mem_range ) {
- // fprintf(stderr, "New range detected. Reopening at memory range %p\n", mem_range);
- prev_mem_range = mem_range;
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- if(virtualized) {
- fd = open("/dev/kmem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/kmem");
- fd = 0;
- return -1;
- }
- }
- else {
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return -1;
- }
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, offset&~0xFFFF);
- if( (void *)-1 == mem_32 ) {
- perror("Unable to mmap file");
-
- if( -1 == close(fd) )
- perror("Also couldn't close file");
-
- fd=0;
- return -1;
- }
- mem_16 = (short *)mem_32;
- mem_8 = (char *)mem_32;
- }
-
- int scaled_offset = (offset-(offset&~0xFFFF));
- // fprintf(stderr, "Returning offset 0x%08x\n", scaled_offset);
- if(size==1)
- result = mem_8[scaled_offset/sizeof(char)];
- else if(size==2)
- result = mem_16[scaled_offset/sizeof(short)];
- else
- result = mem_32[scaled_offset/sizeof(long)];
-
- return result;
-}
-
-#define TEST_LEN 32768
-
-void test_fpga(void) {
- volatile unsigned short *cs0;
- int i;
- unsigned short test[TEST_LEN];
- unsigned short tval;
- unsigned int iters = 0, errs = 0;
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08000000);
- cs0 = (volatile unsigned short *)mem_32;
-
- i = 0;
-// while(1) {
- for( i = 0; i < TEST_LEN; i ++ ) {
- test[i] = (unsigned short) rand();
-#if 0
- if( !(i % 16) )
- printf( "\n" );
- printf( "%04x ", test[i] );
-#endif
- }
-
- for( i = 0; i < TEST_LEN; i ++ ) {
- cs0[i] = test[i];
- }
-#if 0
- printf( "\n. . . . . . . . .\n" );
-#endif
-
- for( i = 0; i < TEST_LEN; i ++ ) {
- iters++;
-#if 0
- if( !(i % 16) )
- printf( "\n" );
- printf( "%04x ", cs0[i] );
-#else
- tval = cs0[i];
- if( test[i] != tval ) {
- printf( "\nFail at %d: wrote %04x, got %04x/%04x\n", i, test[i], tval, cs0[i] );
- errs++;
- } else {
-#if 0
- if( !(i % 16) )
- printf( "\n" );
- printf( "%04x ", test[i] );
-#endif
- }
-#endif
- }
-#if 0
- printf( "\n---------------\n" );
-#endif
- if( errs ) {
- printf( "%d iters, %d errs\n", iters, errs );
- fflush(stdout);
- }
-// }
-
-}
-
-void romulate(int onoff) {
- volatile unsigned short *cs0;
-
- if(mem_16)
- munmap(mem_16, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_16 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08040000);
- cs0 = (volatile unsigned short *)mem_16;
-
- if( onoff )
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x1;
- else
- cs0[F(FPGA_W_ROMULATE_CTL)] &= 0xFFFE;
-
-}
-
-void rom_uk(int mode) {
- volatile unsigned short *cs0;
- int i, tot;
-
- if(mem_16)
- munmap(mem_16, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_16 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08040000);
- cs0 = (volatile unsigned short *)mem_16;
-
- if( mode == 0 ) { // status update
- printf( "ROMulator UK FIFO reports %d entries, full: %d, over: %d, empty: %d\n",
- cs0[F(FPGA_R_ROMULATE_CNT)] & 0x3FF,
- cs0[F(FPGA_R_ROMULATE_STAT)] & 0x200 ? 1 : 0,
- cs0[F(FPGA_R_ROMULATE_STAT)] & 0x400 ? 1 : 0,
- cs0[F(FPGA_R_ROMULATE_STAT)] & 0x100 ? 1 : 0 );
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 1 ) { // reset count
- printf( "resetting ROMulator UK FIFO\n" );
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x4;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x4;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 2 ) { // read out
- tot = cs0[F(FPGA_R_ROMULATE_CNT)] & 0x3FF;
- i = 0;
- printf( "Reading out %d entries\n", tot );
- while( tot > 0 ) {
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x2; // pulse read
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x2;
- printf( "%d: %02x\n", i, cs0[F(FPGA_R_ROMULATE_STAT)] & 0xFF );
- i++;
- tot--;
- }
- }
-
-}
-
-void rom_adr(int mode) {
- volatile unsigned short *cs0;
- int i, tot;
-
- if(mem_16)
- munmap(mem_16, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_16 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08040000);
- cs0 = (volatile unsigned short *)mem_16;
-
- if( mode == 0 ) { // status update
- printf( "ROMulator ADR FIFO reports %d entries, full: %d, over: %d, empty: %d\n",
- cs0[F(FPGA_R_ROMADR_CNT)] & 0x3FF,
- cs0[F(FPGA_R_ROMADR_STAT)] & 0x200 ? 1 : 0,
- cs0[F(FPGA_R_ROMADR_STAT)] & 0x400 ? 1 : 0,
- cs0[F(FPGA_R_ROMADR_STAT)] & 0x100 ? 1 : 0 );
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 1 ) { // reset count
- printf( "resetting ROMulator ADR FIFO\n" );
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x10;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x10;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 2 ) { // read out
- tot = cs0[F(FPGA_R_ROMADR_CNT)] & 0x3FF;
- i = 1;
- printf( "Reading out %d entries\n", i );
- while( tot > 0 ) {
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x8; // pulse read
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x8;
- printf( "%d: %06x\n", i, ((cs0[F(FPGA_R_ROMADR_DH)] & 0xFF) << 16) |
- (cs0[F(FPGA_R_ROMADR_DL)] & 0xFFFF));
- i++;
- tot--;
- }
- }
-
-}
-
-
-void rom_out(int mode) {
- volatile unsigned short *cs0;
- int i, tot;
-
- if(mem_16)
- munmap(mem_16, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_16 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08040000);
- cs0 = (volatile unsigned short *)mem_16;
-
- if( mode == 0 ) { // status update
- printf( "ROMulator UK FIFO reports %d entries, full: %d, over: %d, empty: %d\n",
- cs0[F(FPGA_R_ROMOUT_CNT)] & 0x3FF,
- cs0[F(FPGA_R_ROMOUT_STAT)] & 0x200 ? 1 : 0,
- cs0[F(FPGA_R_ROMOUT_STAT)] & 0x400 ? 1 : 0,
- cs0[F(FPGA_R_ROMOUT_STAT)] & 0x100 ? 1 : 0 );
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 1 ) { // reset count
- printf( "resetting ROMulator out FIFO\n" );
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x40;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x40;
- printf( "ROMulator control register: %04x\n", cs0[F(FPGA_W_ROMULATE_CTL)] );
- } else if( mode == 2 ) { // read out
- tot = cs0[F(FPGA_R_ROMOUT_CNT)] & 0x3FF;
- i = 0;
- printf( "Reading out %d entries\n", tot );
- while( tot > 0 ) {
- cs0[F(FPGA_W_ROMULATE_CTL)] |= 0x20; // pulse read
- cs0[F(FPGA_W_ROMULATE_CTL)] &= ~0x20;
- printf( "%d: %02x\n", i, cs0[F(FPGA_R_ROMOUT_STAT)] & 0xFF );
- i++;
- tot--;
- }
- }
-
-}
-
-int write_kernel_memory(long offset, long value, int virtualized, int size) {
- int old_value = read_kernel_memory(offset, virtualized, size);
- int scaled_offset = (offset-(offset&~0xFFFF));
- if(size==1)
- mem_8[scaled_offset/sizeof(char)] = value;
- else if(size==2)
- mem_16[scaled_offset/sizeof(short)] = value;
- else
- mem_32[scaled_offset/sizeof(long)] = value;
- return old_value;
-}
-
-void print_usage(char *progname) {
- printf("Usage:\n"
- "%s [-h]\n"
- "\t-h This help message\n"
- "\t-s Set up FPGA comms parameter\n"
- "\t-t Test FPGA memory interface\n"
- "", progname);
-}
-
-
-//static inline int swab(int arg) {
-// return ((arg&0xff)<<24) | ((arg&0xff00)<<8) | ((arg&0xff0000)>>8) | ((arg&0xff000000)>>24);
-//}
-
-void setup_fpga() {
- int i;
- printf( "setting up EIM CS0 (register interface) pads and configuring timing\n" );
- // set up pads to be mapped to EIM
- for( i = 0; i < 16; i++ ) {
- write_kernel_memory( 0x20e0114 + i*4, 0x0, 0, 4 ); // mux mapping
- write_kernel_memory( 0x20e0428 + i*4, 0xb0b1, 0, 4 ); // pad strength config'd for a 100MHz rate
- }
-
- // mux mapping
- write_kernel_memory( 0x20e046c - 0x314, 0x0, 0, 4 ); // BCLK
- write_kernel_memory( 0x20e040c - 0x314, 0x0, 0, 4 ); // CS0
- write_kernel_memory( 0x20e0410 - 0x314, 0x0, 0, 4 ); // CS1
- write_kernel_memory( 0x20e0414 - 0x314, 0x0, 0, 4 ); // OE
- write_kernel_memory( 0x20e0418 - 0x314, 0x0, 0, 4 ); // RW
- write_kernel_memory( 0x20e041c - 0x314, 0x0, 0, 4 ); // LBA
- write_kernel_memory( 0x20e0468 - 0x314, 0x0, 0, 4 ); // WAIT
- write_kernel_memory( 0x20e0408 - 0x314, 0x0, 0, 4 ); // A16
- write_kernel_memory( 0x20e0404 - 0x314, 0x0, 0, 4 ); // A17
- write_kernel_memory( 0x20e0400 - 0x314, 0x0, 0, 4 ); // A18
-
- // pad strength
- write_kernel_memory( 0x20e046c, 0xb0b1, 0, 4 ); // BCLK
- write_kernel_memory( 0x20e040c, 0xb0b1, 0, 4 ); // CS0
- write_kernel_memory( 0x20e0410, 0xb0b1, 0, 4 ); // CS1
- write_kernel_memory( 0x20e0414, 0xb0b1, 0, 4 ); // OE
- write_kernel_memory( 0x20e0418, 0xb0b1, 0, 4 ); // RW
- write_kernel_memory( 0x20e041c, 0xb0b1, 0, 4 ); // LBA
- write_kernel_memory( 0x20e0468, 0xb0b1, 0, 4 ); // WAIT
- write_kernel_memory( 0x20e0408, 0xb0b1, 0, 4 ); // A16
- write_kernel_memory( 0x20e0404, 0xb0b1, 0, 4 ); // A17
- write_kernel_memory( 0x20e0400, 0xb0b1, 0, 4 ); // A18
-
- write_kernel_memory( 0x020c4080, 0xcf3, 0, 4 ); // ungate eim slow clocks
-
- // rework timing for sync use
- // 0011 0 001 1 001 0 001 00 00 1 011 1 0 1 1 1 1 1 1
- // PSZ WP GBC AUS CSREC SP DSZ BCS BCD WC BL CREP CRE RFL WFL MUM SRD SWR CSEN
- //
- // PSZ = 0011 64 words page size
- // WP = 0 (not protected)
- // GBC = 001 min 1 cycles between chip select changes
- // AUS = 0 address shifted according to port size
- // CSREC = 001 min 1 cycles between CS, OE, WE signals
- // SP = 0 no supervisor protect (user mode access allowed)
- // DSZ = 001 16-bit port resides on DATA[15:0]
- // BCS = 00 0 clock delay for burst generation
- // BCD = 00 divide EIM clock by 0 for burst clock
- // WC = 1 write accesses are continuous burst length
- // BL = 011 32 word memory wrap length
- // CREP = 1 non-PSRAM, set to 1
- // CRE = 0 CRE is disabled
- // RFL = 1 fixed latency reads
- // WFL = 1 fixed latency writes
- // MUM = 1 multiplexed mode enabled
- // SRD = 1 synch reads
- // SWR = 1 synch writes
- // CSEN = 1 chip select is enabled
-
- // write_kernel_memory( 0x21b8000, 0x5191C0B9, 0, 4 );
- write_kernel_memory( 0x21b8000, 0x31910BBF, 0, 4 );
-
- // EIM_CS0GCR2
- // MUX16_BYP_GRANT = 1
- // ADH = 1 (1 cycles)
- // 0x1001
- write_kernel_memory( 0x21b8004, 0x1000, 0, 4 );
-
-
- // EIM_CS0RCR1
- // 00 000101 0 000 0 000 0 000 0 000 0 000 0 000
- // RWSC RADVA RAL RADVN OEA OEN RCSA RCSN
- // RWSC 000101 5 cycles for reads to happen
- //
- // 0000 0111 0000 0011 0000 0000 0000 0000
- // 0 7 0 3 0 0 0 0
- // 0000 0101 0000 0000 0 000 0 000 0 000 0 000
-// write_kernel_memory( 0x21b8008, 0x05000000, 0, 4 );
-// write_kernel_memory( 0x21b8008, 0x0A024000, 0, 4 );
- write_kernel_memory( 0x21b8008, 0x09014000, 0, 4 );
- // EIM_CS0RCR2
- // 0000 0000 0 000 00 00 0 010 0 001
- // APR PAT RL RBEA RBEN
- // APR = 0 mandatory because MUM = 1
- // PAT = XXX because APR = 0
- // RL = 00 because async mode
- // RBEA = 000 these match RCSA/RCSN from previous field
- // RBEN = 000
- // 0000 0000 0000 0000 0000 0000
- write_kernel_memory( 0x21b800c, 0x00000000, 0, 4 );
-
- // EIM_CS0WCR1
- // 0 0 000100 000 000 000 000 010 000 000 000
- // WAL WBED WWSC WADVA WADVN WBEA WBEN WEA WEN WCSA WCSN
- // WAL = 0 use WADVN
- // WBED = 0 allow BE during write
- // WWSC = 000100 4 write wait states
- // WADVA = 000 same as RADVA
- // WADVN = 000 this sets WE length to 1 (this value +1)
- // WBEA = 000 same as RBEA
- // WBEN = 000 same as RBEN
- // WEA = 010 2 cycles between beginning of access and WE assertion
- // WEN = 000 1 cycles to end of WE assertion
- // WCSA = 000 cycles to CS assertion
- // WCSN = 000 cycles to CS negation
- // 1000 0111 1110 0001 0001 0100 0101 0001
- // 8 7 E 1 1 4 5 1
- // 0000 0111 0000 0100 0000 1000 0000 0000
- // 0 7 0 4 0 8 0 0
- // 0000 0100 0000 0000 0000 0100 0000 0000
- // 0 4 0 0 0 4 0 0
-
- write_kernel_memory( 0x21b8010, 0x09080800, 0, 4 );
- // write_kernel_memory( 0x21b8010, 0x02040400, 0, 4 );
-
- // EIM_WCR
- // BCM = 1 free-run BCLK
- // GBCD = 0 don't divide the burst clock
- write_kernel_memory( 0x21b8090, 0x701, 0, 4 );
-
- // EIM_WIAR
- // ACLK_EN = 1
- write_kernel_memory( 0x21b8094, 0x10, 0, 4 );
-
- printf( "done.\n" );
-}
-
-void setup_fpga_cs1() {
- int i;
- printf( "setting up EIM CS1 (burst interface) pads and configuring timing\n" );
- // ASSUME: setup_fpga() is already called to configure gpio mux setting.
- // this just gets the pads set to high-speed mode
-
- // set up pads to be mapped to EIM
- for( i = 0; i < 16; i++ ) {
- write_kernel_memory( 0x20e0428 + i*4, 0xb0f1, 0, 4 ); // pad strength config'd for a 200MHz rate
- }
-
- // pad strength
- write_kernel_memory( 0x20e046c, 0xb0f1, 0, 4 ); // BCLK
- // write_kernel_memory( 0x20e040c, 0xb0b1, 0, 4 ); // CS0
- write_kernel_memory( 0x20e0410, 0xb0f1, 0, 4 ); // CS1
- write_kernel_memory( 0x20e0414, 0xb0f1, 0, 4 ); // OE
- write_kernel_memory( 0x20e0418, 0xb0f1, 0, 4 ); // RW
- write_kernel_memory( 0x20e041c, 0xb0f1, 0, 4 ); // LBA
- write_kernel_memory( 0x20e0468, 0xb0f1, 0, 4 ); // WAIT
- write_kernel_memory( 0x20e0408, 0xb0f1, 0, 4 ); // A16
- write_kernel_memory( 0x20e0404, 0xb0f1, 0, 4 ); // A17
- write_kernel_memory( 0x20e0400, 0xb0f1, 0, 4 ); // A18
-
- // EIM_CS1GCR1
- // 0011 0 001 1 001 0 001 00 00 1 011 1 0 1 1 1 1 1 1
- // PSZ WP GBC AUS CSREC SP DSZ BCS BCD WC BL CREP CRE RFL WFL MUM SRD SWR CSEN
- //
- // PSZ = 0011 64 words page size
- // WP = 0 (not protected)
- // GBC = 001 min 1 cycles between chip select changes
- // AUS = 0 address shifted according to port size
- // CSREC = 001 min 1 cycles between CS, OE, WE signals
- // SP = 0 no supervisor protect (user mode access allowed)
- // DSZ = 001 16-bit port resides on DATA[15:0]
- // BCS = 00 0 clock delay for burst generation
- // BCD = 00 divide EIM clock by 0 for burst clock
- // WC = 1 write accesses are continuous burst length
- // BL = 011 32 word memory wrap length
- // CREP = 1 non-PSRAM, set to 1
- // CRE = 0 CRE is disabled
- // RFL = 1 fixed latency reads
- // WFL = 1 fixed latency writes
- // MUM = 1 multiplexed mode enabled
- // SRD = 1 synch reads
- // SWR = 1 synch writes
- // CSEN = 1 chip select is enabled
-
- // 0101 0111 1111 0001 1100 0000 1011 1 0 0 1
- // 0x5 7 F 1 C 0 B 9
-
- // 0101 0001 1001 0001 1100 0000 1011 1001
- // 5 1 9 1 c 0 B 9
-
- // 0011 0001 1001 0001 0000 1011 1011 1111
-
- write_kernel_memory( 0x21b8000 + 0x18, 0x31910BBF, 0, 4 );
-
- // EIM_CS1GCR2
- // MUX16_BYP_GRANT = 1
- // ADH = 0 (0 cycles)
- // 0x1000
- write_kernel_memory( 0x21b8004 + 0x18, 0x1000, 0, 4 );
-
-
- // 9 cycles is total length of read
- // 2 cycles for address
- // +4 more cycles for first data to show up
-
- // EIM_CS1RCR1
- // 00 000100 0 000 0 001 0 010 0 000 0 000 0 000
- // RWSC RADVA RAL RADVN OEA OEN RCSA RCSN
- //
- // 00 001001 0 000 0 001 0 110 0 000 0 000 0 000
- // RWSC RADVA RAL RADVN OEA OEN RCSA RCSN
- //
- // 0000 0111 0000 0011 0000 0000 0000 0000
- // 0 7 0 3 0 0 0 0
- // 0000 0101 0000 0000 0 000 0 000 0 000 0 000
-// write_kernel_memory( 0x21b8008, 0x05000000, 0, 4 );
- // 0000 0011 0000 0001 0001 0000 0000 0000
-
- // 0000 1001 0000 0001 0110 0000 0000 0000
- //
- write_kernel_memory( 0x21b8008 + 0x18, 0x09014000, 0, 4 );
-
- // EIM_CS1RCR2
- // 0000 0000 0 000 00 00 0 010 0 001
- // APR PAT RL RBEA RBEN
- // APR = 0 mandatory because MUM = 1
- // PAT = XXX because APR = 0
- // RL = 00 because async mode
- // RBEA = 000 these match RCSA/RCSN from previous field
- // RBEN = 000
- // 0000 0000 0000 0000 0000 0000
- write_kernel_memory( 0x21b800c + 0x18, 0x00000200, 0, 4 );
-
- // EIM_CS1WCR1
- // 0 0 000010 000 001 000 000 010 000 000 000
- // WAL WBED WWSC WADVA WADVN WBEA WBEN WEA WEN WCSA WCSN
- // WAL = 0 use WADVN
- // WBED = 0 allow BE during write
- // WWSC = 000100 4 write wait states
- // WADVA = 000 same as RADVA
- // WADVN = 000 this sets WE length to 1 (this value +1)
- // WBEA = 000 same as RBEA
- // WBEN = 000 same as RBEN
- // WEA = 010 2 cycles between beginning of access and WE assertion
- // WEN = 000 1 cycles to end of WE assertion
- // WCSA = 000 cycles to CS assertion
- // WCSN = 000 cycles to CS negation
- // 1000 0111 1110 0001 0001 0100 0101 0001
- // 8 7 E 1 1 4 5 1
- // 0000 0111 0000 0100 0000 1000 0000 0000
- // 0 7 0 4 0 8 0 0
- // 0000 0100 0000 0000 0000 0100 0000 0000
- // 0 4 0 0 0 4 0 0
-
- // 0000 0010 0000 0000 0000 0010 0000 0000
- // 0000 0010 0000 0100 0000 0100 0000 0000
-
- write_kernel_memory( 0x21b8010 + 0x18, 0x02040400, 0, 4 );
-
- // EIM_WCR
- // BCM = 1 free-run BCLK
- // GBCD = 0 divide the burst clock by 1
- // add timeout watchdog after 1024 bclk cycles
- write_kernel_memory( 0x21b8090, 0x701, 0, 4 );
-
- // EIM_WIAR
- // ACLK_EN = 1
- write_kernel_memory( 0x21b8094, 0x10, 0, 4 );
-
- printf( "resetting CS0 space to 64M and enabling 64M CS1 space.\n" );
- write_kernel_memory( 0x20e0004,
- (read_kernel_memory(0x20e0004, 0, 4) & 0xFFFFFFC0) |
- 0x1B, 0, 4);
-
- printf( "done.\n" );
-}
-
-
-#define ROM_SIZE 32768 // size in 16-bit words
-
-void rom_dump() {
- int i;
- volatile unsigned short *cs0;
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08010000);
- cs0 = (volatile unsigned short *)mem_32;
-
- for( i = 0; i < ROM_SIZE; i++ ) {
- if( (i % 16) == 0 ) {
- printf( "\n%04x: ", i*2 );
- }
- printf( "%04hx ", cs0[i] );
- }
- printf( "\n" );
-}
-
-
-void rom_upload(int infile) {
- int bytes, i;
- unsigned short data[ROM_SIZE];
- volatile unsigned short *cs0;
- int errors = 0;
-
- for( i = 0; i < ROM_SIZE; i++ )
- data[i] = 0;
-
- bytes = read(infile, data, ROM_SIZE * sizeof(unsigned short));
- if( bytes != ROM_SIZE * sizeof(unsigned short) ) {
- printf( "Note: read only %d shorts from input file\n", bytes );
- }
-
- if(mem_16)
- munmap(mem_16, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_16 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08010000);
- cs0 = (volatile unsigned short *)mem_16;
-
- // write it in
- for( i = 0; i < ROM_SIZE; i++ ) {
- cs0[i] = data[i];
- }
- // check it
- for( i = 0, errors = 0; i < ROM_SIZE; i++ ) {
- if( cs0[i] != data[i] ) {
- errors++;
- printf( "%04x: %04x , %04x\n", i, cs0[i], data[i] );
- }
- }
- if( errors )
- printf( "Found %d errors on readback check\n", errors );
- else
- printf( "ROM uploaded successfully\n" );
-}
-
-void rom_upload2(int infile) { // upload with ECC holes
- int bytes, i;
- unsigned short data[ROM_SIZE];
- volatile unsigned short *cs0;
-
- printf( "uploading a ROM with holes for ECC\n" );
- for( i = 0; i < ROM_SIZE; i++ )
- data[i] = 0;
-
- bytes = read(infile, data, ROM_SIZE * sizeof(unsigned short));
- if( bytes != ROM_SIZE * sizeof(unsigned short) ) {
- printf( "Note: read only %d shorts from input file\n", bytes );
- }
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08000000);
- cs0 = (volatile unsigned short *)mem_32;
-
- // clear memory
- for( i = 0; i < ROM_SIZE; i++ ) {
- cs0[i] = 0xFFFF;
- }
-
- for( i = 0; i + ((i / 1024) * 32) < ROM_SIZE; i++ ) {
- cs0[i + ((i / 1024) * 32)] = data[i];
- }
-
-}
-
-void rom_verify(int infile) {
- int bytes, i;
- unsigned short data[ROM_SIZE];
- volatile unsigned short *cs0;
- int errors = 0;
-
- for( i = 0; i < ROM_SIZE; i++ )
- data[i] = 0;
-
- bytes = read(infile, data, ROM_SIZE * sizeof(unsigned short));
- if( bytes != ROM_SIZE * sizeof(unsigned short)) {
- printf( "Note: read only %d shorts from input file\n", bytes );
- }
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return;
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x08000000);
- cs0 = (volatile unsigned short *)mem_32;
-
- // check it
- for( i = 0, errors = 0; i < ROM_SIZE; i++ ) {
- if( cs0[i] != data[i] )
- errors++;
- }
- if( errors )
- printf( "Found %d errors on readback check\n", errors );
- else
- printf( "No errors found on readback compare\n" );
-}
-
-
-int testcs1() {
- unsigned long long i;
- unsigned long long retval;
- volatile unsigned long long *cs1;
- unsigned long long testbuf[16];
- unsigned long long origbuf[16];
-
- setup_fpga_cs1();
-
- if(mem_32)
- munmap(mem_32, 0xFFFF);
- if(fd)
- close(fd);
-
- fd = open("/dev/mem", O_RDWR);
- if( fd < 0 ) {
- perror("Unable to open /dev/mem");
- fd = 0;
- return 0;
- }
-
- mem_32 = mmap(0, 0xffff, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x0C040000);
- cs1 = (unsigned long long *)mem_32;
-
- for( i = 0; i < 2; i++ ) {
- testbuf[i] = i | (i + 64) << 16 | (i + 8) << 32 | (i + 16) << 48 ;
- }
- testbuf[0] = 0xdeadbeeffeedfaceLL;
- // testbuf[0] = 0x0LL;
- testbuf[1] = 0x5555aaaa33339999LL;
-
-
- retval = 0;
-
- // memcpy( (void *) cs1, testbuf, 2*8);
- origbuf[0] = testbuf[0];
- origbuf[1] = testbuf[1];
- cs1[0] = testbuf[0];
- cs1[1] = testbuf[1];
-
- for( i = 0; i < 2; i++ ) {
- testbuf[i] = 0;
- }
-
- memcpy(testbuf,(void *) cs1, 8);
- memcpy(&(testbuf[1]),(void *)cs1 + 8, 8);
-
- for( i = 0; i < 2; i++ ) {
- printf( "%lld: %016llx\n", i, origbuf[i] );
- printf( "%lld: %016llx\n", i, testbuf[i] );
- }
-
- // cs1[0] = 0xdeadbeeffeedfaceLL;
- // cs1[1] = 0x12456789abcdef01LL;
- // cs1[2] = 0xf0f0f0f0f0f0f0f0LL;
- // cs1[3] = 0x12345555aaaa9876LL;
-
- return retval;
-}
-
-
-int main(int argc, char **argv) {
- int infile = -1;
-
- char *prog = argv[0];
- argv++;
- argc--;
-
- setup_fpga();
-
- if(!argc) {
- print_usage(prog);
- return 1;
- }
-
- while(argc > 0) {
- if(!strcmp(*argv, "-h")) {
- argc--;
- argv++;
- print_usage(prog);
- }
- else if(!strcmp(*argv, "-s")) {
- argc--;
- argv++;
- setup_fpga();
- // setup_fpga_cs1();
- }
- else if(!strcmp(*argv, "-t")) {
- argc--;
- argv++;
- test_fpga();
- }
- else if(!strcmp(*argv, "-v")) {
- argc--;
- argv++;
- printf( "FPGA version code: %04hx.%04hx\n",
- read_kernel_memory(FPGA_R_DDR3_V_MINOR, 0, 2),
- read_kernel_memory(FPGA_R_DDR3_V_MAJOR, 0, 2) );
- }
- else if(!strcmp(*argv, "-rd")) { // dump ROM contents
- argc--;
- argv++;
- rom_dump();
- }
- else if(!strcmp(*argv, "-rul")) { // upload a ROM image
- argc--;
- argv++;
- infile = open(*argv, O_RDONLY );
- if( infile == -1 ) {
- printf("Unable to open %s\n", *argv );
- return 1;
- }
- argc--;
- argv++;
- rom_upload(infile);
- close(infile);
- }
- else if(!strcmp(*argv, "-rcheck")) { // chek a ROM image
- argc--;
- argv++;
- infile = open(*argv, O_RDONLY );
- if( infile == -1 ) {
- printf("Unable to open %s\n", *argv );
- return 1;
- }
- argc--;
- argv++;
- rom_verify(infile);
- close(infile);
- }
- else if(!strcmp(*argv, "-rul2")) { // upload a ROM image with ECC holes
- argc--;
- argv++;
- infile = open(*argv, O_RDONLY );
- if( infile == -1 ) {
- printf("Unable to open %s\n", *argv );
- return 1;
- }
- argc--;
- argv++;
- rom_upload2(infile);
- close(infile);
- }
-
- else if(!strcmp(*argv, "-uk")) {
- argc--;
- argv++;
- rom_uk(2);
- }
- else if(!strcmp(*argv, "-uk_reset")) {
- argc--;
- argv++;
- rom_uk(1);
- }
- else if(!strcmp(*argv, "-uk_stat")) {
- argc--;
- argv++;
- rom_uk(0);
- }
-
- else if(!strcmp(*argv, "-adr")) {
- argc--;
- argv++;
- rom_adr(2);
- }
- else if(!strcmp(*argv, "-adr_reset")) {
- argc--;
- argv++;
- rom_adr(1);
- }
- else if(!strcmp(*argv, "-adr_stat")) {
- argc--;
- argv++;
- rom_adr(0);
- }
-
- else if(!strcmp(*argv, "-out")) {
- argc--;
- argv++;
- rom_out(2);
- }
- else if(!strcmp(*argv, "-out_reset")) {
- argc--;
- argv++;
- rom_out(1);
- }
- else if(!strcmp(*argv, "-out_stat")) {
- argc--;
- argv++;
- rom_out(0);
- }
-
- else if(!strcmp(*argv, "-testcs1")) {
- argc--;
- argv++;
- testcs1();
- }
- else if(!strcmp(*argv, "-romulate")) {
- argc--;
- argv++;
- romulate(1);
- }
- else if(!strcmp(*argv, "-bypass")) {
- argc--;
- argv++;
- romulate(0);
- }
- else {
- print_usage(prog);
- return 1;
- }
- }
-
- return 0;
-}
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