[Cryptech-Commits] [test/coretest_bp_entropy] 02/02: Adding the RTL source files for the BP entropy source and test system.
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Sat May 24 15:32:44 UTC 2014
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joachim at secworks.se pushed a commit to branch master
in repository test/coretest_bp_entropy.
commit b1d6b3ab96987e4ce03cfcd3467c4a424421148a
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Sat May 24 17:32:37 2014 +0200
Adding the RTL source files for the BP entropy source and test system.
---
src/rtl/coretest_bp_entropy.v | 215 ++++++++++++++++++++++++++++++++++++++++++
src/rtl/entropy.v | 172 +++++++++++++++++++++++++++++++++
src/rtl/rosc.v | 60 ++++++++++++
3 files changed, 447 insertions(+)
diff --git a/src/rtl/coretest_bp_entropy.v b/src/rtl/coretest_bp_entropy.v
new file mode 100644
index 0000000..bc8166a
--- /dev/null
+++ b/src/rtl/coretest_bp_entropy.v
@@ -0,0 +1,215 @@
+//======================================================================
+//
+// coretest_bp_entropy.v
+// ---------------------
+// Top level module for the BP FPGA entropy source tester.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2014 Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module coretest_bp_entropy(
+ input wire clk,
+ input wire reset_n,
+
+ // External interface.
+ input wire rxd,
+ output wire txd,
+
+ output wire [7 : 0] debug
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter UART_ADDR_PREFIX = 8'h00;
+ parameter ENT_ADDR_PREFIX = 8'h10;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ // Coretest connections.
+ wire coretest_reset_n;
+ wire coretest_cs;
+ wire coretest_we;
+ wire [15 : 0] coretest_address;
+ wire [31 : 0] coretest_write_data;
+ reg [31 : 0] coretest_read_data;
+ reg coretest_error;
+
+ // uart connections
+ wire uart_rxd_syn;
+ wire [7 : 0] uart_rxd_data;
+ wire uart_rxd_ack;
+ wire uart_txd_syn;
+ wire [7 : 0] uart_txd_data;
+ wire uart_txd_ack;
+ reg uart_cs;
+ reg uart_we;
+ reg [7 : 0] uart_address;
+ reg [31 : 0] uart_write_data;
+ wire [31 : 0] uart_read_data;
+ wire uart_error;
+ wire [7 : 0] uart_debug;
+
+ reg ent_cs;
+ reg ent_we;
+ reg [7 : 0] ent_address;
+ reg [31 : 0] ent_write_data;
+ wire [15 : 0] ent_read_data;
+ wire [7 : 0] ent_debug;
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignment.
+ //----------------------------------------------------------------
+ assign debug = ent_debug;
+
+
+ //----------------------------------------------------------------
+ // Core instantiations.
+ //----------------------------------------------------------------
+ coretest coretest(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .rx_syn(uart_rxd_syn),
+ .rx_data(uart_rxd_data),
+ .rx_ack(uart_rxd_ack),
+
+ .tx_syn(uart_txd_syn),
+ .tx_data(uart_txd_data),
+ .tx_ack(uart_txd_ack),
+
+ // Interface to the core being tested.
+ .core_reset_n(coretest_reset_n),
+ .core_cs(coretest_cs),
+ .core_we(coretest_we),
+ .core_address(coretest_address),
+ .core_write_data(coretest_write_data),
+ .core_read_data(coretest_read_data),
+ .core_error(coretest_error)
+ );
+
+
+ uart uart(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .rxd(rxd),
+ .txd(txd),
+
+ .rxd_syn(uart_rxd_syn),
+ .rxd_data(uart_rxd_data),
+ .rxd_ack(uart_rxd_ack),
+
+ .txd_syn(uart_txd_syn),
+ .txd_data(uart_txd_data),
+ .txd_ack(uart_txd_ack),
+
+ .cs(uart_cs),
+ .we(uart_we),
+ .address(uart_address),
+ .write_data(uart_write_data),
+ .read_data(uart_read_data),
+ .error(uart_error),
+
+ .debug(uart_debug)
+ );
+
+
+ entropy entropy(.clk(clk),
+ .nreset(reset_n),
+ .cs(ent_cs),
+ .we(ent_we),
+ .addr(ent_address),
+ .dwrite(ent_write_data),
+ .dread(ent_read_data),
+ .debug(ent_debug)
+ );
+
+
+ //----------------------------------------------------------------
+ // address_mux
+ //
+ // Combinational data mux that handles addressing between
+ // cores using the 32-bit memory like interface.
+ //----------------------------------------------------------------
+ always @*
+ begin : address_mux
+ // Default assignments.
+ coretest_read_data = 32'h00000000;
+ coretest_error = 0;
+
+ uart_cs = 0;
+ uart_we = 0;
+ uart_address = 8'h00;
+ uart_write_data = 32'h00000000;
+
+ ent_cs = 0;
+ ent_we = 0;
+ ent_address = 8'h00;
+ ent_write_data = 32'h00000000;
+
+ case (coretest_address[15 : 8])
+ UART_ADDR_PREFIX:
+ begin
+ uart_cs = coretest_cs;
+ uart_we = coretest_we;
+ uart_address = coretest_address[7 : 0];
+ uart_write_data = coretest_write_data;
+ coretest_read_data = uart_read_data;
+ coretest_error = uart_error;
+ end
+
+ ENT_ADDR_PREFIX:
+ begin
+ ent_cs = coretest_cs;
+ ent_we = coretest_we;
+ ent_address = coretest_address[7 : 0];
+ ent_write_data = coretest_write_data[15 : 0];
+ coretest_read_data = {16'h0000, ent_read_data};
+ coretest_error = 1'b0;
+ end
+
+ default:
+ begin
+ end
+ endcase // case (coretest_address[15 : 8])
+ end // address_mux
+
+endmodule // coretest_bp_entropy
+
+//======================================================================
+// EOF coretest_bp_entropy.v
+//======================================================================
diff --git a/src/rtl/entropy.v b/src/rtl/entropy.v
new file mode 100644
index 0000000..6295ef9
--- /dev/null
+++ b/src/rtl/entropy.v
@@ -0,0 +1,172 @@
+//======================================================================
+//
+// entropy.v
+// ---------
+// digital HW based entropy generator.
+//
+//
+// Author: Bernd Paysan, Joachim Strombergson
+// Copyright (c) 2014, Bernd Paysan, Secworks Sweden AB
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module entropy(input wire clk,
+ input wire nreset,
+
+ input wire cs,
+ input wire we,
+ input wire [7:0] addr,
+ input wire [15:0] dwrite,
+ output wire [15:0] dread,
+ output wire [7 : 0] debug
+ );
+
+ //----------------------------------------------------------------
+ // Symbolic names.
+ //----------------------------------------------------------------
+ // Delay in cycles between sampling random values
+ // and updating the debug port.
+ // Corresponds to about 1/10s with clock @ 50 MHz.
+ parameter DELAY_MAX = 32'h004c4b40;
+
+ parameter ADDR_ENT_WR_RNG1 = 8'h00;
+ parameter ADDR_ENT_WR_RNG2 = 8'h01;
+
+ parameter ADDR_ENT_RD_RNG1_RNG2 = 8'h10;
+ parameter ADDR_ENT_RD_P = 8'h11;
+ parameter ADDR_ENT_RD_N = 8'h12;
+
+
+ //----------------------------------------------------------------
+ // Registers.
+ //----------------------------------------------------------------
+ reg [7:0] rng1, rng2; // must be inverse to each other
+ reg [31 : 0] delay_ctr_reg;
+ reg [31 : 0] delay_ctr_new;
+ reg [7 : 0] debug_reg;
+
+
+ //----------------------------------------------------------------
+ // Wires.
+ //----------------------------------------------------------------
+ wire [15:0] p, n;
+ reg [15 : 0] tmp_dread;
+
+
+ //----------------------------------------------------------------
+ // Module instantiations.
+ //----------------------------------------------------------------
+ genvar i;
+ generate
+ for(i=0; i<16; i=i+1) begin: tworoscs
+ rosc px(clk, nreset, rng1, rng2, p[i]);
+ rosc nx(clk, nreset, rng1, rng2, n[i]);
+ end
+ endgenerate
+
+
+ //----------------------------------------------------------------
+ // Concurrent assignments to connect output ports.
+ //----------------------------------------------------------------
+ assign dread = tmp_dread;
+ assign debug = debug_reg;
+
+
+ //----------------------------------------------------------------
+ // reg updates
+ //----------------------------------------------------------------
+ always @(posedge clk or negedge nreset)
+ begin
+ if(!nreset)
+ begin
+ rng1 <= 8'h55;
+ rng2 <= 8'haa;
+ delay_ctr_reg <= 32'h00000000;
+ debug_reg <= 8'h00;
+ end
+ else
+ begin
+ delay_ctr_reg <= delay_ctr_new;
+
+ if (delay_ctr_reg == 32'h00000000)
+ begin
+ debug_reg <= n[7 : 0];
+ end
+
+ if(cs & we) begin
+ case(addr)
+ ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
+ ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
+ default:;
+ endcase
+ end
+ end // else: !if(!nreset)
+ end
+
+
+ //----------------------------------------------------------------
+ // read_data
+ //----------------------------------------------------------------
+ always @*
+ begin : read_data
+ tmp_dread = 16'h0000;
+
+ if(cs & ~we)
+ case(addr)
+ ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {rng1, rng2};
+ ADDR_ENT_RD_P: tmp_dread = p;
+ ADDR_ENT_RD_N: tmp_dread = n;
+ default:;
+ endcase
+ end
+
+
+ //----------------------------------------------------------------
+ // delay_ctr
+ //
+ // Simple counter that counts to DELAY_MAC. Used to slow down
+ // the debug port updates to human speeds.
+ //----------------------------------------------------------------
+ always @*
+ begin : delay_ctr
+ if (delay_ctr_reg == DELAY_MAX)
+ begin
+ delay_ctr_new = 32'h00000000;
+ end
+ else
+ begin
+ delay_ctr_new = delay_ctr_reg + 1'b1;
+ end
+ end // delay_ctr
+
+endmodule // entropy
+
+//======================================================================
+// EOF entropy.v
+//======================================================================
diff --git a/src/rtl/rosc.v b/src/rtl/rosc.v
new file mode 100644
index 0000000..9494261
--- /dev/null
+++ b/src/rtl/rosc.v
@@ -0,0 +1,60 @@
+//======================================================================
+//
+// rosc.v
+// ---------
+// Digital ring oscillator used as entropy source.
+//
+//
+// Author: Bernd Paysan
+// Copyright (c) 2014, Bernd Paysan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module rosc(clk, nreset, in1, in2, dout);
+ parameter l=8;
+ input clk, nreset;
+ input [l-1:0] in1, in2;
+ output reg dout;
+
+ wire cin;
+ wire [l:0] sum = in1 + in2 + cin;
+
+ assign cin = ~sum[l];
+
+ always @(posedge clk or negedge nreset)
+ if(!nreset)
+ dout <= 0;
+ else
+ dout <= sum[l];
+
+endmodule // rosc
+
+//======================================================================
+// EOF rosc.v
+//======================================================================
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