[Cryptech-Commits] [core/coretest] 01/01: Update of coretest to new, reworked parser. This fixes problems with SOC and EOC in address or data.
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Wed May 7 09:59:40 UTC 2014
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joachim at secworks.se pushed a commit to branch master
in repository core/coretest.
commit 91f7bf94ad047c067d143d7982c133da05c3092a
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Wed May 7 11:59:35 2014 +0200
Update of coretest to new, reworked parser. This fixes problems with SOC and EOC in address or data.
---
src/rtl/coretest.v | 785 ++++++++++++++++++++++++++++++++++++-----------------
1 file changed, 539 insertions(+), 246 deletions(-)
diff --git a/src/rtl/coretest.v b/src/rtl/coretest.v
index c8172a5..0c1a503 100644
--- a/src/rtl/coretest.v
+++ b/src/rtl/coretest.v
@@ -9,7 +9,7 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
@@ -65,6 +65,9 @@ module coretest(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
+ // Max elements in read and write buffers.
+ parameter BUFFER_MAX = 4'hf;
+
// Command constants.
parameter SOC = 8'h55;
parameter EOC = 8'haa;
@@ -83,14 +86,10 @@ module coretest(
// rx_engine states.
parameter RX_IDLE = 3'h0;
- parameter RX_SYN = 3'h1;
- parameter RX_ACK = 3'h2;
- parameter RX_NSYN = 3'h4;
- parameter RX_PARSE = 3'h5;
- parameter RX_CMD = 3'h6;
- parameter RX_DONE = 3'h7;
+ parameter RX_ACK = 3'h1;
+ parameter RX_NSYN = 3'h2;
- // rx_engine states.
+ // tx_engine states.
parameter TX_IDLE = 3'h0;
parameter TX_SYN = 3'h1;
parameter TX_NOACK = 3'h2;
@@ -100,7 +99,15 @@ module coretest(
// test_engine states.
parameter TEST_IDLE = 8'h00;
- parameter TEST_PARSE_CMD = 8'h10;
+ parameter TEST_GET_CMD = 8'h10;
+ parameter TEST_PARSE_CMD = 8'h11;
+ parameter TEST_GET_ADDR0 = 8'h20;
+ parameter TEST_GET_ADDR1 = 8'h21;
+ parameter TEST_GET_DATA0 = 8'h24;
+ parameter TEST_GET_DATA1 = 8'h25;
+ parameter TEST_GET_DATA2 = 8'h26;
+ parameter TEST_GET_DATA3 = 8'h27;
+ parameter TEST_GET_EOC = 8'h28;
parameter TEST_RST_START = 8'h30;
parameter TEST_RST_WAIT = 8'h31;
parameter TEST_RST_END = 8'h32;
@@ -110,9 +117,10 @@ module coretest(
parameter TEST_WR_START = 8'h60;
parameter TEST_WR_WAIT = 8'h61;
parameter TEST_WR_END = 8'h62;
- parameter TEST_UNKNOWN = 8'h80;
+ parameter TEST_CMD_UNKNOWN = 8'h80;
+ parameter TEST_CMD_ERROR = 8'h81;
parameter TEST_SEND_RESPONSE = 8'hc0;
-
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
@@ -141,10 +149,6 @@ module coretest(
reg core_we_new;
reg core_we_we;
- reg cmd_available_reg;
- reg cmd_available_new;
- reg cmd_available_we;
-
reg send_response_reg;
reg send_response_new;
reg send_response_we;
@@ -154,29 +158,59 @@ module coretest(
reg response_sent_we;
reg [7 : 0] cmd_reg;
- reg [15 : 0] core_address_reg;
- reg [31 : 0] core_write_data_reg;
+ reg [7 : 0] cmd_we;
+
+ reg [7 : 0] core_addr_byte0_reg;
+ reg core_addr_byte0_we;
+ reg [7 : 0] core_addr_byte1_reg;
+ reg core_addr_byte1_we;
+
+ reg [7 : 0] core_wr_data_byte0_reg;
+ reg core_wr_data_byte0_we;
+ reg [7 : 0] core_wr_data_byte1_reg;
+ reg core_wr_data_byte1_we;
+ reg [7 : 0] core_wr_data_byte2_reg;
+ reg core_wr_data_byte2_we;
+ reg [7 : 0] core_wr_data_byte3_reg;
+ reg core_wr_data_byte3_we;
+
reg [31 : 0] core_read_data_reg;
reg core_error_reg;
reg sample_core_output;
+
+ reg [3 : 0] rx_buffer_rd_ptr_reg;
+ reg [3 : 0] rx_buffer_rd_ptr_new;
+ reg rx_buffer_rd_ptr_we;
+ reg rx_buffer_rd_ptr_inc;
+
+ reg [3 : 0] rx_buffer_wr_ptr_reg;
+ reg [3 : 0] rx_buffer_wr_ptr_new;
+ reg rx_buffer_wr_ptr_we;
+ reg rx_buffer_wr_ptr_inc;
+
+ reg [3 : 0] rx_buffer_ctr_reg;
+ reg [3 : 0] rx_buffer_ctr_new;
+ reg rx_buffer_ctr_we;
+ reg rx_buffer_ctr_inc;
+ reg rx_buffer_ctr_dec;
+ reg rx_buffer_full;
+ reg rx_buffer_empty;
- reg [3 : 0] rx_buffer_ptr_reg;
- reg [3 : 0] rx_buffer_ptr_new;
- reg rx_buffer_ptr_we;
- reg rx_buffer_ptr_rst;
- reg rx_buffer_ptr_inc;
+ reg [7 : 0] rx_buffer [0 : 15];
+ reg rx_buffer_we;
reg [3 : 0] tx_buffer_ptr_reg;
reg [3 : 0] tx_buffer_ptr_new;
reg tx_buffer_ptr_we;
- reg tx_buffer_ptr_rst;
reg tx_buffer_ptr_inc;
-
- reg [7 : 0] rx_buffer [0 : 8];
- reg rx_buffer_we;
+ reg tx_buffer_ptr_rst;
reg [7 : 0] tx_buffer [0 : 8];
reg tx_buffer_we;
+
+ reg [3 : 0] tx_msg_len_reg;
+ reg [3 : 0] tx_msg_len_new;
+ reg tx_msg_len_we;
reg [2 : 0] rx_engine_reg;
reg [2 : 0] rx_engine_new;
@@ -194,22 +228,20 @@ module coretest(
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [7 : 0] tx_buffert_muxed0;
- reg [7 : 0] tx_buffert_muxed1;
- reg [7 : 0] tx_buffert_muxed2;
- reg [7 : 0] tx_buffert_muxed3;
- reg [7 : 0] tx_buffert_muxed4;
- reg [7 : 0] tx_buffert_muxed5;
- reg [7 : 0] tx_buffert_muxed6;
- reg [7 : 0] tx_buffert_muxed7;
- reg [7 : 0] tx_buffert_muxed8;
-
- reg extract_cmd_fields;
+ reg [7 : 0] tx_buffer_muxed0;
+ reg [7 : 0] tx_buffer_muxed1;
+ reg [7 : 0] tx_buffer_muxed2;
+ reg [7 : 0] tx_buffer_muxed3;
+ reg [7 : 0] tx_buffer_muxed4;
+ reg [7 : 0] tx_buffer_muxed5;
+ reg [7 : 0] tx_buffer_muxed6;
+ reg [7 : 0] tx_buffer_muxed7;
+ reg [7 : 0] tx_buffer_muxed8;
reg update_tx_buffer;
reg [7 : 0] response_type;
-
- reg cmd_accepted;
+
+ reg [7 : 0] rx_byte;
//----------------------------------------------------------------
@@ -223,8 +255,9 @@ module coretest(
assign core_reset_n = core_reset_n_reg & reset_n;
assign core_cs = core_cs_reg;
assign core_we = core_we_reg;
- assign core_address = core_address_reg;
- assign core_write_data = core_write_data_reg;
+ assign core_address = {core_addr_byte0_reg, core_addr_byte1_reg};
+ assign core_write_data = {core_wr_data_byte0_reg, core_wr_data_byte1_reg,
+ core_wr_data_byte2_reg, core_wr_data_byte3_reg};
//----------------------------------------------------------------
@@ -237,51 +270,65 @@ module coretest(
begin: reg_update
if (!reset_n)
begin
- rx_buffer[0] <= 8'h00;
- rx_buffer[1] <= 8'h00;
- rx_buffer[2] <= 8'h00;
- rx_buffer[3] <= 8'h00;
- rx_buffer[4] <= 8'h00;
- rx_buffer[5] <= 8'h00;
- rx_buffer[6] <= 8'h00;
- rx_buffer[7] <= 8'h00;
- rx_buffer[8] <= 8'h00;
+ rx_buffer[0] <= 8'h00;
+ rx_buffer[1] <= 8'h00;
+ rx_buffer[2] <= 8'h00;
+ rx_buffer[3] <= 8'h00;
+ rx_buffer[4] <= 8'h00;
+ rx_buffer[5] <= 8'h00;
+ rx_buffer[6] <= 8'h00;
+ rx_buffer[7] <= 8'h00;
+ rx_buffer[8] <= 8'h00;
+ rx_buffer[9] <= 8'h00;
+ rx_buffer[10] <= 8'h00;
+ rx_buffer[11] <= 8'h00;
+ rx_buffer[12] <= 8'h00;
+ rx_buffer[13] <= 8'h00;
+ rx_buffer[14] <= 8'h00;
+ rx_buffer[15] <= 8'h00;
- tx_buffer[0] <= 8'h00;
- tx_buffer[1] <= 8'h00;
- tx_buffer[2] <= 8'h00;
- tx_buffer[3] <= 8'h00;
- tx_buffer[4] <= 8'h00;
- tx_buffer[5] <= 8'h00;
- tx_buffer[6] <= 8'h00;
- tx_buffer[7] <= 8'h00;
- tx_buffer[8] <= 8'h00;
-
- rx_syn_reg <= 0;
- rx_ack_reg <= 0;
- tx_ack_reg <= 0;
- tx_syn_reg <= 0;
+ tx_buffer[0] <= 8'h00;
+ tx_buffer[1] <= 8'h00;
+ tx_buffer[2] <= 8'h00;
+ tx_buffer[3] <= 8'h00;
+ tx_buffer[4] <= 8'h00;
+ tx_buffer[5] <= 8'h00;
+ tx_buffer[6] <= 8'h00;
+ tx_buffer[7] <= 8'h00;
+ tx_buffer[8] <= 8'h00;
+
+ rx_syn_reg <= 0;
+ rx_ack_reg <= 0;
+ tx_ack_reg <= 0;
+ tx_syn_reg <= 0;
- rx_buffer_ptr_reg <= 4'h0;
- tx_buffer_ptr_reg <= 4'h0;
+ rx_buffer_rd_ptr_reg <= 4'h0;
+ rx_buffer_wr_ptr_reg <= 4'h0;
+ rx_buffer_ctr_reg <= 4'h0;
+
+ tx_buffer_ptr_reg <= 4'h0;
+ tx_msg_len_reg <= 4'h0;
- send_response_reg <= 0;
- response_sent_reg <= 0;
+ send_response_reg <= 0;
+ response_sent_reg <= 0;
- cmd_reg <= 8'h00;
- cmd_available_reg <= 0;
+ cmd_reg <= 8'h00;
+ core_addr_byte0_reg <= 8'h00;
+ core_addr_byte1_reg <= 8'h00;
+ core_wr_data_byte0_reg <= 8'h00;
+ core_wr_data_byte1_reg <= 8'h00;
+ core_wr_data_byte2_reg <= 8'h00;
+ core_wr_data_byte3_reg <= 8'h00;
- core_reset_n_reg <= 1;
- core_cs_reg <= 0;
- core_we_reg <= 0;
- core_error_reg <= 0;
- core_address_reg <= 16'h0000;
- core_write_data_reg <= 32'h00000000;
- core_read_data_reg <= 32'h00000000;
+ core_reset_n_reg <= 1;
+ core_cs_reg <= 0;
+ core_we_reg <= 0;
+ core_error_reg <= 0;
+ core_read_data_reg <= 32'h00000000;
- rx_engine_reg <= RX_IDLE;
- tx_engine_reg <= TX_IDLE;
- test_engine_reg <= TEST_IDLE;
+ rx_engine_reg <= RX_IDLE;
+ tx_engine_reg <= TX_IDLE;
+ test_engine_reg <= TEST_IDLE;
end
else
begin
@@ -300,43 +347,80 @@ module coretest(
if (rx_buffer_we)
begin
- rx_buffer[rx_buffer_ptr_reg] <= rx_data;
+ rx_buffer[rx_buffer_wr_ptr_reg] <= rx_data;
end
if (tx_buffer_we)
begin
- tx_buffer[0] <= tx_buffert_muxed0;
- tx_buffer[1] <= tx_buffert_muxed1;
- tx_buffer[2] <= tx_buffert_muxed2;
- tx_buffer[3] <= tx_buffert_muxed3;
- tx_buffer[4] <= tx_buffert_muxed4;
- tx_buffer[5] <= tx_buffert_muxed5;
- tx_buffer[6] <= tx_buffert_muxed6;
- tx_buffer[7] <= tx_buffert_muxed7;
- tx_buffer[8] <= tx_buffert_muxed8;
+ tx_buffer[0] <= tx_buffer_muxed0;
+ tx_buffer[1] <= tx_buffer_muxed1;
+ tx_buffer[2] <= tx_buffer_muxed2;
+ tx_buffer[3] <= tx_buffer_muxed3;
+ tx_buffer[4] <= tx_buffer_muxed4;
+ tx_buffer[5] <= tx_buffer_muxed5;
+ tx_buffer[6] <= tx_buffer_muxed6;
+ tx_buffer[7] <= tx_buffer_muxed7;
+ tx_buffer[8] <= tx_buffer_muxed8;
end
+
+ if (cmd_we)
+ begin
+ cmd_reg <= rx_byte;
+ end
+
+ if (core_addr_byte0_we)
+ begin
+ core_addr_byte0_reg <= rx_byte;
+ end
+
+ if (core_addr_byte1_we)
+ begin
+ core_addr_byte1_reg <= rx_byte;
+ end
+
+ if (core_wr_data_byte0_we)
+ begin
+ core_wr_data_byte0_reg <= rx_byte;
+ end
+
+ if (core_wr_data_byte1_we)
+ begin
+ core_wr_data_byte1_reg <= rx_byte;
+ end
+
+ if (core_wr_data_byte2_we)
+ begin
+ core_wr_data_byte2_reg <= rx_byte;
+ end
+
+ if (core_wr_data_byte3_we)
+ begin
+ core_wr_data_byte3_reg <= rx_byte;
+ end
- if (rx_buffer_ptr_we)
+ if (rx_buffer_rd_ptr_we)
begin
- rx_buffer_ptr_reg <= rx_buffer_ptr_new;
+ rx_buffer_rd_ptr_reg <= rx_buffer_rd_ptr_new;
end
- if (tx_buffer_ptr_we)
+ if (rx_buffer_wr_ptr_we)
begin
- tx_buffer_ptr_reg <= tx_buffer_ptr_new;
+ rx_buffer_wr_ptr_reg <= rx_buffer_wr_ptr_new;
end
-
- if (extract_cmd_fields)
+
+ if (rx_buffer_ctr_we)
begin
- cmd_reg <= rx_buffer[1];
- core_address_reg <= {rx_buffer[2], rx_buffer[3]};
- core_write_data_reg <= {rx_buffer[4], rx_buffer[5],
- rx_buffer[6], rx_buffer[7]};
+ rx_buffer_ctr_reg <= rx_buffer_ctr_new;
+ end
+
+ if (tx_buffer_ptr_we)
+ begin
+ tx_buffer_ptr_reg <= tx_buffer_ptr_new;
end
- if (cmd_available_we)
+ if (tx_msg_len_we)
begin
- cmd_available_reg <= cmd_available_new;
+ tx_msg_len_reg <= tx_msg_len_new;
end
if (core_reset_n_we)
@@ -387,6 +471,16 @@ module coretest(
end
end // reg_update
+
+ //---------------------------------------------------------------
+ // read_rx_buffer
+ // Combinatinal read mux for the rx_buffer.
+ //---------------------------------------------------------------
+ always @*
+ begin : read_rx_buffer
+ rx_byte = rx_buffer[rx_buffer_rd_ptr_reg];
+ end // read_rx_buffer
+
//---------------------------------------------------------------
// tx_buffer_logic
@@ -398,63 +492,74 @@ module coretest(
always @*
begin: tx_buffer_logic
// Defafult assignments
- tx_buffert_muxed0 = 8'h00;
- tx_buffert_muxed1 = 8'h00;
- tx_buffert_muxed2 = 8'h00;
- tx_buffert_muxed3 = 8'h00;
- tx_buffert_muxed4 = 8'h00;
- tx_buffert_muxed5 = 8'h00;
- tx_buffert_muxed6 = 8'h00;
- tx_buffert_muxed7 = 8'h00;
- tx_buffert_muxed8 = 8'h00;
-
- tx_buffer_we = 0;
+ tx_buffer_muxed0 = 8'h00;
+ tx_buffer_muxed1 = 8'h00;
+ tx_buffer_muxed2 = 8'h00;
+ tx_buffer_muxed3 = 8'h00;
+ tx_buffer_muxed4 = 8'h00;
+ tx_buffer_muxed5 = 8'h00;
+ tx_buffer_muxed6 = 8'h00;
+ tx_buffer_muxed7 = 8'h00;
+ tx_buffer_muxed8 = 8'h00;
+ tx_msg_len_new = 4'h0;
+ tx_msg_len_we = 0;
+ tx_buffer_we = 0;
if (update_tx_buffer)
begin
tx_buffer_we = 1;
- tx_buffert_muxed0 = SOR;
+ tx_buffer_muxed0 = SOR;
case (response_type)
READ_OK:
begin
- tx_buffert_muxed1 = READ_OK;
- tx_buffert_muxed2 = core_address_reg[15 : 8];
- tx_buffert_muxed3 = core_address_reg[7 : 0];
- tx_buffert_muxed4 = core_read_data_reg[31 : 24];
- tx_buffert_muxed5 = core_read_data_reg[23 : 16];
- tx_buffert_muxed6 = core_read_data_reg[15 : 8];
- tx_buffert_muxed7 = core_read_data_reg[7 : 0];
- tx_buffert_muxed8 = EOR;
+ tx_buffer_muxed1 = READ_OK;
+ tx_buffer_muxed2 = core_addr_byte0_reg;
+ tx_buffer_muxed3 = core_addr_byte1_reg;
+ tx_buffer_muxed4 = core_read_data_reg[31 : 24];
+ tx_buffer_muxed5 = core_read_data_reg[23 : 16];
+ tx_buffer_muxed6 = core_read_data_reg[15 : 8];
+ tx_buffer_muxed7 = core_read_data_reg[7 : 0];
+ tx_buffer_muxed8 = EOR;
+ tx_msg_len_new = 4'h8;
+ tx_msg_len_we = 1;
end
WRITE_OK:
begin
- tx_buffert_muxed1 = WRITE_OK;
- tx_buffert_muxed2 = core_address_reg[15 : 8];
- tx_buffert_muxed3 = core_address_reg[7 : 0];
- tx_buffert_muxed4 = EOR;
+ tx_buffer_muxed1 = WRITE_OK;
+ tx_buffer_muxed2 = core_addr_byte0_reg;
+ tx_buffer_muxed3 = core_addr_byte1_reg;
+ tx_buffer_muxed4 = EOR;
+ tx_msg_len_new = 4'h4;
+ tx_msg_len_we = 1;
end
RESET_OK:
begin
- tx_buffert_muxed1 = RESET_OK;
- tx_buffert_muxed2 = EOR;
+ tx_buffer_muxed1 = RESET_OK;
+ tx_buffer_muxed2 = EOR;
+ tx_msg_len_new = 4'h2;
+ tx_msg_len_we = 1;
end
ERROR:
begin
- tx_buffert_muxed1 = ERROR;
- tx_buffert_muxed2 = cmd_reg;
- tx_buffert_muxed3 = EOR;
+ tx_buffer_muxed1 = ERROR;
+ tx_buffer_muxed2 = cmd_reg;
+ tx_buffer_muxed3 = EOR;
+ tx_msg_len_new = 4'h3;
+ tx_msg_len_we = 1;
end
default:
begin
// Any response type not explicitly defined is treated as UNKNOWN.
- tx_buffert_muxed1 = UNKNOWN;
- tx_buffert_muxed2 = cmd_reg;
- tx_buffert_muxed3 = EOR;
+ tx_buffer_muxed1 = UNKNOWN;
+ tx_buffer_muxed2 = cmd_reg;
+ tx_buffer_muxed3 = EOR;
+ tx_msg_len_new = 4'h3;
+ tx_msg_len_we = 1;
end
endcase // case (response_type)
end
@@ -462,32 +567,84 @@ module coretest(
//----------------------------------------------------------------
- // rx_buffer_ptr
+ // rx_buffer_rd_ptr
//
- // Logic for the rx buffer pointer. Supports reset and
- // incremental updates.
+ // Logic for the rx buffer read pointer.
//----------------------------------------------------------------
always @*
- begin: rx_buffer_ptr
+ begin: rx_buffer_rd_ptr
// Default assignments
- rx_buffer_ptr_new = 4'h0;
- rx_buffer_ptr_we = 0;
+ rx_buffer_rd_ptr_new = 4'h0;
+ rx_buffer_rd_ptr_we = 1'b0;
+ rx_buffer_ctr_dec = 0;
- if (rx_buffer_ptr_rst)
+ if (rx_buffer_rd_ptr_inc)
begin
- rx_buffer_ptr_new = 4'h0;
- rx_buffer_ptr_we = 1;
+ rx_buffer_ctr_dec = 1;
+ rx_buffer_rd_ptr_new = rx_buffer_rd_ptr_reg + 1'b1;
+ rx_buffer_rd_ptr_we = 1'b1;
end
+ end // rx_buffer_rd_ptr
+
+
+ //----------------------------------------------------------------
+ // rx_buffer_wr_ptr
+ //
+ // Logic for the rx buffer write pointer.
+ //----------------------------------------------------------------
+ always @*
+ begin: rx_buffer_wr_ptr
+ // Default assignments
+ rx_buffer_wr_ptr_new = 4'h0;
+ rx_buffer_wr_ptr_we = 1'b0;
+ rx_buffer_ctr_inc = 0;
- else if (rx_buffer_ptr_inc)
+ if (rx_buffer_wr_ptr_inc)
begin
- rx_buffer_ptr_new = rx_buffer_ptr_reg + 1'b1;
- rx_buffer_ptr_we = 1;
+ rx_buffer_ctr_inc = 1;
+ rx_buffer_wr_ptr_new = rx_buffer_wr_ptr_reg + 1'b1;
+ rx_buffer_wr_ptr_we = 1'b1;
end
- end // rx_buffer_ptr
+ end // rx_buffer_wr_ptr
//----------------------------------------------------------------
+ // rx_buffer_ctr
+ //
+ // Logic for the rx buffer element counter.
+ //----------------------------------------------------------------
+ always @*
+ begin: rx_buffer_ctr
+ // Default assignments
+ rx_buffer_ctr_new = 4'h0;
+ rx_buffer_ctr_we = 1'b0;
+ rx_buffer_empty = 1'b0;
+ rx_buffer_full = 1'b0;
+
+ if (rx_buffer_ctr_inc)
+ begin
+ rx_buffer_ctr_new = rx_buffer_ctr_reg + 1'b1;
+ rx_buffer_ctr_we = 1'b1;
+ end
+ else if (rx_buffer_ctr_dec)
+ begin
+ rx_buffer_ctr_new = rx_buffer_ctr_reg - 1'b1;
+ rx_buffer_ctr_we = 1'b1;
+ end
+
+ if (rx_buffer_ctr_reg == 4'h0)
+ begin
+ rx_buffer_empty = 1'b1;
+ end
+
+ if (rx_buffer_ctr_reg == BUFFER_MAX)
+ begin
+ rx_buffer_full = 1'b1;
+ end
+ end // rx_buffer_ctr
+
+
+ //----------------------------------------------------------------
// tx_buffer_ptr
//
// Logic for the tx buffer pointer. Supports reset and
@@ -497,18 +654,18 @@ module coretest(
begin: tx_buffer_ptr
// Default assignments
tx_buffer_ptr_new = 4'h0;
- tx_buffer_ptr_we = 0;
+ tx_buffer_ptr_we = 1'b0;
- if (tx_buffer_ptr_rst)
+ if (tx_buffer_ptr_inc)
begin
- tx_buffer_ptr_new = 4'h0;
- tx_buffer_ptr_we = 1;
+ tx_buffer_ptr_new = tx_buffer_ptr_reg + 1'b1;
+ tx_buffer_ptr_we = 1'b1;
end
-
- else if (tx_buffer_ptr_inc)
+
+ else if (tx_buffer_ptr_rst)
begin
- tx_buffer_ptr_new = tx_buffer_ptr_reg + 1'b1;
- tx_buffer_ptr_we = 1;
+ tx_buffer_ptr_new = 4'h0;
+ tx_buffer_ptr_we = 1'b1;
end
end // tx_buffer_ptr
@@ -517,90 +674,55 @@ module coretest(
// rx_engine
//
// FSM responsible for handling receiving message bytes from the
- // host interface and signalling the test engine that there is
- // a new command to be executed.
+ // host interface and storing them in the receive buffer.
//----------------------------------------------------------------
always @*
begin: rx_engine
// Default assignments
- rx_ack_new = 0;
- rx_ack_we = 0;
- rx_buffer_we = 0;
- rx_buffer_ptr_rst = 0;
- rx_buffer_ptr_inc = 0;
- cmd_available_new = 0;
- cmd_available_we = 0;
- rx_engine_new = RX_IDLE;
- rx_engine_we = 0;
+ rx_ack_new = 1'b0;
+ rx_ack_we = 1'b0;
+ rx_buffer_we = 1'b0;
+ rx_buffer_wr_ptr_inc = 1'b0;
+ rx_engine_new = RX_IDLE;
+ rx_engine_we = 1'b0;
case (rx_engine_reg)
RX_IDLE:
begin
if (rx_syn_reg)
begin
- rx_buffer_we = 1;
- rx_engine_new = RX_ACK;
- rx_engine_we = 1;
+ if (!rx_buffer_full)
+ begin
+ rx_buffer_we = 1'b1;
+ rx_engine_new = RX_ACK;
+ rx_engine_we = 1'b1;
+ end
end
end
-
+
RX_ACK:
begin
- rx_ack_new = 1;
- rx_ack_we = 1;
- rx_engine_new = RX_NSYN;
- rx_engine_we = 1;
+ rx_ack_new = 1'b1;
+ rx_ack_we = 1'b1;
+ rx_buffer_wr_ptr_inc = 1'b1;
+ rx_engine_new = RX_NSYN;
+ rx_engine_we = 1'b1;
end
RX_NSYN:
begin
if (!rx_syn_reg)
begin
- rx_engine_new = RX_PARSE;
- rx_engine_we = 1;
- end
- end
-
- RX_PARSE:
- begin
- rx_ack_new = 0;
- rx_ack_we = 1;
- if (rx_buffer[rx_buffer_ptr_reg] == EOC)
- begin
- rx_engine_new = RX_DONE;
+ rx_ack_new = 1'b0;
+ rx_ack_we = 1'b1;
+ rx_engine_new = RX_IDLE;
rx_engine_we = 1;
end
- else
- begin
- rx_buffer_ptr_inc = 1;
- rx_engine_new = RX_IDLE;
- rx_engine_we = 1;
- end
end
- RX_DONE:
- begin
- cmd_available_new = 1;
- cmd_available_we = 1;
- rx_engine_new = RX_CMD;
- rx_engine_we = 1;
- end
-
- RX_CMD:
- if (cmd_accepted)
- begin
- cmd_available_new = 0;
- cmd_available_we = 1;
- rx_buffer_ptr_rst = 1;
- rx_engine_new = RX_IDLE;
- rx_engine_we = 1;
- end
-
default:
begin
- rx_buffer_ptr_rst = 1;
- rx_engine_new = RX_IDLE;
- rx_engine_we = 1;
+
end
endcase // case (rx_engine_reg)
end // rx_engine
@@ -615,8 +737,8 @@ module coretest(
always @*
begin: tx_engine
// Default assignments
- tx_buffer_ptr_rst = 0;
tx_buffer_ptr_inc = 0;
+ tx_buffer_ptr_rst = 0;
response_sent_new = 0;
response_sent_we = 0;
tx_syn_new = 0;
@@ -659,7 +781,7 @@ module coretest(
TX_NEXT:
begin
- if (tx_buffer[tx_buffer_ptr_reg] == EOR)
+ if (tx_buffer_ptr_reg == tx_msg_len_reg)
begin
tx_engine_new = TX_SENT;
tx_engine_we = 1;
@@ -684,9 +806,9 @@ module coretest(
TX_DONE:
begin
- tx_buffer_ptr_rst = 1;
response_sent_new = 0;
response_sent_we = 1;
+ tx_buffer_ptr_rst = 1;
tx_engine_new = TX_IDLE;
tx_engine_we = 1;
end
@@ -710,65 +832,216 @@ module coretest(
always @*
begin: test_engine
// Default assignments.
- core_reset_n_new = 1;
- core_reset_n_we = 0;
- core_cs_new = 0;
- core_cs_we = 0;
- core_we_new = 0;
- core_we_we = 0;
- cmd_accepted = 0;
- extract_cmd_fields = 0;
- sample_core_output = 0;
- update_tx_buffer = 0;
- response_type = 8'h00;
- send_response_new = 0;
- send_response_we = 0;
- test_engine_new = TEST_IDLE;
- test_engine_we = 0;
+ core_reset_n_new = 1;
+ core_reset_n_we = 0;
+ core_cs_new = 0;
+ core_cs_we = 0;
+ core_we_new = 0;
+ core_we_we = 0;
+ sample_core_output = 0;
+ update_tx_buffer = 0;
+ response_type = 8'h00;
+ rx_buffer_rd_ptr_inc = 0;
+ cmd_we = 0;
+ core_addr_byte0_we = 0;
+ core_addr_byte1_we = 0;
+ core_wr_data_byte0_we = 0;
+ core_wr_data_byte1_we = 0;
+ core_wr_data_byte2_we = 0;
+ core_wr_data_byte3_we = 0;
+ send_response_new = 0;
+ send_response_we = 0;
+ test_engine_new = TEST_IDLE;
+ test_engine_we = 0;
+
case (test_engine_reg)
TEST_IDLE:
begin
- if (cmd_available_reg)
+ if (!rx_buffer_empty)
begin
- extract_cmd_fields = 1;
- test_engine_new = TEST_PARSE_CMD;
- test_engine_we = 1;
+ rx_buffer_rd_ptr_inc = 1;
+ if (rx_byte == SOC)
+ begin
+ test_engine_new = TEST_GET_CMD;
+ test_engine_we = 1;
+ end
end
end
- TEST_PARSE_CMD:
+ TEST_GET_CMD:
begin
- cmd_accepted = 1;
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ cmd_we = 1;
+ test_engine_new = TEST_PARSE_CMD;
+ test_engine_we = 1;
+ end
+ end
+ TEST_PARSE_CMD:
+ begin
case (cmd_reg)
RESET_CMD:
begin
- test_engine_new = TEST_RST_START;
+ test_engine_new = TEST_GET_EOC;
test_engine_we = 1;
end
READ_CMD:
begin
- test_engine_new = TEST_RD_START;
+ test_engine_new = TEST_GET_ADDR0;
test_engine_we = 1;
end
WRITE_CMD:
begin
- test_engine_new = TEST_WR_START;
+ test_engine_new = TEST_GET_ADDR0;
test_engine_we = 1;
end
default:
begin
- // Unknown command.
- test_engine_new = TEST_UNKNOWN;
+ test_engine_new = TEST_CMD_UNKNOWN;
test_engine_we = 1;
end
endcase // case (cmd_reg)
end
-
+
+
+ TEST_GET_ADDR0:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_addr_byte0_we = 1;
+ test_engine_new = TEST_GET_ADDR1;
+ test_engine_we = 1;
+ end
+ end
+
+
+ TEST_GET_ADDR1:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_addr_byte1_we = 1;
+
+ case (cmd_reg)
+ READ_CMD:
+ begin
+ test_engine_new = TEST_GET_EOC;
+ test_engine_we = 1;
+ end
+
+ WRITE_CMD:
+ begin
+ test_engine_new = TEST_GET_DATA0;
+ test_engine_we = 1;
+ end
+
+ default:
+ begin
+ test_engine_new = TEST_CMD_UNKNOWN;
+ test_engine_we = 1;
+ end
+ endcase // case (cmd_reg)
+ end
+ end
+
+
+ TEST_GET_DATA0:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_wr_data_byte0_we = 1;
+ test_engine_new = TEST_GET_DATA1;
+ test_engine_we = 1;
+ end
+ end
+
+
+ TEST_GET_DATA1:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_wr_data_byte1_we = 1;
+ test_engine_new = TEST_GET_DATA2;
+ test_engine_we = 1;
+ end
+ end
+
+
+ TEST_GET_DATA2:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_wr_data_byte2_we = 1;
+ test_engine_new = TEST_GET_DATA3;
+ test_engine_we = 1;
+ end
+ end
+
+
+ TEST_GET_DATA3:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ core_wr_data_byte3_we = 1;
+ test_engine_new = TEST_GET_EOC;
+ test_engine_we = 1;
+ end
+ end
+
+
+ TEST_GET_EOC:
+ begin
+ if (!rx_buffer_empty)
+ begin
+ rx_buffer_rd_ptr_inc = 1;
+ if (rx_byte == EOC)
+ begin
+ case (cmd_reg)
+ RESET_CMD:
+ begin
+ test_engine_new = TEST_RST_START;
+ test_engine_we = 1;
+ end
+
+ READ_CMD:
+ begin
+ test_engine_new = TEST_RD_START;
+ test_engine_we = 1;
+ end
+
+ WRITE_CMD:
+ begin
+ test_engine_new = TEST_WR_START;
+ test_engine_we = 1;
+ end
+
+ default:
+ begin
+ test_engine_new = TEST_CMD_UNKNOWN;
+ test_engine_we = 1;
+ end
+ endcase // case (cmd_reg)
+ end
+ else
+ begin
+ test_engine_new = TEST_CMD_ERROR;
+ test_engine_we = 1;
+ end
+ end
+ end
+
+
TEST_RST_START:
begin
core_reset_n_new = 0;
@@ -776,6 +1049,7 @@ module coretest(
test_engine_new = TEST_RST_WAIT;
test_engine_we = 1;
end
+
TEST_RST_WAIT:
begin
@@ -783,6 +1057,7 @@ module coretest(
test_engine_we = 1;
end
+
TEST_RST_END:
begin
core_reset_n_new = 1;
@@ -793,6 +1068,7 @@ module coretest(
test_engine_we = 1;
end
+
TEST_RD_START:
begin
core_cs_new = 1;
@@ -801,6 +1077,7 @@ module coretest(
test_engine_we = 1;
end
+
TEST_RD_WAIT:
begin
sample_core_output = 1;
@@ -808,6 +1085,7 @@ module coretest(
test_engine_we = 1;
end
+
TEST_RD_END:
begin
core_cs_new = 0;
@@ -828,7 +1106,8 @@ module coretest(
test_engine_new = TEST_SEND_RESPONSE;
test_engine_we = 1;
end
-
+
+
TEST_WR_START:
begin
core_cs_new = 1;
@@ -839,7 +1118,8 @@ module coretest(
test_engine_new = TEST_WR_WAIT;
test_engine_we = 1;
end
-
+
+
TEST_WR_WAIT:
begin
sample_core_output = 1;
@@ -847,6 +1127,7 @@ module coretest(
test_engine_we = 1;
end
+
TEST_WR_END:
begin
core_cs_new = 0;
@@ -870,7 +1151,8 @@ module coretest(
test_engine_we = 1;
end
- TEST_UNKNOWN:
+
+ TEST_CMD_UNKNOWN:
begin
update_tx_buffer = 1;
response_type = UNKNOWN;
@@ -878,6 +1160,16 @@ module coretest(
test_engine_we = 1;
end
+
+ TEST_CMD_ERROR:
+ begin
+ update_tx_buffer = 1;
+ response_type = ERROR;
+ test_engine_new = TEST_SEND_RESPONSE;
+ test_engine_we = 1;
+ end
+
+
TEST_SEND_RESPONSE:
begin
send_response_new = 1;
@@ -890,6 +1182,7 @@ module coretest(
test_engine_we = 1;
end
end
+
default:
begin
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