[Cryptech-Commits] [core/sha1] 01/01: Adding info about the sha1 design.

git at cryptech.is git at cryptech.is
Tue Feb 25 09:23:11 UTC 2014

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joachim at secworks.se pushed a commit to branch master
in repository core/sha1.

commit 5b7e7a8aead742a4b08ceab8e70a191fc0047639
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Feb 25 10:23:02 2014 +0100

    Adding info about the sha1 design.
 README.md | 45 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 41 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 1f04420..e979b7c 100644
--- a/README.md
+++ b/README.md
@@ -13,16 +13,48 @@ takses one cycle. The W memory is based around a sliding window of 16
 32-bit registers that are updated in sync with the round processing. The
 total latency/message block is 82 cycles.
-There is a top level wrapper that provides a 32-bit memory like
-interface for easy integration into a System on Chip (SoC). This
-interface contains mesage block and digest registers to allow a host to
-load the next block while the current block is being processed.
+There are top level wrappers that provides interface for easy
+integration into a System on Chip (SoC). This interface contains mesage
+block and digest registers to allow a host to load the next block while
+the current block is being processed.
 The implementation also includes a functional model written in Python.
 ## Implementation details ##
+The sha1 design is divided into the following sections.
+- src/rtl - RTL source files
+- src/tb  - Testbenches for the RTL files
+- src/model/python - Functional model written in python
+- doc - documentation (currently not done.)
+- toolruns - Where tools are supposed to be run. Includes a Makefile for
+building and simulating the design using [Icarus Verilog](http://iverilog.icarus.com/)
+The actual core consists of the following files:
+- sha1_core.v - The core itself with wide interfaces.
+- sha1_w_mem.v - W message block memort and expansion logic.
+- sha1_k_constants.v - K constants ROM memory.
+The top level entity is called sha1_core. This entity has wide
+interfaces (512 bit block input, 160 bit digest). In order to make it
+usable you probably want to wrap the core with a bus interface.
+Unless you want to provide your own interface you therefore also need to
+select one top level wrapper. There are two wrappers provided:
+- sha1.v - A wrapper with a 32-bit memory like interface.
+- wb_sha1.v - A wrapper that implements a [Wishbone](http://opencores.org/opencores,wishbone) interface.
+***Do not include both wrappers in the same project.***
+The core (sha1_core) will sample all data inputs when given the init
+or next signal. the wrappers provided contains additional data
+registers. This allows you to load a new block while the core is
+processing the previous block.
+## FPGA-results ##
 ### Altera Cyclone FPGAs ###
 Implementation results using Altera Quartus-II 13.1.
@@ -53,6 +85,11 @@ Implementation results using Altera Quartus-II 13.1.
 ## Status ##
+Updated README with some more information about the design.
 New version of the W memory module that quite drastically improves

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