[Cryptech-Commits] [core/sha256] 01/01: Updating README with info on the design.

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joachim at secworks.se pushed a commit to branch master
in repository core/sha256.

commit e242bbecb22b37672427db9956a667ea75a435c9
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Tue Feb 25 10:10:00 2014 +0100

    Updating README with info on the design.
---
 README.md | 35 +++++++++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index b5fcd12..d27d280 100644
--- a/README.md
+++ b/README.md
@@ -11,8 +11,33 @@ there is no sharing of operations such as adders.
 The hardware implementation is complemented by a functional model
 written in Python.
 
-
-## Implementation ##
+## Implementation details ##
+The sha256 is divided into the following sections.
+- src/rtl - RTL source files
+- src/tb  - Testbenches for the RTL files
+- src/model/python - Functional model written in python
+- doc - documentation (currently not done.)
+- toolruns - Where tools are supposed to be run. Includes a Makefile for
+building and simulating the design using [Icarus Verilog](http://iverilog.icarus.com/)
+
+The actual core consists of the following files:
+- sha256_core.v - The core itself with wide interfaces.
+- sha256_w_mem.v - W message block memort and expansion logic.
+- sha256_k_constants.v - K constants ROM memory.
+
+The top level entity is called sha256_core.
+
+Unless you want to provide your own interface you also need to select
+one top level wrapper. There are two wrappers provided:
+- sha256.v - A wrapper with a 32-bit memory like interface.
+- wb_sha256.v - A wrapper that implement a [Wishbone](http://opencores.org/opencores,wishbone) interface.
+
+***Do not include both wrappers in the same project.***
+
+The core (sha256_core) will sample all data inputs when given the init
+or next signal. the wrappers provided contains additional data
+registers. This allows you to load a new block while the core is
+processing the previous block.
 
 The W-memory scheduler is based on 16 32-bit registers. Thee registers
 are loaded with the current block. After 16 rounds the contents of the
@@ -20,8 +45,10 @@ registers slide through the registers r5..r0 while the new W word is
 inserted at r15 as well as being returned to the core.
 
 
-### Cyclone IV E ###
-Implementation results using the Altera Quartus-II v13.1 design tool.
+## FPGA-results ##
+
+### Altera Cyclone FPGAs ###
+Implementation results using Altera Quartus-II 13.1.
 
 ***Cyclone IV E***
 - EP4CE6F17C6